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Static Noise margin
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Static Noise margin

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http://vlsisystemdesign.com/noise_margin.php

Noise margin is the amount of noise that a CMOS circuit could withstand without compromising the operation of circuit. Noise margin does makes sure that any signal which is logic '1' with finite noise added to it, is still recognised as logic '1' and not logic '0'. It is basically the difference between signal value and the nosie value.

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  • 1. In Out Circuit Ideal Scenario OutIn Circuit Practical Scenario
  • 2. Out In Circuit Practical ScenarioDue to the behavioral aspects of the passive components (R,L,C), the ideal characteristicsof the circuits are affected.To understand this behavior, let’s focus on below mentioned terms1. Noise Margin2. Switching Activity of CMOS
  • 3. Noise Margin1. Noise margin is the amount of noise that a CMOS circuit could withstand without compromising the operation of circuit.2. Noise margin does makes sure that any signal which is logic 1 with finite noise added to it, is still recognized as logic 1 and not logic 0.3. It is basically the difference between signal value and the noise value 3/2/2013 3
  • 4. 0 1Let’s Begin with a example, Consider a Inverter
  • 5. 0/1 1/0Input and Output of an Inverter
  • 6. 0/1 1/0Vout 0 Vin I/O Characteristic of a Inverter
  • 7. 0/1 1/0VoutVdd 0 Vdd/2 Vdd Vin Ideal I/O Characteristic of a Inverter
  • 8. 0/1 1/0Vout Infinite SlopeVdd 0 Vdd/2 Vdd Vin Ideal I/O Characteristic of a Inverter with Infinite Slope
  • 9. 0/1 1/0Vout Vout Infinite SlopeVdd Vdd 0 Vdd/2 Vdd Vin Vdd/2 Vdd Vin Actual I/O Characteristic of a Inverter with Finite Slope
  • 10. 0/1 1/0Vout Vout Infinite Slope Finite SlopeVdd Vdd 0 Vdd/2 Vdd Vin Vdd/2 Vdd Vin Actual I/O Characteristic of a Inverter with Finite Slope
  • 11. 0/1 1/0Vout Vout Infinite Slope Finite SlopeVdd Vdd VOL 0 Vdd/2 Vdd Vin Vdd/2 Vdd Vin VIL VIH VIL is Input Low Voltage => Any input voltage level between 0 and VIL will be treated as logic ‘0’
  • 12. 0/1 1/0Vout Vout Infinite Slope Finite SlopeVdd Vdd VOL 0 Vdd/2 Vdd Vin Vdd/2 Vdd Vin VIL VIH VOL is Output Low Voltage => Any output voltage level between 0 and VOL will be treated as logic ‘0’
  • 13. 0/1 1/0Vout Vout Infinite Slope Finite SlopeVdd Vdd VOL 0 Vdd/2 Vdd Vin Vdd/2 Vdd Vin VIL VIH VIH is Input High Voltage =>Any input voltage level between VIH and VDD will be treated as logic ‘1’
  • 14. 0/1 1/0Vout Vout Infinite Slope Finite SlopeVdd Vdd VOH VOL 0 Vdd/2 Vdd Vin Vdd/2 Vdd Vin VIL VIH VOH is Output High Voltage =>Any output voltage level between VOH and VDD will be treated as logic ‘1’
  • 15. 0/1 1/0Vout Vout Finite SlopeVdd Vdd VOH VOL 0 Vdd/2 Vdd Vin Vdd/2 Vdd Vin VIL VIH Actual I/O Characteristic of a Inverter
  • 16. 0/1 1/0Vout Vout Finite SlopeVdd Vdd VOH VOL 0 Vdd Vin Vdd/2 Vdd Vin VIL VIH Actual I/O Characteristic of a Inverter
  • 17. 0/1 1/0Vout Vout Finite SlopeVdd Vdd VOH VOL 0 Vdd Vin Vdd/2 Vdd Vin VIL VIH Actual I/O Characteristic of a Inverter
  • 18. 0/1 1/0Vout Vout Finite SlopeVdd Vdd VOH VOL 0 VIL Vdd Vin Vdd/2 Vdd Vin VIL VIH Actual I/O Characteristic of a Inverter
  • 19. 0/1 1/0Vout Vout Finite SlopeVdd Vdd VOH VOL 0 VIL VIH Vdd Vin Vdd/2 Vdd Vin VIL VIH Actual I/O Characteristic of a Inverter
  • 20. 0/1 1/0Vout Vout Finite SlopeVdd Vdd VOH VOL VOL 0 VIL VIH Vdd Vin Vdd/2 Vdd Vin VIL VIH Actual I/O Characteristic of a Inverter
  • 21. 0/1 1/0Vout Vout Finite SlopeVdd Vdd VOHVOH VOL VOL 0 VIL VIH Vdd Vin Vdd/2 Vdd Vin VIL VIH Actual I/O Characteristic of a Inverter
  • 22. 0/1 1/0Vout Vout Finite SlopeVdd Slope = -1 Vdd VOHVOH Slope = -1 VOL VOL 0 VIL VIH Vdd Vin Vdd/2 Vdd Vin VIL VIH Actual I/O Characteristic of a Inverter
  • 23. 0/1 1/0VoutVdd Slope = -1VOH Slope = -1 VOL 0 VIL VIH Vdd Vin I/O Characteristic plotted on Scale
  • 24. 0/1 1/0VoutVdd Slope = -1VOH Slope = -1 VOL 0 VIL VIH Vdd Vin I/O Characteristic plotted on Scale
  • 25. 0/1 1/0Vout VddVdd Slope = -1VOH Slope = -1 VOL 0 0 VIL VIH Vdd Vin I/O Characteristic plotted on Scale
  • 26. 0/1 1/0Vout Vdd VOHVdd Slope = -1VOH Slope = -1 VOL 0 0 VIL VIH Vdd Vin I/O Characteristic plotted on Scale
  • 27. 0/1 1/0Vout Vdd VOHVdd Slope = -1 VIHVOH Slope = -1 VOL 0 0 VIL VIH Vdd Vin I/O Characteristic plotted on Scale
  • 28. 0/1 1/0Vout Vdd VOHVdd Slope = -1 VIHVOH Slope = -1 VIL VOL 0 0 VIL VIH Vdd Vin I/O Characteristic plotted on Scale
  • 29. 0/1 1/0Vout Vdd VOHVdd Slope = -1 VIHVOH Slope = -1 VIL VOL VOL 0 0 VIL VIH Vdd Vin I/O Characteristic plotted on Scale
  • 30. 0/1 1/0Vout Vdd VOHVdd Slope = -1 VIHVOH Slope = -1 VIL VOL VOL 0 0 VIL VIH Vdd Vin I/O Characteristic plotted on Scale
  • 31. 0/1 1/0Vout Vdd VOHVdd Slope = -1 NMH VIH Noise Margin HighVOH Slope = -1 VIL VOL VOL 0 0 VIL VIH Vdd Vin NMH is the Noise Margin High => Any voltage level in “NMH” range will be detected as logic ‘1’
  • 32. 0/1 1/0Vout Vdd VOHVdd Slope = -1 NMH VIH Noise Margin HighVOH Slope = -1 VIL NML Noise Margin Low VOL VOL 0 0 VIL VIH Vdd Vin NML is the Noise Margin Low => Any voltage level in “NML” range will be detected as logic ‘0’
  • 33. 0/1 1/0Vout Vdd VOHVdd Slope = -1 NMH VIH Noise Margin HighVOH Slope = -1 VIL NML Noise Margin Low VOL VOL 0 0 VIL VIH Vdd Vin NMH = VOH - VIH NML = VIL - VOL
  • 34. 0/1 1/0Vout Vdd VOHVdd Slope = -1 NMH VIH Noise Margin HighVOH Undefined Region Slope = -1 VIL NML Noise Margin Low VOL VOL 0 0 VIL VIH Vdd Vin Any Signal in ‘Undefined Region’ will be indefinite logic level
  • 35. Noise Margin SummaryFor any signal to be considered as logic ‘0’ and logic ‘1’, it should be in the NML andNMH ranges, respectively 3/2/2013 35