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Leakage Power Power Reduction Techniques in VLSI Circuits by Vivek MaheshwariPresentation Transcript
REDUCTION TECHNIQUES IN
CMOS VLSI CIRCUITS”
Name: VIVEK MAHESHWARI
Branch: M.Tech (M.E.T.)
Enrl. No.: 12305161
Effect of Leakage Power in IC Industry
Types of Leakages
Modes of operation
Of Switched Capacitance
EFFECT OF LEAKAGE POWER IN IC INDUSTRY
With the rapid progress in semiconductor technology, chip density
and operation frequency have increased, making the power
consumption in battery-operated portable devices a major concern.
High power consumption reduces the battery service life. The goal
of low-power design for battery-powered devices is thus to extend
the battery service life while meeting performance requirements.
With the advent of battery operated devices and scaling trends in
deep submicron (DSM) regime, leakage power is becoming large
component of total power dissipation.
Reports indicate that 40% or even higher percentage of the total
power consumption is due to the leakage of transistors for the recent
CMOS feature sizes (e.g., 90nm and 65nm).
The combination of higher clock speeds, greater functional
integration, and smaller process geometries has contributed to
significant growth in power density.
SOURCES OF LEAKAGE POWER
Dynamic power disspation is given by,
Pd =C. V2.f
There are four main sources of leakage current in a
CMOS transistor (see Figure 1):
Reverse-biased junction leakage current (IREV)
Gate induced drain leakage (IGIDL)
Gate direct-tunneling leakage (IG)
Sub threshold (weak inversion) leakage (ISUB)
The JUNCTION LEAKAGE occurs from the source or drain to the substrate
through the reverse biased diodes when a transistor is OFF. A reversebiased pn junction leakage has two main components:
minority carrier diffusion/drift near the edge of the depletion region;
due to electron-hole pair generation in the depletion region of the reversebiased junction.
For instance, in the case of an inverter with low input voltage, the NMOS is
OFF, the PMOS is ON, and the output voltage is high. Subsequently, the
drain-to-substrate voltage of the OFF NMOS transistor is equal to the
This results in a leakage current from the drain to the substrate through the
reverse-biased diode. The magnitude of the diode’s leakage current
depends on the area of the drain diffusion and the leakage current
density, which is in turn determined by the doping concentration.
The GATE INDUCED DRAIN LEAKAGE (GIDL) is caused by high
field effect in the drain junction of MOS transistors. For an NMOS transistor
with grounded gate and drain potential at VDD, significant band bending in
multiplication and band-to-band tunneling.
A deep depletion condition is created since the holes are rapidly swept out
to the substrate. At the same time, electrons are collected by the
drain, resulting in GIDL current. This leakage mechanism is made worse by
high drain to body voltage and high drain to gate voltage.
Transistor scaling has led to increasingly steep halo implants, where the
substrate doping at the junction interfaces is increased (cf. Figure 1), while
the channel doping is low. This is done mainly to control punch-through and
drain-induced barrier lowering while having a low impact on the carrier
mobility in the channel.
The GATE LEAKAGE flows from the gate through the ―leaky‖ oxide
insulation to the substrate.
In oxide layers thicker than 3–4 nm, this kind of current results from the
Fowler-Nordheim tunneling of electrons.
For lower oxide thicknesses (which are typically 0.15µm and lower
technology nodes), however, direct tunneling through the silicon oxide layer
is the leading effect.
Mechanisms for direct tunneling include electron tunneling in the conduction
band (ECB)(most dominant), electron tunneling in the valence band
(EVB), and hole tunneling in the valence band (HVB). The magnitude of the
gate direct tunneling current increases exponentially with the gate oxide
thickness Tox and supply voltage VDD.
As transistor length and supply voltage are scaled down, gate oxide
thickness must also be reduced to maintain effective gate control over the
channel region. Unfortunately this results in an exponential increase in the
gate leakage due to direct tunneling of electrons through the gate oxide.
SUBTHRESHOLD LEAKAGE CURRENTS
When gate voltage is lower than the threshold voltage and there is a voltage
applied between drain and source of a MOS transistor, a diffusion current
appears due to the different carrier concentrations at the inversion layer in
source and drain terminals. This current depends exponentially on gate-tosource voltage VGS and drain-to-source voltage V through the carrier
For an NMOS transistor, the subthreshold current is given by,
where, µN is the electron carrier mobility,
Cox is the gate capacitance per unit area,
WN is the channel width,
LN is the channel length,
Vt is the thermal voltage, and
VTH is the threshold voltage.
The inverse slope of the subthreshold current n is given by,
where C is the depletion channel region capacitance per unit area. The
subthreshold parameter n is related to the subthreshold swing S — the gate
voltage change needed to raise the subthreshold current by one decade:
Putting It All Together
Let IOFF denote the leakage of an OFF transistor (V =0V) for an NMOS
device. From the above discussion, we know that
Clearly, IREV and IGIDL are maximized when VDB = VDD. Similarly, for
short-channel devices, ISUB increases with VDB because of the DIBL
effect. Note the IG is not a component of the OFF current, since the
transistor gate must be at a high potential with respect to the source
and substrate for this current to flow. Among the three components
of IOFF, ISUB is clearly the dominant component.
MODES OF OPERATION
On the basis of operation, the circuit blocks can be of following types:
The circuit block is said to be in active mode if it is operational and its
pattern could not be controlled
A circuit is in standby, if it is not in operation of the complete logic
some span of time.
Previous low-power techniques are primarily target reducing leakage power
consumption of CMOS circuits. Each prior technique reduces leakage
dramatically as well as some delay and area penalty. By concluding, the
previous technique, leakage is categorized into two different factors:
State destructive technique.
State savings techniques preserve the generic logic state in both active
and sleep mode, but state destructive technique save the state in active
mode, but lose the state in sleep mode. So, state destructive technique
had long wake up time while preserving the logic state.
USING SLEEP TRANSISTORS:
The most common technique for semiconductor
Dual threshold transistor stacking
SLEEPY STACK APPROACH:
It is the combined structure of sleep transistor and forced stack
method. In this method two transistors is stacking with the inverter
circuit and two sleep transistors are parallel with the inverter circuit
in both pull-up and pull-down network.
This approach works in two mode, in active mode when
S=1, S’=0, two sleep transistor is ON and if in=0 asserted, two
PMOS transistors is ON pull-up network. So, there is high internal
resistance in between the pull-up network which suppressed the
leakages the dramatically. But this approaches had an area and
propagation delay penalty.
SLEEPY KEEPER APPROACH
In sleepy keeper technique ,two sleep transistors are parallel in both pull-up
and pull-down network. These two extra sleep transistors are used to save
the logic state. The leakage reduction of this method is similarly like as the
sleep transistors technique. During the sleep mode two extra transistors are
turned ON to saving the logic state. So this is obvious
In DUAL SLEEP METHODS, two sleep transistors are parallel
similarly as in sleepy keeper. In both active and inactive mode two
sleep transistors is always ON in both pull-up and pull-down
network. So, output has an always connectivity with the Gnd and
Vdd. This is obvious state savings technique. This method has
excellent trade-offs between power, delay and area.
In DUAL THRESHOLD TRANSISTOR STACKING TECHNIQUE, the
body of one transistor is connected with the other body of transistors. So, when
one transistor is ON the threshold of another body connected transistors is also
changed. That does actually reduce the sub-threshold leakage while maintaining
the dual Vth. But this method increases propagation delay and area.
This technique is actual modification of two prior technique namely sleepy
keeper approach and dual sleep method.
Here two sleep transistors (M1 & M5) is parallel in both pull-up and pull down
network with two extra transistors(M2 & M6). This two extra transistors (M2 &
M6) is used for saving state because in both active and sleep mode M2 and M6
transistors are helps the novel circuit to make contact with output and ground.
In this architecture same aspect ratio w/l=1 is maintained in both pull-up and
network and aspect ratio w/l=6 and w/l=3 is maintained
respectively in inverter circuit (M3 & M4).
The main feature of this technique is that, M2 transistor is connected with the
power rails and M6 transistor is connected with the Gnd. So, in active mode
pull-up NMOS M2 transistor is always ON and Inactive mode pull-down PMOS
M6 transistors is always ON.
So, in both active and inactive modes, output always have connectivity with
the Vdd and Gnd, for that reason, this novel technique name is Common Vdd
During active mode, S=1 and S’=0 are asserted, and all sleep transistors (M1
M5) are turned ON. Due to the added sleep transistor, the resistance
Increases, and the propagation delay decreases and then this novel technique
reduce leakages like prior forced stack and sleep transistors technique.
Moreover, M1 and M3 transistors are ON, the internal resistance is increases
and which reduced the leakage dramatically.
REVERSE BODY BIASING (RBB) TECHNIQUE
The reverse body biasing (RBB) technique increases the threshold voltage
(Vth) of transistors during standby mode.
Figure shows the leakage current (Ileakage) components under the reverse
body-bias condition. The total leakage current in the OFF-state n-MOSFET
is given by,
MULTIPLE THRESHOLD CELLS
The high threshold transistors can suppress the subthreshold leakage
current, while the low threshold transistors are used to achieve the high
There are four classes of dual VTh designs based on how low and high
threshold voltage transistors are mixed within a logic cell :
Class 1: Using the same type of transistors (i.e., low threshold or high
in a logic cell.
Class 2: Using the same type of transistors in a pull up or pull down network.
Class 3: Using the same type of transistors in a stack of transistors.
Class 4: Mixing transistors freely.
In MTCMOS technique, a high-threshold voltage transistor is inserted in series
with the power supply and the existing design and ground. In fact, only one
type (either PMOS or NMOS) of high VTH transistor is sufficient for leakage
reduction. When in active mode, sleep transistors are turned ON, while in
standby mode sleep transistors are turned OFF by applying appropriate
voltage levels in the power gated mode, and large inserted MOSFET
increase area and delay.
These high threshold sleep transistors act as a current gate to the low
threshold designed circuit, so this technique is also referred as Power
Gating. Inserting additional sleep transistor(s) has an adverse effect on the
Therefore, sizing sleep transistors is an important design consideration. The
drain current (IDS) flowing through the NMOS sleep transistor
LONG CHANNEL DEVICES
Active leakage of CMOS gates can be reduced by increasing their transistor
channel lengths . This is because there is a V roll-off due to the Short
Channel Effect (SCE). Therefore, different threshold voltages can be
achieved by using different channel lengths.
In such technologies, it is non-trivial to control threshold voltages by using
multiple channel lengths. The longer transistor lengths used to achieve high
threshold transistors tend to increase the gate capacitance, which has a
negative impact on the performance and dynamic power dissipation.
We reviewed various sources of leakage current in CMOS integrated circuits and described a
number of proven circuit optimizations for controlling the OFF current of CMOS circuits in
both standby and active modes of circuit operation.
In way of enumerating some of the design conclusions & challenges that lie ahead, are
mentioned in the following:
Need robust subthreshold leakage control techniques that do not adversely affect the
circuit performance and layout cost.
Develop physical design tools that support multiple voltages on the chip, MTCMOS, and
adaptive supply voltage and/or body biasing.
Consider power plane integrity in light of sleep transistor insertions, accounting for both
DC voltage drop during the active mode, and ground bounce during the wakeup transition
from sleep mode.
Develop RT-level design flows and tools that allow early evaluation and insertion of power
gating structures and other leakage reduction mechanisms.
MOSFET MODELING FOR CIRCUIT ANALYSIS AND DESIGN by
Galup-Montoro and Schneider
Low-Power CMOS Circuits Technology, Logic Design and CAD
Tools by Christian Piguet
Low-Power Digital VLSI Design by Mohamed Elmasry
Standby and Active Leakage Current Control and Minimization in
CMOS VLSI Circuits by Farzan Fallah & Massoud Pedram (IEICEleakage-review-journal)
Standby Leakage Power Reduction Technique forNanoscale CMOS
VLSI Systems by HeungJun Jeon, Yong-Bin Kim, and Minsu Choi
(Senior Member, IEEE)
Analysis of Leakage Power Reduction Techniques in Digital Circuits
by Anup Jalan and Mamta Khosla