M.Tech - II Semester Supplementary April/May 2012 Examinations
(for students admitted in 2009- 10 & 2010-11 only)
FPGA ARCHITECTURES & APPLICATIONS
(Common to VLSIS, VLSISD, VLSI, VLSID & ES)
Time: 3 hours Max. Marks: 60
Answer any FIVE Questions
All Questions carry equal marks
1. (a) State the various types of PLDS available and differentiate between PAL and PLA.
(b) Implement the following Boolean function using a suitable PAL
2. (a) Differentiate between CPLD and FPGA.
(b) Explain FPGA design flow and compare FPGA design flow and ASIC design flow.
3. (a) Explain the routing architecture of an ACTEL FPGA and give the speed performance of
ACTEL- ACT-1, 2, 3.
(b) Explain the problem of initial state assignment for one-hot encoding.
4. (a) Explain the concept of meta stability and how to avoid the meta stable state in FSM.
(b) Describe the extended petrinetes for parallel controllers.
5. (a) Draw a state diagram for a sequence checker, whose output will be ‘1’ whenever the
sequence 1011 is detected. Develop a one-hot design for the same sequence checker.
(b) Explain the data path and functional partition of FSM system level design.
6. (a) Explain how a 4-bit parallel adder can be designed using four 1-bit parallel adders
using FPGA advantage tool.
(b) Discuss about front end digital design tools for FPGAs ASICs.
7. (a) List out the salient features of mentor graphics EDA tool “FPGA advantages”.
(b) Mention the applications of CPLD & FPGAs in digital design.
8. Write short note on
(a) Features of Xilinx XC 4000 & ALTERA’s FLEX 8000/10000 FPGAs
(b) Technology mapping for FPGAs.