A transmission line based technique for de-embedding noise parameters

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De-embedding of Noise Parameters

De-embedding of Noise Parameters

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  • 1. A Transmission-Line Based Technique for De-Embedding Noise ParametersKenneth H. K. Yau∗, Alain M. Mangan∗, Pascal Chevalier†, Peter Schvan‡, and Sorin P. Voinigescu∗∗Department of Electrical and Computer Engineering,University of Toronto, 10 King’s College Rd., Toronto ON, M5S 3G4, Canada†STMicroelectronics, 850 rue Jean Monnet, F-38926 Crolles, France‡NORTEL, 3500 Carling Ave., Ottawa ON, K2H 8E9, CanadaAbstract— A transmission line-based de-embedding techniquefor on-wafer S parameter measurements is extended to thenoise parameters of MOSFETs and HBTs. Since it accountsfor the distributed effects of interconnect lines and for the pad-interconnect discontinuity, it is expected to yield more accurateresults at high frequencies than existing approaches. Further-more, by requiring only two transmission line test structures tode-embed all test structures in a (Bi)CMOS process, it is oneof the most area-efficient. Experimental validation is providedon 90 nm and 130 nm n-MOSFETs and SiGe HBTs and itsaccuracy is compared with that of other lumped or distributedde-embedding techniques.I. INTRODUCTIONAccurate characterization of the noise parameters of activedevices relies on the complete removal of test structure par-asitics from the measured data. The limitations of a lumped-element approach and the need to account for the distributednature of the interconnect linking the pads with the device havebeen recognized and different techniques have recently beendeveloped based on a cascade configuration [1], [2] and a four-port parasitic model [3]. Although the techniques in [1], [3]account for the distributed effects, they require, respectively,three and five de-embedding structures for each device to becharacterized. This results in a large area overhead, long test-ing times and becomes very expensive in nano-scale CMOStechnologies. This paper expands on a recently proposedtransmission line characterization technique [4], [5], to presenta noise parameter de-embedding method that requires only twodummy structures to characterize the noise parameters of allthe test structures fabricated on a wafer. The new techniquediffers from that in [2] in the method employed to obtain thecharacteristic impedance (ZC) and the propagation constant(γ) of the transmission line. It is experimentally validated on130 nm and 90 nm n-MOSFETs and on SiGe HBTs with fT ’sof 150 GHz and 230 GHz, respectively, from two generationsof 130 nm SiGe BiCMOS processes [6], [7].II. THEORYA transistor test structure can be represented as a cascadeof three two-port networks as shown in Fig. 1. The electricaland noise properties of the input and output networks, whichare composed of the probe pads and the interconnects leadingto the transistor, are described by their two-port networkparameters and noise correlation matrices [8], with the notationdefined in Fig. 1. The transistor is represented by its owntwo-port parameters and noise correlation matrix, CiT. Two-InputDeviceOutputNetwork NetworkElectrical:Noise:YIN YT YOUTCiIN CiT CiOUTYDUT CiDUTFig. 1. A test structure modelled as a cascade of two-port networks. Thesuperscript “i” denotes the representation (A: chain, Y : admittance, etc.) ofthe noise correlation matrix.GSGGSGGSGGSG(a) (b)(c)GSGGSGDEVICElSlLl1 l2YLEFT YRIGHTFig. 2. Test structures required for noise parameter de-embedding. (a) shorttransmission line, (b) transistor test structure utilizing interconnects with thesame width at the in the input and output ports, and (c) long transmissionline.port parameter and noise correlation matrix conversions areassumed implicitly for a concise presentation. For instance,both YT and AT represent the transistor, but one is a Y -parameter representation and the other is an ABCD parameterrepresentation, likewise for CYT and CAT. Noise correlationmatrix conversions are accomplished using the formulae in [8].Figure2 describes the dummy structures required for de-embedding and defines relevant symbols.The noise parameter de-embedding technique can be sep-arated into three major steps: (1) de-embedding the probe
  • 2. pads from the transmission line test structures to obtain thecharacteristic impedance (ZC) and propagation constant (γ),(2) splitting the short transmission line into two halves asillustrated in Fig. 2(a) and determining the matrices YLEFTand YRIGHT, and (3) calculate the electrical and noisematrices of the input and output networks (i.e. YIN/OUTand CYIN/OUT) and de-embed their contributions from themeasured noise parameters. The remainder of this section shalldescribe each of the three steps in sequence.A. De-embedding the Transmission Line Test StructuresFor simplicity, the interconnects at the input and output ofthe transistor are assumed to have the same width. A methodto remove this restriction will be illustrated at the end of thelast subsection.In this work, the interconnects from the probe pads to thetransistor are characterized as transmission lines. ZC and γ ofthe interconnects are determined from two transmission linetest structures of different lengths, but having the same widthas the interconnects, using the technique described in [4].B. Splitting Short Transmission Line Test StructureSplitting the short transmission line test structure and calcu-lating the electrical matrices of the two halves form the basisof the noise parameter de-embedding technique. The methodused was presented in [5] and summarized in the remainderof this subsection.From transmission line theory, the Y -parameters of a trans-mission line of length l are given by [9]Y =1ZCcoth γl −cschγl−cschγl coth γl. (1)If the transmission line is short such that |γl| 1, then thehyperbolic functions can be approximated by the first non-zeroterm of their Maclaurin series expansion [5]. By approximatingthe probe pads as lumped elements (YP ) and accounting forthe pad-line discontinuity through (ZD) as illustrated in Fig. 3,it can be shown that the Y -parameter matrix of the left half ofthe short transmission line, including the probe pads, is givenby [5]YLEFT =yS11 − yS12 − γlS4ZC2yS122yS12γlS4ZC− 2yS12, (2)where ySij are the measured Y -parameters of the shorttransmission line test structure before de-embedding and lSis the length of the short transmission line. Since the leftand right halves are mirror images of each other, YRIGHTcan be obtained by simultaneously interchanging the rows andcolumns of YLEFT asYRIGHT = P × YLEFT × P, (3)where P is the permutation matrixP =0 11 0. (4)TRANSMISSION LINEY1 Y2Y3YPYP ZDZDFig. 3. Equivalent circuit model of a transmission line test structure. Note thatthe lumped pad approximation is the only assumption made. Any transmissionline can be represented exactly by the π-network inside the dashed boxby frequency dependent impedances, although the impedances may not berealizable with physical R, L, and C elements.Since the short transmission line test structure is symmetric,its S-parameter matrix should also be symmetric. However,because of measurement errors, this is strictly not the case. Inthis work, the measurement error is handled by averaging themeasured S-parameter matrix according tos11 = s22 =s11 + s222(5)s12 = s21 =s12 + s212, (6)where the quantities without primes are the measured values.The averaged S-parameter matrices are used in (2) to calculateYLEFT.C. De-embedding Noise ParametersThe Y -parameter matrices of the input (YIN) and outputnetworks (YOUT) have to be determined in order to de-embedthe measured noise parameters. Based on the transmissionline de-embedding technique summarized in section II-A, theinput network is obtained by appending (or subtracting) atransmission line of length |l1 − lS/2| to the network repre-sented YLEFT. Likewise, the matrix of the output networkis calculated by appending (or subtracting) a |l2 − lS/2| longline to YRIGHT. Mathematically,AIN = ALEFT × Al1−lS /2 (7)AOUT = Al2−lS /2 × ARIGHT, (8)where Al1−lS /2 and Al2−lS /2, respectively, are ABCD ma-trices of intrinsic transmission lines of lengths l1 − lS/2and l2 − lS/2 obtained from (1). Note that if l1 − lS/2and/or l2 − lS/2 is negative, the above equations elegantlysubtract the appropriate transmission length from ALEFTand/or ARIGHT.Since the input and output networks are passive, their noisecorrelation matrices can be determined from their Y -parametermatrices as in [10]CYIN/OUT = kBT YIN/OUT + Y†IN/OUT , (9)where †represents the conjugate-transpose (adjoint) operation.This equation, which reduces to 2kBT {Y} if the real part
  • 3. of the Y -parameter matrix is symmetric, ensures that the noisematrix is also symmetric even in the presence of measurementerrors.Having determined both the electrical and noise matricesof the input and output networks, the chain noise correlationmatrix of the transistor from which the de-embedded noiseparameters are calculated can be isolated as [8], [11]CAT = A−1IN CADUT − CAIN A†IN−1− ATCAOUTA†T.(10)AT is the ABCD parameter matrix of the transistor and canbe calculated asAT = A−1INADUTA−1OUT (11)and CADUT is reconstructed from the measured noise param-eters of the test structure using the formulae in [8], [11].An additional pair of long and short transmission linetest structures is necessary to remove the restriction that theinterconnects at the input and output of the transistor haveidentical widths. AIN and CYIN are determined from the pairof transmission line test structures that have the same linewidth as the input interconnect. Likewise, AOUT and CYOUTare obtained from the lines whose width is identical to thatof the output interconnect. The de-embedding technique willotherwise remain unchanged.III. RESULTS AND DISCUSSIONVerification of the proposed de-embedding technique isprovided in two steps. First, electromagnetic simulations areemployed to assess the accuracy of using (2) to split the shorttransmission line test structure. Next, the noise parameter de-embedding technique is verified experimentally on 90 nm and130 nm n-MOSFETs and SiGe HBTs and compared to existingtechniques.A. Three Dimensional Electromagnetic SimulationsThe error assoicated with using the approximation in (2)to split the short transmission line test structure was assessedusing 3-D electromagnetic simulations. The S-parameters ofthe long and short transmission line test structures, togetherwith the pads, were calculated using Ansoft HFSS. Thetransmission line de-embedding technique in [4] was appliedto the simulated S-parameters to extract ZC and γ, and (2)was applied to split the short transmission line test structure.The simulated test structures have 40 × 40µm2signal pads.The length of the long line (lL) is 600µm, while that of theshort line (lS) is 100µm. The transmission lines are 5µm wideand 0.9µm thick and the dielectric is 7µm thick.The S-parameters calculated from (2) are compared withthose obtained directly from HFSS simulations in Figs. 4-6.The errors for the real and imaginary parts of each of theS-parameters are summarized in Table II. A validation ofthis de-embedding technique on the measured Y -parametersof MOSFETs, SiGe HBTs, inductors and varactors in the upto 65 GHz range will be presented in [12]. Below, we focusonly on noise parameter measurements.-0.20-0.15-0.10-0.050.000.050.10REAL(S11),REAL(S22)100806040200FREQUENCY (GHz)REAL(S11)REAL(S22)HFSS SIMULATEDCALCULATEDFig. 4. Real parts of s11 and s22 of the left half of the splitted shorttransmission line test structure as calculated from (2): solid line and directlyfrom HFSS simulations: symbols.-0.20-0.15-0.10-0.050.00IMAG(S11),IMAG(S22)100806040200FREQUENCY (GHz)IMAG(S11)IMAG(S22)HFSS SIMULATEDCALCULATEDFig. 5. Imaginary parts of s11 and s22 of the left half of the splitted shorttransmission line test structure as calculated from (2): solid line and directlyfrom HFSS simulations: symbols.1.000.950.900.850.80REAL(S12)100806040200FREQUENCY (GHz)-0.5-0.4-0.3-0.2-0.10.0IMAG(S12)HFSS SIMULATEDCALCULATEDFig. 6. s12 of the left half of the splitted short transmission line teststructure as calculated from (2): solid line and directly from HFSS simulations:symbols.TABLE IPERCENTAGE ERROR IN THE S-PARAMETERS DUE TO (2)Real 100 GHz 50 GHz Imag 100 GHz 50 GHzs11 134.5% 60.2% s11 8.28% 0.48%s22 19.13% 25.29% s22 4.68% 4.72%s12 0.48% 0.103% s12 2.26% 1.08%B. Experimental VerificationFigure 7 is a die photo of the SiGe HBT and n-MOSFET teststructures and the necessary dummy structures fabricated to
  • 4. TABLE IIABSOLUTE ERROR IN THE S-PARAMETERS DUE TO (2)100 GHz 50 GHz 100 GHz 50 GHzReal (×10−3) (×10−3) Imag (×10−3) (×10−3)s11 12.8 4.6 s11 9.7 0.3s22 16.0 4.6 s22 3.1 2.1s12 4.3 1.0 s12 9.8 2.4TABLE IIITEST STRUCTURE AND DEVICE GEOMETRIESWE/lG lE/WF NE/NF l1 l2Tech./Device (µm) (µm) - (µm) (µm)90 nm (n-FET) 0.1 1 80 34.935 34.555130 nm (n-FET) 0.13 1 80 43.83 45.225HBT [6]/ [13] 0.17/0.13 2.5 3 44.91 42.335validate the new de-embedding technique. The geometries ofthe devices are summarized in Table III. All the test structuresemploy a M1 ground shield with abundant substrate PTAPs toreduce the substrate loss, as indicated by the shaded region inFig. 2. The ground planes are slotted to comply with the metaldensity rules in nano-scale CMOS technologies.S-parameters and noise parameters were measured on-waferusing a Wiltron 360B VNA, a Focus Microwaves tuner and aHP8971C noise figure test set. The open-short technique [14],the transmission line-based technique in [2] and the proposedtechnique were used to de-embed measured noise parameters.The measurement results summarized in Figs. 8-11 indicatethat there is negligible difference between the three techniquesfor all noise parameters of SiGe HBTs and n-MOSFETs upto 26 GHz. This is expected, showing that the new techniqueagrees with previously published ones at low frequencieswhile consuming less silicon area. Note that the same pairof transmission lines is used to de-embed both the 130 nmMOSFETs and SiGe HBTs. The difference between the open-short technique and the new technique is expected to increasewith frequency, since the lumped-element approximation willgradually fail as distributive effects become important.Another observation is that the differences between theraw data and the de-embedded results are smaller for the90 nm MOSFETs (Figs. 12-13) than for the 130 nm HBTsand MOSFETs (Figs. 8-11). In the 90 nm CMOS test chip,a metal 1 ground plane extends throughout the test structure,including under the high speed signal pads. In contrast, thesignal pads in the 130 nm designs do not have a metal 1ground shield directly underneath. This introduces extra losses,which translate into a higher measured noise figure of thetest structure before de-embedding. While this loss can be de-embedded, measurement accuracy improves when the parasiticlosses are minimized.The importance of employing a ground plane is moreevident by comparing the de-embedded NFMIN of two gener-ations of SiGe HBTs with exactly the same interconnect andpad layouts. Shown in Fig. 14 are the de-embedded NFMINdata for two generations of SiGe HBTs [6], [13]. The NFMINof the newer generation HBT, [13] remains below 0.6 dB up toFig. 7. Die photos of 90 nm CMOS (top) and 130 nm BiCMOS (bottom)test structures. Note that only one pair of transmission lines is necessary ineach technology.22 GHz but exhibits significant fluctuations after the pad andinterconnect losses are de-embedded due to a relatively largercontribution from the parasitics to the measured noise figure.Finally, Fig. 14 confirms that the optimum noise bias ofan n-MOSFET remains constant across frequencies, consistentwith the results reported in [15]. The minimum noise bias ofthe 150 GHz SiGe HBT in [6] shifts to higher current densitieswith increasing frequency. However, this trend is drowned inthe relatively larger scatter in NFMIN data for the 230 GHzSiGe HBT in [13] due to the aforementioned parasitic lossesand due to the device noise figure being lower than 1 dB.
  • 5. 43210NFMIN(dB)262422201816141210FREQUENCY (GHz)5040302010Rn(Ω)RAW DATAT-LINEREF [2]OPEN-SHORTFig. 8. NFMIN and Rn of the 130 nm n-FET. JD = 0.15mA/µm andVDS=1 V10080604020REAL(ZSOPT)(Ω)262422201816141210FREQUENCY706050403020100IMAG(ZSOPT)(Ω)RAW DATAT-LINEREF [2]OPEN-SHORTFig. 9. ZSOP T of the 130 nm n-FET. JD = 0.15mA/µm and VDS=1 V543210NFMIN(dB)262422201816141210FREQUENCY (GHz)50403020100Rn(Ω)RAW DATAT-LINEREF [2]OPEN-SHORTFig. 10. NFMIN and Rn of the SiGe HBT [6]. IC = 1mA and VCE=1 VIV. CONCLUSIONSA transmission line de-embedding technique was extendedto de-embed the noise parameters of FETs and HBTs. Itsaccuracy was assessed using electromagnetic simulations andtested experimentally on 90 nm and 130 nm n-MOSFETs andon 150 GHz and 230 GHz SiGe HBTs from two generationsof SiGe BiCMOS processes. Measurement results indicate thatthis technique agrees with existing ones up to 26 GHz, whileconsuming less silicon area and requiring fewer dummy teststructures and fewer S-parameter measurements. Furthermore,compared to existing lumped element-based de-embeddingtechniques, because of its distributed nature, its accuracy200150100500REAL(ZSOPT)(Ω)262422201816141210FREQUENCY (GHz)80706050403020100IMAG(ZSOPT)(Ω)RAW DATAT-LINEREF [2]OPEN-SHORTFig. 11. ZSOP T of the SiGe HBT [6]. IC = 1mA and VCE=1 V43210NFMIN(dB)262422201816141210FREQUENCY (GHz)1816141210Rn(W)RAW DATAT-LINEFig. 12. NFMIN and Rn of the 90 nm n-FET. JD = 0.15mA/µm andVDS=0.7 V70605040302010REAL(ZSOPT)(W)262422201816141210FREQUENCY (GHz)6050403020100IMAG(ZSOPT)(W)RAW DATAT-LINEFig. 13. ZSOP T of the 90 nm n-FET. JD = 0.15mA/µm and VDS=0.7 Vis expected to be better at higher frequencies. Finally, theimportance of minimizing the parasitic losses of the teststructures for accurate measurements was also demonstrated.ACKNOWLEDGEMENTSThe authors would like to acknowledge STMicroelectronicsfor fabrication and NORTEL for funding.REFERENCES[1] C.-H. Chen and M. J. Deen, “A general procedure for high-frequencynoise parameter de-embedding of MOSFETs by taking the capacitiveeffects of metal interconnections into account,” in IEEE InternationalConference on Microelectronic Test Structures, Mar. 2001, pp. 109–114.
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