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# Lect10_Analog Layout and Process Concern

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• 1. Analog Layout and Process Concern 授課教師 : 顏志仁 博士
• 2.
• Introduction
• Integrated-Circuit Devices and Modeling
• Modern CMOS Process
• Analog Layout Considerations
• SPICE Simulation
Contents
• 3. References
• P. E. Allen and D. R. Holberg, “ CMOS Analog Circuit Design ”, Oxford University Press, 2002.
• D. A. Johns and K. Martin, “ Analog Integrated Circuit Design ”, John Wiely & Sons, 1997.
• R. Gregorian, “ Introduction to CMOS Op-Amps and Comparators ”, John Wiely & Sons, 1999.
• 5. Major Functions of Analog ICs
• Provide interfaces between the analog environment of the physical world and a digital environment.
• – amplification
• – filtering
• – analog-to-digital conversion
• – digital-to-analog conversion
• – power supply conditioning
• Sometimes integrated with digital VLSI circuits for better performance or lower cost.
Introduction 2 C.–J. Yen Analog Layout and Process Concern
• 6. Signals
• An analog signal is defined over a
• continuous range of time and a continuous
• range of amplitudes.
• A digital signal is defined only at discrete
• values of time and amplitude.
• D = b 1 2 -1 + b 2 2 -2 +b 3 2 -3 + ·····b N 2 -N =
• An analog sampled-data signal is defined
• over a continuous range of amplitudes but
• only at discrete values of time.
Introduction 3 C.–J. Yen Analog Layout and Process Concern
• 7. Bandwidths of Signals Introduction 4 C.–J. Yen Analog Layout and Process Concern
• 8. Signal Bandwidths can be Processed Introduction 5 C.–J. Yen Analog Layout and Process Concern
• 9. Digitization of a Nature Signal Introduction 6 C.–J. Yen Analog Layout and Process Concern
• 10. Symbols for MOS Transistors Integrated-Circuit Devices and Modeling Commonly used symbols for p-channel transistors. Commonly used symbols for n-channel transistors. 7 C.–J. Yen Analog Layout and Process Concern
• 11. Cross Section of a MOS Transistor 8 Integrated-Circuit Devices and Modeling A cross section of a typical n-channel transistor. C.–J. Yen Analog Layout and Process Concern
• 12. N-Channel MOS Transistor (V G << 0) 9 Integrated-Circuit Devices and Modeling V G << 0 resulting in an accumulated channel (no current flow). C.–J. Yen Analog Layout and Process Concern
• 13. N-Channel MOS Transistor (V G >> 0) 10 Integrated-Circuit Devices and Modeling The channel is present (current flow possible from drain to source). C.–J. Yen Analog Layout and Process Concern
• 14. Dimensions of a MOS Transistor 11 Integrated-Circuit Devices and Modeling C.–J. Yen Analog Layout and Process Concern
• 15. Channel Charge Density 12 Integrated-Circuit Devices and Modeling C.–J. Yen Analog Layout and Process Concern
• 16. Pinch Off 13 Integrated-Circuit Devices and Modeling C.–J. Yen Analog Layout and Process Concern
• 17. I D -V DS Curve for a MOS Transistor 14 Integrated-Circuit Devices and Modeling C.–J. Yen Analog Layout and Process Concern
• 18. I D -V DS Curve for Different V GS 15 Integrated-Circuit Devices and Modeling C.–J. Yen Analog Layout and Process Concern
• 19. Weak Inversion 16 Integrated-Circuit Devices and Modeling if and then is a characteristic current C.–J. Yen Analog Layout and Process Concern
• 20. Moderate Inversion 17 Integrated-Circuit Devices and Modeling C.–J. Yen Analog Layout and Process Concern
• 21. Transfer Characteristics of Temperature 18 Integrated-Circuit Devices and Modeling C.–J. Yen Analog Layout and Process Concern
• 22. Small-Signal Capacitances 19 Integrated-Circuit Devices and Modeling C.–J. Yen Analog Layout and Process Concern
• 23. Small-Signal Model in Active Region 20 Integrated-Circuit Devices and Modeling C.–J. Yen Analog Layout and Process Concern
• 24. MOS Transistor Equations in Active Region 21 Integrated-Circuit Devices and Modeling C.–J. Yen Analog Layout and Process Concern
• 25. Small-Signal Model in Triode Region 22 Integrated-Circuit Devices and Modeling C.–J. Yen Analog Layout and Process Concern
• 26. MOS Transistor Equations in Triode Region 23 Integrated-Circuit Devices and Modeling C.–J. Yen Analog Layout and Process Concern
• 27. MOS Parameters for a 0.8- μ m Technology 24 Integrated-Circuit Devices and Modeling C.–J. Yen Analog Layout and Process Concern
• 28. SPICE Parameters for Modeling BJTs 25 Integrated-Circuit Devices and Modeling C.–J. Yen Analog Layout and Process Concern
• 29. Simple CMOS Logic Circuits 26 Modern CMOS Process C.–J. Yen Analog Layout and Process Concern
• 30. Cross Section of the CMOS IC 27 Modern CMOS Process C.–J. Yen Analog Layout and Process Concern
• 31. SiO 2 and Si 3 N 4 28 Modern CMOS Process
• Following initial cleaning, an SiO 2 layer is thermally grown on the silicon
• substrate. A Si 3 N 4 layer is then deposited by LPCVD. Photoresist is spun on
• the wafer to prepare for mask 1 operation.
C.–J. Yen Analog Layout and Process Concern
• 32. Mask 1 29 Modern CMOS Process
• Mask 1 patterns the photoresist. The Si 3 N 4 layer is removed where it is not protected by
• the photoresist by dry etching.
C.–J. Yen Analog Layout and Process Concern
• 33. Field Oxide 30 Modern CMOS Process
• After photoresist stripping, the field oxide is grown in an oxidizing ambient.
C.–J. Yen Analog Layout and Process Concern
• 34. Mask 2 31 Modern CMOS Process
• Photoresist is used to mask the regions where PMOS devices will be built using mask 2.
• A boron implant provides the doping for the P wells for the NMOS devices.
C.–J. Yen Analog Layout and Process Concern
• 35. Mask 3 32 Modern CMOS Process
• Photoresist is used to mask the regions where NMOS devices will be built using mask 3.
• A phosphorus implant provides the doping for the N wells for the PMOS devices.
C.–J. Yen Analog Layout and Process Concern
• 36. N and P Wells 33 Modern CMOS Process
• A high temperature drive-in completes the formation of the N and P wells.
C.–J. Yen Analog Layout and Process Concern
• 37. Mask 4 34 Modern CMOS Process
• After spinning photoresist on the wafer, mask 4 is used to define the NMOS transistors.
• A boron implant adjusts the N-channel V TH .
C.–J. Yen Analog Layout and Process Concern
• 38. Mask 5 35 Modern CMOS Process
• After spinning photoresist on the wafer, mask 5 is used to define the PMOS transistors.
• A arsenic implant adjusts the P-channel V TH .
C.–J. Yen Analog Layout and Process Concern
• 39. Polysilicon Gate 36 Modern CMOS Process
• A layer of polysilicon is deposited. Ion implantation of phosphorus follows the
• deposition to heavily dope the poly.
C.–J. Yen Analog Layout and Process Concern
• 40. Mask 6 37 Modern CMOS Process
• Photoresist is applied and mask 6 is used to define the regions where MOS gates are
• located. The polysilicon layer is then etched using plasma etching.
C.–J. Yen Analog Layout and Process Concern
• 41. Mask 7 38 Modern CMOS Process
• Mask 7 is used to cover the PMOS devices. A phosphorus implant is used to form the
• tip or extension (LDD) regions in the NMOS devices.
C.–J. Yen Analog Layout and Process Concern
• 42. Mask 8 39 Modern CMOS Process
• Mask 8 is used to cover the NMOS devices. A boron implant is used to form the tip or
• extension (LDD) regions in the PMOS devices.
C.–J. Yen Analog Layout and Process Concern
• 43. Sidewall of Polysilicon 40 Modern CMOS Process
• The deposited SiO 2 layer is etched back anisotropically, leaving sidewall spacers along
• the edges of the polysilicon.
C.–J. Yen Analog Layout and Process Concern
• 44. Mask 9 41 Modern CMOS Process
• After growing a thin “screen” oxide, photoresist is applied and mask 9 is used to protect
• the PMOS transistors. An arsenic implant then forms the NMOS source and drain
• regions.
C.–J. Yen Analog Layout and Process Concern
• 45. Mask 10 42 Modern CMOS Process
• After applying photoresist, mask 10 is used to protect the NMOS transistors. A boron
• implant then forms the PMOS source and drain .
C.–J. Yen Analog Layout and Process Concern
• 46. Coating of Ti 43 Modern CMOS Process
• An unmasked oxide etch removes the SiO 2 from the devices source drain regions and
• form the top surface of the polysilicon. Titanium is deposited on the wafer surface by
• sputtering.
C.–J. Yen Analog Layout and Process Concern
• 47. TiSi 2 and TiN 44 Modern CMOS Process
• The titanium is reacted in an N 2 ambient, forming TiSi 2 where it contacts silicon or
• polysilicon (black regions in the figure) and TiN elsewhere.
C.–J. Yen Analog Layout and Process Concern
• 48. Mask 11 45 Modern CMOS Process
• Photoresist is applied and mask 11 is used to define the regions where TiN local
• interconnects will be used. The TiN is then etched.
C.–J. Yen Analog Layout and Process Concern
• 49. SiO 2 Deposited and Planarized 46 Modern CMOS Process
• After stripping the photoresist, a conformal SiO 2 layer is deposited by LPCVD.
• Chemical-Mechanical Polishing (CMP) or resist etchback is used to polish or etchback
• the deposited SiO 2 layer. This planarizes the wafer surface.
C.–J. Yen Analog Layout and Process Concern
• 50. Mask 12 47 Modern CMOS Process
• Photoresist is spun onto the wafer. Mask 12 is used to define the contact holes. The
• deposited SiO 2 layer is then etched to allow connections to the silicon, polysilicon
• and local interconnect regions.
C.–J. Yen Analog Layout and Process Concern
• 51. TiN/W Deposited and Planarized 48 Modern CMOS Process
• A thin TiN layer is deposited on the wafer by sputtering, followed by deposition of a W
• layer by CVD. CMP is used to polish back the W and TiN layer, leaving a planar
• surface on which the first level metal can be deposited.
C.–J. Yen Analog Layout and Process Concern
• 52. Mask 13 49 Modern CMOS Process
• Aluminum is deposited on the wafer by sputtering. Photoresist is spun on the wafer and
• mask 13 is used to define the first level of metal. The Al is then plasma etched.
C.–J. Yen Analog Layout and Process Concern
• 53. Masks 14/15/16 50 Modern CMOS Process
• The steps to form the second level of Al interconnect follow those in 1-55 to 1-58.
• Mask 14 is used to define via holes between metal 1 and metal 2. Mask 15 is used to
• define metal 2. The last step in the process is deposition of a final passivation layer,
• usually Si 3 N 4 deposited by PECVD. The last mask 16 is used to open holes in this mask
C.–J. Yen Analog Layout and Process Concern
• 54. MOS Transistor 51 Analog Layout Considerations C.–J. Yen Analog Layout and Process Concern
• 55. Parallel Transistors 52 Analog Layout Considerations
• Node 1 should be connected to
• the more critical node.
• To minimize voltage drops due
• to silicon-junction resistivity.
C.–J. Yen Analog Layout and Process Concern
• 56. Weight Current Cell Layout 53 Analog Layout Considerations C.–J. Yen Analog Layout and Process Concern
• 57. Current Mirror Layout Technique (I) 54 Analog Layout Considerations C.–J. Yen Analog Layout and Process Concern
• 58. Current Mirror Layout Technique (II) 55 Analog Layout Considerations C.–J. Yen Analog Layout and Process Concern
• 59. Current Mirror Layout Technique (III) 56 Analog Layout Considerations C.–J. Yen Analog Layout and Process Concern
• 60. Current Mirror Layout Technique (IV) 57 Analog Layout Considerations C.–J. Yen Analog Layout and Process Concern
• 61. Current Mirror Layout Technique (V) 58 Analog Layout Considerations C.–J. Yen Analog Layout and Process Concern
• 62. Serious-Connected Transistors 59 Analog Layout Considerations C.–J. Yen Analog Layout and Process Concern
• 63. CMOS Inverter 60 Analog Layout Considerations C.–J. Yen Analog Layout and Process Concern
• 64. Input Transistors 61 Analog Layout Considerations C.–J. Yen Analog Layout and Process Concern
• 65. Cross-Coupled Transistors 62 Analog Layout Considerations
• Offsets can be minimized.
• Minimum bends and corners in
• transistors to be matched.
C.–J. Yen Analog Layout and Process Concern
• 66. Common-Centroid Layout 63 Analog Layout Considerations
• Reducing errors caused by gradient effects.
• Dummy fingers are used for better matching accuracy.
C.–J. Yen Analog Layout and Process Concern
• 67. Input Stages of Op-Amp 64 Analog Layout Considerations C.–J. Yen Analog Layout and Process Concern
• 68. Layout Floor Plan for a Two-Stage Op-Amp 65 Analog Layout Considerations C.–J. Yen Analog Layout and Process Concern
• 69. Integrated Resistor 66 Analog Layout Considerations
• The contact contributes 0.14
• squares.
• Each bend contributes 2.11
• squares.
C.–J. Yen Analog Layout and Process Concern
• 70. Accurate Resistor Ratios 67 Analog Layout Considerations
• Reducing errors caused by R1/R2 contact impedance.
• Matching boundary conditions with dummy fingers.
C.–J. Yen Analog Layout and Process Concern
• 71. Resistor Matching 68 Analog Layout Considerations C.–J. Yen Analog Layout and Process Concern
• 72. Resistor Layout Technique (I) 69 Analog Layout Considerations C.–J. Yen Analog Layout and Process Concern
• 73. Resistor Layout Technique (II) 70 Analog Layout Considerations C.–J. Yen Analog Layout and Process Concern
• 74. Resistor Layout Technique (III) 71 Analog Layout Considerations C.–J. Yen Analog Layout and Process Concern
• 75. Resistor Layout Technique (IV) 72 Analog Layout Considerations C.–J. Yen Analog Layout and Process Concern
• 76. R-string Layout (I) 73 Analog Layout Considerations C.–J. Yen Analog Layout and Process Concern
• 77. R-string Layout (II) 74 Analog Layout Considerations C.–J. Yen Analog Layout and Process Concern
• 78. Integrated Capacitor (I) 75 Analog Layout Considerations C.–J. Yen Analog Layout and Process Concern
• 79. Integrated Capacitor (II) 76 Analog Layout Considerations C.–J. Yen Analog Layout and Process Concern
• 80. Capacitor Array (I) 77 Analog Layout Considerations
• Boundary-condition matching.
• The top plate should be connect to critical nodes.
C.–J. Yen Analog Layout and Process Concern
• 81. Capacitor Array (II) 78 Analog Layout Considerations C.–J. Yen Analog Layout and Process Concern
• 82. Capacitor Array (III) 79 Analog Layout Considerations C.–J. Yen Analog Layout and Process Concern
• 83. BJT Layout (I) 80 Analog Layout Considerations C.–J. Yen Analog Layout and Process Concern
• 84. BJT Layout (II) 81 Analog Layout Considerations C.–J. Yen Analog Layout and Process Concern
• 85. Shielding 82 Analog Layout Considerations
• To keep noise from being coupled into and out of the substrate.
C.–J. Yen Analog Layout and Process Concern
• 86. Signal Line Shielding 83 Analog Layout Considerations C.–J. Yen Analog Layout and Process Concern
• 87. Guard Rings 84 Analog Layout Considerations
• Minimizing the injection of noise into the substrate.
C.–J. Yen Analog Layout and Process Concern
• 88. Decoupling 85 Analog Layout Considerations C.–J. Yen Analog Layout and Process Concern
• 89. Separate Power Supplies 86 Analog Layout Considerations
• Preventing the digital noise coupling.
• To minimize substrate noise.
C.–J. Yen Analog Layout and Process Concern
• 90. Layout of a Two-Stage Op-Amp 87 Analog Layout Considerations C.–J. Yen Analog Layout and Process Concern
• 91. Layout of a Cascode Op-Amp 88 Analog Layout Considerations C.–J. Yen Analog Layout and Process Concern
• 92. Layout Floor Plan for Switched-Capacitor Circuits 89 Analog Layout Considerations C.–J. Yen Analog Layout and Process Concern
• 93. Latch-Up 90 Analog Layout Considerations
• The equivalent circuit of the parasitic bipolar transistors.
• The voltages after latch-up has occurred.
C.–J. Yen Analog Layout and Process Concern
• 94. Critical Layout Issues
• RC Delay
• Signal coupling
• Device matching
• Parasitic capacitance
• Noise considerations
• Latch-up
Analog Layout Considerations C.–J. Yen 91 Analog Layout and Process Concern
• 95. SPICE Simulation Simulation of a Common-Source Gain Stage C.–J. Yen 92 Analog Layout and Process Concern
• 96. SPICE Simulation Simulation of the Common-Source Gain Stage with a Capacitive Load C.–J. Yen 93 Analog Layout and Process Concern
• 97. SPICE Simulation Simulation of a Source Follower C.–J. Yen 94 Analog Layout and Process Concern
• 98. SPICE Simulation Step Response of a Source Follower C.–J. Yen 95 Analog Layout and Process Concern
• 99. SPICE Simulation Simulation of the Source Follower with a Compensation Circuit C.–J. Yen 96 Analog Layout and Process Concern
• 100. SPICE Simulation Simulation of the Cascode Gain Stage C.–J. Yen 97 Analog Layout and Process Concern