I2C Bus (Inter-Integrated Circuit)

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I2C Bus (Inter-Integrated Circuit)

  1. 1. I2C Bus Author: Varun Mahajan <varunmahajan06@gmail.com>
  2. 2. Contents ● I2C Bus concept ● Communication Protocol ● Bus Terminology ● General characteristics ● I2C Communication ● Data Validity ● START & STOP Conditions ● Byte Format ● Acknowledgment ● Synchronization ● Arbitration ● 7-Bit Addressing ● 10-Bit Addressing
  3. 3. I2C Bus concept ● Two bi-directional lines – SDA and SCL ● Each device is recognized by a unique address and can operate as a transmitter or receiver ● A master is the device which initiates the data transfer on the bus and generates the clock signals to permit the transfer. At that time any device addressed is considered a slave ● Multi-master bus
  4. 4. I2C Communication Protocol WRITE OPERATION START CONTROL BYTE ACK Byte1 ACK Byte2 ACK STOP READ OPERATION START CONTROL BYTE ACK Byte1 ACK Byte2 ACK STOP CONTROL BYTE 7 bit slave address R/W Sent by master Sent by slave
  5. 5. I2C Bus Terminology
  6. 6. I2C Bus Terminology Microcontroller A wants to send information to Microcontroller B: ● MC A (master), addresses MC B (slave) ● MC A (master-transmitter), sends data to MC B (slave-receiver) ● MC A (master) terminates the transfer Microcontroller A wants to receive information from microcontroller B: ● MC A (master), addresses MC B (slave) ● MC A (master-receiver), receives data from MC B (slave-transmitter) ● MC A (master) terminates the transfer
  7. 7. H/W Connections All the I2C interfaces are connected to the I2C bus using the wired-AND connection D1 D2 SDA2 SDA1 SCL2 SCL1 AND logic AND logic SDA SCL
  8. 8. I2C Bus: General Characteristics ● Transfer rates: - Standard mode : up to 100 kbit/sec - Fast mode : up to 400 kbit/sec - High Speed mode : up to 3.4 Mbit/sec ● 7-Bit and 10-Bit addressing ● Bus Free: Both SCL and SDA lines are HIGH ● The number of interfaces connected to the bus is solely dependent on the bus capacitance limit of 400 pF
  9. 9. Data Validity The data on SDA line must be stable during the HIGH period of SCL. The HIGH or LOW state of SDA can change when the SCL is LOW.
  10. 10. START and STOP conditions • START condition: A HIGH to LOW transition on SDA line while SCL is HIGH • STOP condition: A LOW to HIGH transition on SDA line while SCL is HIGH The bus is considered to be busy after the START condition. The bus is considered to be free again after the STOP condition
  11. 11. Byte Format ● Each byte put on the SDA line must be 8-bits long ● The number of bytes that can be transmitted per transfer is unrestricted ● Data is transferred with the most significant bit (MSB) first ● Slave can force the master into a wait state by holding the SCL LOW
  12. 12. Acknowledgement ● Each transferred byte needs to be acknowledged by the receiver ● The acknowledge-related clock pulse is generated by the master ● The transmitter releases the SDA line (HIGH) during the acknowledge clock pulse. The receiver must pull down the SDA line during the acknowledge clock pulse so that it remains stable LOW during the HIGH period of this clock pulse
  13. 13. Synchronization ● Synchronization is performed using the wired-AND connection of I2C interfaces to the SCL line ● A synchronized clock is generated with its LOW period determined by the device with the longest clock LOW period, and its HIGH period determined by the one with the shortest clock HIGH period
  14. 14. Arbitration Arbitration takes place on the SDA line, while the SCL line is at HIGH level, in such a way that the master which transmits a HIGH level, while another master is transmitting LOW will switch off its DATA output stage because the level on the bus doesn’t correspond to its own level
  15. 15. 7-Bit Addressing ● The first seven bits of the first byte make up the slave address ● The eighth bit (LSB) determines the direction of the message. 0 means that the master will write information to a selected device. 1 means that the master will read information from the slave
  16. 16. 7-Bit Addressing Definition of bits in the first byte
  17. 17. 7-Bit Addressing
  18. 18. 10-Bit Addressing ● The first seven bits of the first byte are the combination 11110XX of which the last two bits are the two MSBs of the 10-bit address ● The eighth bit (LSB) determines the direction of the message. 0 means that the master will write information to a selected device. 1 means that the master will read information from the slave ● If the eighth bit is 0, then the second byte contains the remaining 8 bits of the 10- bit address ● If the eighth bit is 1, then the next byte contains data transmitted from a slave to a master
  19. 19. 10-Bit Addressing
  20. 20. References ● I2C Bus Specification version 2.1 January 2000
  21. 21. END…

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