Each time the input switches from 0to 1 or 1 to 0 power is consumed.
PART IS DISSPATED in charging and discharging the capacitor
PART IS STORED in the load capacitor
Dynamic Power Dissipation Energy/transition = C L * V dd 2 Power = Energy/transition * f = C L * V dd 2 * f 0 to1 or 1 to 0 Need to reduce C L , V dd , and f to reduce power. Not a function of transistor sizes! i VDD f 0 to1 or 1 to 0 is the frequency of transition Vin Vout C L Vdd
Half the energy stored in the Capacitor, the other half is lost !
Delay Formula C int = C gin with 1 f = C ext /C gin - effective fanout C ext =fC gin R = R unit /W ; C int =WC unit t p 0 = 0.69 R unit C unit Let tp=0.69 Req(Cint+Cext) =0.69 ReqCint(1+Cext/Cint) =tp0(1+Cext/Cint) =tp0(1+f/ )
Refers to direct path from V DD to V GND during switching events
Short Circuit Currents scr is short circuit rise time And scf is short circuit fall time P SC is short circuit power consumption I SC is the short circuit current consumed Δ t sc is the duration for which the short circuit current flows I SC , avg is the average crowbar current during rise and fall.
Notice in the previous graph that when tsin/tsout=1 Power Dissipation is minimum
Reducing V DD leads to lower power consumption
Point 1 is VTn Point2 is VDD-VTP
If 2 lies before 1 short circuit power consumption is 0!
However circuit will be slower
V T VDD-V T 1 2 time voltage
Dynamic Power -Glitches Glitches are caused by arrival time of two separate input signals. If a given input signal arrives first and causes the output to switch, later another input signal arrives and causes the output to switch back to original value. Undesired Power dissipation ! Glitches propagate thought the fanout gate and cause further unintended transitions
Subthreshold currents and ie currents that flow when VGS is less than VT
Leakage Sub-threshold current one of most compelling issues in low-energy circuit design!
Reverse-Biased Diode Leakage JS = 10-100 pA/ m2 at 25 deg C for 0.25 m CMOS JS doubles for every 9 deg C!
Junction Leakage currents are caused by thermally generated carriers. Their value increases with increasing temperature. At 85 degrees Celsius, (upper bound for junction temperature) their value increases by 60 times over room temperature value.
Sub threshold Leakage issues Closer V T is to 0 V, larger is the static power dissipation as I D becomes larger L is getting smaller as source and drain are getting closer Supply voltages are being scaled while keeping V T constant. This leads to increase in delay –see next slide. As Supply voltage goes down to 2V T,, performance goes down substantially. If V T is lowered, performance improves, sub threshold leakage becomes an issue i.e. Trade off between power and delay!
Power Equation Static power loss in pseudo nmos only half the time!
POWER DELAY TRADE OFF We want low power and small delay. Why not minimize the product? P avg is average Power consumed t p is average delay Only dominant term in Power Equation Assume Gate switches at maximum possible rate so rise and fall