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# Low Power Design - PPT 1

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Anu Mehra Maam PPT - 1

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### Low Power Design - PPT 1

1. 1. Low Power VLSI Design The Inverter Dr Anu Mehra
2. 2. The CMOS Inverter: A First Glance V in V out C L V DD
3. 3. CMOS Inverter Polysilicon In Out GND PMOS 2  Metal 1 NMOS Contacts N Well V DD
4. 4. Two Inverters Connect in Metal Share power and ground Abut cells
5. 5. CMOS Inverter First-Order DC Analysis V OL = 0 V OH = V DD V M = f(R n , R p ) V DD V DD V in 5 V DD V in 5 0 V out V out R n R p
6. 6. CMOS Inverter: Transient Response V out V out R n R p V DD V DD V in 5 V DD V in 5 0 (a) Low-to-high (b) High-to-low C L C L t pHL = f(R on .C L ) = 0.69 R on C L
7. 7. Voltage Transfer Characteristic
8. 8. PMOS Load Lines V DSp I Dp V GSp =-2.5 V GSp =-1 V DSp I Dn V in =0 V in =1.5 V out I Dn V in =0 V in =1.5 V in = V DD +V GSp I Dn = - I Dp V out = V DD +V DSp V out I Dn V in = V DD +V GSp I Dn = - I Dp V out = V DD +V DSp
9. 9. CMOS Inverter Load Characteristics
10. 10. CMOS Inverter VTC
11. 11. Switching Threshold as a function of Transistor Ratio 10 0 10 1 0.8 0.9 1 1.1 1.2 1.3 1.4 1.5 1.6 1.7 1.8 M V (V) W p /W n
12. 12. Determining V IH and V IL A simplified approach V OH V OL V in V out V M V IL V IH
13. 13. Inverter Gain
14. 14. Simulated VTC
15. 15. Propagation Delay
16. 16. CMOS Inverter Propagation Delay Approach 1 ∆ t=C L ∆V/I DS Iav is average charging current and ∆V is V DD /2 V DD V out V in = V DD C L I av t pHL = C L V swing /2 I av
17. 17. CMOS Inverter Propagation Delay Approach 2
18. 18. Transient Response t p = 0.69 C L (R eqn +R eqp )/2 t pLH t pHL
19. 19. Delay as a function of V DD
20. 20. The Transistor as a Switch
21. 21. Design for Performance (minimum delay) <ul><li>Keep capacitances small –keep drain diffusion area small so less overlap </li></ul><ul><li>Increase transistor sizes </li></ul><ul><ul><li>watch out for self-loading! </li></ul></ul><ul><li>Increase V DD – however increasing voltage beyond a level leads to reliability concern </li></ul>
22. 22. To MAKE A SYMMETRIC INVERTER tpHL=tpLH <ul><li>Reqn= 13k Ω and Reqp= 31k Ω (for 0.25 µ m technology) </li></ul><ul><li>R N = Reqn(L/W)n </li></ul><ul><li>R P= Reqp(L/W)p </li></ul><ul><li>tpLH=ln(2)R P C L </li></ul><ul><li>tnHL=ln(2)R N C L </li></ul>
23. 23. <ul><li>In order to make tpHL=tpLH </li></ul>
24. 24. To minimize total delay <ul><li>Total delay =tpHL+tpLH </li></ul><ul><li>Approximate load Capacitance </li></ul><ul><li>C L = (Cdp1+Cdn1)+(Cgp2+Cgn2)+CW </li></ul><ul><li>Let β =(W/L)p/(W/L)n </li></ul><ul><li>Then Cdp1= βCdn1 and Cgp2= β Cgn2 </li></ul><ul><li>Total delay=tp </li></ul>
25. 25. <ul><li>tp=0.69((1+β)(Cdn1+Cgn2)+C W (Reqn+Reqp/β) </li></ul><ul><li>tp=0.69((1+β)(Cdn1+Cgn2)+C W Reqn(1+r/β) </li></ul><ul><li>To minimize delay </li></ul>
26. 26. <ul><li>For 0.25 technology </li></ul>
27. 27. NMOS/PMOS ratio tpLH tpHL tp  = W p /W n