1D and 2D Bitstream Relocation for Partially Dynamically Reconfigurable Architecture BY Marco Novati [email_address] Thesi...
Aims <ul><li>Architectural support for relocation: </li></ul><ul><ul><li>Create an integrated HW/SW system to manage onlin...
Outline <ul><li>Introduction </li></ul><ul><li>Relocation </li></ul><ul><li>State of Art </li></ul><ul><li>Proposed Soluti...
What’s Next… <ul><li>Introduction </li></ul><ul><ul><li>Reconfiguration </li></ul></ul><ul><ul><li>Xilinx FPGAs </li></ul>...
Reconfigurable Computing <ul><li>“ Reconfigurable computing is intended to fill the gap between hardware and software, ach...
5 W <ul><li>who  controls the reconfiguration </li></ul><ul><li>where  the reconfigurator is located </li></ul><ul><li>whe...
Reconfiguration in everyday life <ul><li>Soccer </li></ul>Hockey Football (Complete – Static) (Partial – Dynamic) (Partial...
Reconfigurable architecture <ul><li>A basic reconfigurable architecture consists of: </li></ul><ul><ul><li>a Static area :...
Basic Definitions <ul><li>Core : a specific representation of a functionality. It is possible, for example, to have a core...
Xilinx FPGAs and Configuration Memory
Frame Addressing: Virtex, Virtex-E *  Inspired to Virtex Series Configuration Architecture User Guide
Frame Addressing: Virtex2pro *  Taken from Virtex-II Pro and Virtex-II Pro X FPGA User Guide
Frame Addressing: Virtex 4-5 (1/2) <ul><li>New Frame Addressing: </li></ul><ul><ul><li>Possibility of addressing rows and ...
Frame Addressing: Virtex 4-5 (2/2) *  Inspired to Virtex 4 & 5 Configuration Architecture User Guide
What’s Next… <ul><li>Introduction </li></ul><ul><li>Relocation </li></ul><ul><li>State of Art </li></ul><ul><li>Proposed S...
Relocation: Rationale <ul><li>Bitstreams relocation technique to:  </li></ul><ul><ul><li>speedup the overall system execut...
Relocation: The Problem
Relocation: Scenario
Relocation: Motivation
What’s Next… <ul><li>Introduction </li></ul><ul><li>Relocation </li></ul><ul><li>State of Art </li></ul><ul><ul><li>PARBIT...
PARBIT <ul><li>[E. Horta and John W. Lockwood, ”PARBIT: A Tool to Transform Bitfiles to Implement Partial Reconfiguration of...
BITPOS <ul><li>[Yana E. Krasteva, Eduardo de la Torre, Teresa Riesgo and Didier Joly, ”Virtex II FPGA Bitstream Maniplatio...
BAnMaT <ul><li>[D. Deori, ”BAnMaT: un Framework per l’Analisi e la Manipolazione di un Bitstream Orientato alla Riconfigura...
REPLICA <ul><li>[H. Kalte, G. Lee, M. Porrmann and U. Rckert, ”REPLICA: A Bitstream Manipulation Filter for Module Relocat...
What’s Next… <ul><li>Introduction </li></ul><ul><li>Relocation </li></ul><ul><li>State of Art </li></ul><ul><li>Polaris </...
Polaris: Motivations <ul><li>Complete workflow to generate a self dynamically reconfigurable architecture that: </li></ul>...
Polaris  Overview <ul><li>Workflow to manage allocation and relocation of tasks in self dynamically reconfigurable archite...
Target Architecture: YaRA
PPC Based YaRA STATIC AREA
Proposed Relocation Solutions <ul><li>Runtime Support for Self Dynamical Runtime 1D and 2D Reconfiguration </li></ul><ul><...
Configuration Bitstream
BiRF & BiRF Square Block Diagram
The Parser
CRC Calculation <ul><li>Particular CRC value, used by Xilinx tools </li></ul><ul><li>Two version of BiRF and BiRF Square: ...
What’s Next… <ul><li>Introduction </li></ul><ul><li>Relocation </li></ul><ul><li>State of Art </li></ul><ul><li>Proposed S...
Results <ul><li>Relocation solutions: </li></ul><ul><ul><li>Small area usage (slide 37) </li></ul></ul><ul><ul><li>High ti...
Synthesis Results: Area FPGA BiRF BiRF Square Family Model Generic Version Optimized Version Generic Version Optimized Ver...
Synthesis Results: Time Performances <ul><li>BiRF: </li></ul><ul><ul><li>On a Virtex2pro with speed grade -5 </li></ul></u...
Relocation Solutions Results (1/2) <ul><li>BiRF, BiRF Square, BAnMaT Lite </li></ul><ul><ul><li>Permit to support relocati...
Relocation Solutions Results (2/2) <ul><li>A total configuration file size is about 1 MB </li></ul><ul><li>Considering an ...
Relocation Time Results (1/4)
Relocation Time Results (2/4) <ul><li>FPU1: clock time 0.01 ms, required for 3.65 s (7 add, 3 sub, 10 mul, 1 square root a...
Relocation Time Results (3/4)
Relocation Time Results (4/4)
What’s Next… <ul><li>Introduction </li></ul><ul><li>Relocation </li></ul><ul><li>State of Art </li></ul><ul><li>Proposed S...
Concluding Remarks <ul><li>Architectural support for relocation: </li></ul><ul><ul><li>Create an integrated HW/SW system t...
Future Work <ul><li>Validation tool for the chosen </li></ul><ul><ul><li>Reconfiguration model </li></ul></ul><ul><ul><li>...
General Information <ul><li>Webpage </li></ul><ul><ul><li>www.dresd.org/?q=polaris </li></ul></ul><ul><li>Mailing List </l...
Questions
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  • UIC Thesis Novati

    1. 1. 1D and 2D Bitstream Relocation for Partially Dynamically Reconfigurable Architecture BY Marco Novati [email_address] Thesis committee: Shantanu Dutt (chair), Marco Domenico Santambrogio, Piotr Gmytrasiewicz UIC Thesis Defense: May 8, 2008
    2. 2. Aims <ul><li>Architectural support for relocation: </li></ul><ul><ul><li>Create an integrated HW/SW system to manage online relocation (1D and 2D) in reconfigurable architecture </li></ul></ul><ul><ul><li>Create efficient bitstream relocation solutions suitable for the target system: </li></ul></ul><ul><ul><ul><li>1D - 2D </li></ul></ul></ul><ul><ul><ul><li>HW – SW </li></ul></ul></ul>
    3. 3. Outline <ul><li>Introduction </li></ul><ul><li>Relocation </li></ul><ul><li>State of Art </li></ul><ul><li>Proposed Solutions </li></ul><ul><li>Results </li></ul><ul><li>Concluding Remarks and Future Work </li></ul>
    4. 4. What’s Next… <ul><li>Introduction </li></ul><ul><ul><li>Reconfiguration </li></ul></ul><ul><ul><li>Xilinx FPGAs </li></ul></ul><ul><li>Relocation </li></ul><ul><li>State of Art </li></ul><ul><li>Proposed Solutions </li></ul><ul><li>Results </li></ul><ul><li>Concluding Remarks and Future Work </li></ul>
    5. 5. Reconfigurable Computing <ul><li>“ Reconfigurable computing is intended to fill the gap between hardware and software, achieving potentially much higher performance than software, while maintaining a higher level of flexibility than hardware” </li></ul><ul><li>(K. Compton and S. Hauck, Reconfigurable Computing: a Survey of Systems and Software , 2002) </li></ul>
    6. 6. 5 W <ul><li>who controls the reconfiguration </li></ul><ul><li>where the reconfigurator is located </li></ul><ul><li>when the configurations are generated </li></ul><ul><li>which is the granularity of the reconfiguration </li></ul><ul><li>in what dimension the reconfiguration operates </li></ul>
    7. 7. Reconfiguration in everyday life <ul><li>Soccer </li></ul>Hockey Football (Complete – Static) (Partial – Dynamic) (Partial – Static)
    8. 8. Reconfigurable architecture <ul><li>A basic reconfigurable architecture consists of: </li></ul><ul><ul><li>a Static area : a basic Harward architecture </li></ul></ul><ul><ul><li>a Reconfigurable area : an device area composed by several reconfigurable regions </li></ul></ul>
    9. 9. Basic Definitions <ul><li>Core : a specific representation of a functionality. It is possible, for example, to have a core described in VHDL, in C or in an intermediate representation (e.g. a DFG) </li></ul><ul><li>IP-Core : a core described using a HD Language combined with its communication infrastructure (i.e. the bus interface) </li></ul><ul><li>Reconfigurable Functional Unit : an IP-Core that can be plugged and/or unplugged at runtime in an already working architecture </li></ul><ul><li>Reconfigurable Region : a portion of the device area used to implement a reconfigurable core </li></ul>
    10. 10. Xilinx FPGAs and Configuration Memory
    11. 11. Frame Addressing: Virtex, Virtex-E * Inspired to Virtex Series Configuration Architecture User Guide
    12. 12. Frame Addressing: Virtex2pro * Taken from Virtex-II Pro and Virtex-II Pro X FPGA User Guide
    13. 13. Frame Addressing: Virtex 4-5 (1/2) <ul><li>New Frame Addressing: </li></ul><ul><ul><li>Possibility of addressing rows and columns </li></ul></ul>* Inspired to Virtex 4 & 5 Configuration Architecture User Guide
    14. 14. Frame Addressing: Virtex 4-5 (2/2) * Inspired to Virtex 4 & 5 Configuration Architecture User Guide
    15. 15. What’s Next… <ul><li>Introduction </li></ul><ul><li>Relocation </li></ul><ul><li>State of Art </li></ul><ul><li>Proposed Solutions </li></ul><ul><li>Results </li></ul><ul><li>Concluding Remarks and Future Work </li></ul>
    16. 16. Relocation: Rationale <ul><li>Bitstreams relocation technique to: </li></ul><ul><ul><li>speedup the overall system execution </li></ul></ul><ul><ul><li>reduce the amount of memory used to store partial bitstreams </li></ul></ul><ul><ul><li>achieve a core preemptive execution </li></ul></ul><ul><ul><li>assign at runtime the bitstreams placement </li></ul></ul>
    17. 17. Relocation: The Problem
    18. 18. Relocation: Scenario
    19. 19. Relocation: Motivation
    20. 20. What’s Next… <ul><li>Introduction </li></ul><ul><li>Relocation </li></ul><ul><li>State of Art </li></ul><ul><ul><li>PARBIT </li></ul></ul><ul><ul><li>BITPOS </li></ul></ul><ul><ul><li>BAnMaT </li></ul></ul><ul><ul><li>REPLICA </li></ul></ul><ul><li>Proposed Solutions </li></ul><ul><li>Results </li></ul><ul><li>Concluding Remarks and Future Work </li></ul>
    21. 21. PARBIT <ul><li>[E. Horta and John W. Lockwood, ”PARBIT: A Tool to Transform Bitfiles to Implement Partial Reconfiguration of Field Programmable Gate Arrays (FPGAs)”, Washington University, Technical Report, July 2001.] </li></ul><ul><li>Features: </li></ul><ul><ul><li>PureC software </li></ul></ul><ul><ul><li>Enables the generation of the partial bitstream file </li></ul></ul><ul><ul><li>Small modifications, altering only the parts related to the location on the device. </li></ul></ul><ul><li>CONS: </li></ul><ul><ul><li>Only offline </li></ul></ul><ul><ul><li>Only 1D reconfiguration </li></ul></ul>
    22. 22. BITPOS <ul><li>[Yana E. Krasteva, Eduardo de la Torre, Teresa Riesgo and Didier Joly, ”Virtex II FPGA Bitstream Maniplation: Application to Reconfiguration Control Systems”, 2006 International Conference on Field Programmable Logic and Applications, August 2006.] </li></ul><ul><li>Features: </li></ul><ul><ul><li>Extract an area from a configuration file </li></ul></ul><ul><ul><li>Generate the new relocated bitstream </li></ul></ul><ul><li>CONS: </li></ul><ul><ul><li>Only offline </li></ul></ul><ul><ul><li>Only Virtex II, Virtex II Pro [1D] </li></ul></ul>
    23. 23. BAnMaT <ul><li>[D. Deori, ”BAnMaT: un Framework per l’Analisi e la Manipolazione di un Bitstream Orientato alla Riconfigurabilita Parziale”, DEI, Milano, Politecnico di Milano, 2006] </li></ul><ul><li>Features: </li></ul><ul><ul><li>Bitstream correctness check </li></ul></ul><ul><ul><li>Perform modification on a configuration bitstream </li></ul></ul><ul><ul><li>Permits to bypass synthesis process from the VHDL </li></ul></ul><ul><li>CONS: </li></ul><ul><ul><li>Only offline manipulation </li></ul></ul>
    24. 24. REPLICA <ul><li>[H. Kalte, G. Lee, M. Porrmann and U. Rckert, ”REPLICA: A Bitstream Manipulation Filter for Module Relocation in Partial Reconfigurable Systems”, The 12th Reconfigurable Architectures Workshop (RAW 2005), 2005.] </li></ul><ul><li>Features: </li></ul><ul><ul><li>Hardware filter that exploit relocation </li></ul></ul><ul><ul><li>Necessary manipulations during the download process </li></ul></ul><ul><ul><li>Relocation hiding </li></ul></ul><ul><li>CONS: </li></ul><ul><ul><li>Only for external reconfigurable system </li></ul></ul><ul><ul><li>Only 1D relocation </li></ul></ul><ul><ul><li>Maximum frequency of 50 MHz </li></ul></ul>
    25. 25. What’s Next… <ul><li>Introduction </li></ul><ul><li>Relocation </li></ul><ul><li>State of Art </li></ul><ul><li>Polaris </li></ul><ul><li>Proposed Solutions </li></ul><ul><ul><li>Polaris </li></ul></ul><ul><ul><li>Target Architecture </li></ul></ul><ul><ul><li>Proposed Relocation Solutions </li></ul></ul><ul><li>Results </li></ul><ul><li>Concluding Remarks and Future Work </li></ul>
    26. 26. Polaris: Motivations <ul><li>Complete workflow to generate a self dynamically reconfigurable architecture that: </li></ul><ul><ul><li>Supports 1D and 2D reconfiguration </li></ul></ul><ul><ul><li>Has “good” area constraints for cores </li></ul></ul><ul><ul><li>Performs Runtime task placement decisions </li></ul></ul><ul><ul><li>Exploits internal and fast Core relocation </li></ul></ul><ul><li>Starting from specification of: </li></ul><ul><ul><li>Target application </li></ul></ul><ul><ul><li>Target device info </li></ul></ul><ul><ul><li>Reconfiguration model </li></ul></ul><ul><ul><li>Communication Infrastructure </li></ul></ul>
    27. 27. Polaris Overview <ul><li>Workflow to manage allocation and relocation of tasks in self dynamically reconfigurable architectures </li></ul><ul><li>Final goal: complete architecture (bitstreams and code) generation </li></ul>
    28. 28. Target Architecture: YaRA
    29. 29. PPC Based YaRA STATIC AREA
    30. 30. Proposed Relocation Solutions <ul><li>Runtime Support for Self Dynamical Runtime 1D and 2D Reconfiguration </li></ul><ul><ul><li>Xilinx Virtex, Virtex-E, Virtex2pro [1D] </li></ul></ul><ul><ul><li>Xilinx Virtex-4 and Virtex-5 [2D] </li></ul></ul><ul><li>Relocation, different solutions: </li></ul><ul><ul><li>Software: </li></ul></ul><ul><ul><ul><li>BAnMaT Lite </li></ul></ul></ul><ul><ul><li>Hardware: </li></ul></ul><ul><ul><ul><li>BiRF [1D] </li></ul></ul></ul><ul><ul><ul><li>BiRF Square [2D] </li></ul></ul></ul>
    31. 31. Configuration Bitstream
    32. 32. BiRF & BiRF Square Block Diagram
    33. 33. The Parser
    34. 34. CRC Calculation <ul><li>Particular CRC value, used by Xilinx tools </li></ul><ul><li>Two version of BiRF and BiRF Square: </li></ul><ul><ul><li>By using the “predefined” values </li></ul></ul><ul><ul><li>With actual CRC calculation </li></ul></ul><ul><li>X 16 + X 15 + X 2 + 1 [1D] </li></ul><ul><li>X 32 + X 28 + X 27 + X 26 + X 25 + X 23 + X 22 + X 20 + X 19 + X 18 + X 14 + X 13 + X 11 + X 10 + X 9 + X 8 + X 6 + 1 [2D] </li></ul>
    35. 35. What’s Next… <ul><li>Introduction </li></ul><ul><li>Relocation </li></ul><ul><li>State of Art </li></ul><ul><li>Proposed Solutions </li></ul><ul><li>Results </li></ul><ul><ul><li>Synthesis Results </li></ul></ul><ul><ul><li>Relocation Solutions Results </li></ul></ul><ul><li>Concluding Remarks and Future Work </li></ul>
    36. 36. Results <ul><li>Relocation solutions: </li></ul><ul><ul><li>Small area usage (slide 37) </li></ul></ul><ul><ul><li>High time performance (slide 38) </li></ul></ul><ul><li>Relocation results: </li></ul><ul><ul><li>Internal memory saving (slides 39 – 40) </li></ul></ul><ul><ul><li>Time saving (slides 41- 44) </li></ul></ul>
    37. 37. Synthesis Results: Area FPGA BiRF BiRF Square Family Model Generic Version Optimized Version Generic Version Optimized Version Virtex II Pro vp7 11.6 % 3.6 % − − Virtex II Pro vp20 5.8 % 1.8 % − − Virtex II Pro vp30 4.2 % 1.3 % − − Virtex 4 vlx40 − − 2.2 % 0.9 % Virtex 4 vlx60 − − 1.5 % 0.6 % Virtex 4 vlx100 − − 0.8 % 0.3 % Virtex 5 vlx50 − − 1.1 % 0.8 % Virtex 5 vlx85 − − 0.6 % 0.4 % Virtex 5 vlx110 − − 0.5 % 0.3 %
    38. 38. Synthesis Results: Time Performances <ul><li>BiRF: </li></ul><ul><ul><li>On a Virtex2pro with speed grade -5 </li></ul></ul><ul><ul><ul><li>General purpose version: max frequency of 101 MHz </li></ul></ul></ul><ul><ul><ul><li>Specific version: max frequency of 136 MHz </li></ul></ul></ul><ul><li>BiRF Square: </li></ul><ul><ul><li>On a Virtex-4 with speed grade -12 </li></ul></ul><ul><ul><ul><li>General purpose version: max frequency of 160 MHz </li></ul></ul></ul><ul><ul><ul><li>Specific version: max frequency of 290 MHz </li></ul></ul></ul><ul><ul><li>On a Virtex-5 with speed grade -3 </li></ul></ul><ul><ul><ul><li>General purpose version: max frequency of 226 MHz </li></ul></ul></ul><ul><ul><ul><li>Specific version: max frequency of 304 MHz </li></ul></ul></ul>
    39. 39. Relocation Solutions Results (1/2) <ul><li>BiRF, BiRF Square, BAnMaT Lite </li></ul><ul><ul><li>Permit to support relocation in a self partially and dynamically 1D or 2D reconfigurable system </li></ul></ul><ul><ul><li>The occupation ratio is relatively small </li></ul></ul><ul><ul><li>Frequency more than acceptable </li></ul></ul><ul><ul><li>Reduction of internal memory requirements </li></ul></ul><ul><li>Throughput: </li></ul><ul><ul><li>BiRF: 6 MB/s </li></ul></ul><ul><ul><li>BiRF Square: 7.3 MB/s </li></ul></ul><ul><ul><li>BAnMaT Lite: 2.6 MB/s </li></ul></ul>
    40. 40. Relocation Solutions Results (2/2) <ul><li>A total configuration file size is about 1 MB </li></ul><ul><li>Considering an architecture: </li></ul><ul><ul><li>1/3 of the area as fixed part </li></ul></ul><ul><ul><li>2/3 as reconfigurable part with 6 slots </li></ul></ul><ul><li>With such hypothesis </li></ul><ul><ul><li>Size of a partial bitstream will be about 110 KB </li></ul></ul><ul><ul><li>Relocation time of about: </li></ul></ul><ul><ul><ul><li>18 ms with BiRF </li></ul></ul></ul><ul><ul><ul><li>15 ms with BiRF Square </li></ul></ul></ul><ul><ul><ul><li>42 ms with BAnMaT Lite </li></ul></ul></ul>
    41. 41. Relocation Time Results (1/4)
    42. 42. Relocation Time Results (2/4) <ul><li>FPU1: clock time 0.01 ms, required for 3.65 s (7 add, 3 sub, 10 mul, 1 square root and 4 div) </li></ul><ul><ul><li>Feasible RR assignment: (0,0) and (6,0) </li></ul></ul><ul><li>JPEG: a complete JPEG Hardware Compressor, compression rate 24 img(352x288)/s, required for 3 seconds (72 img 352x288) </li></ul><ul><ul><li>Feasible RR assignment: (0,0), (0,1), (6,0) and (6,1) </li></ul></ul><ul><li>FPU2: clock time 0.01 ms, required for 3.13 s (6 add, 5 sub, 8 mul and 4 div) </li></ul><ul><ul><li>Feasible RR assignment: (0,0) and (6,0) </li></ul></ul><ul><li>3DES: a Triple-DES 64-bit block cipher, required for 1 second, in order to process a file of 72 MB </li></ul><ul><ul><li>Feasible RR assignment: (0,0),(1,0), (3,0) and (3,1) </li></ul></ul>
    43. 43. Relocation Time Results (3/4)
    44. 44. Relocation Time Results (4/4)
    45. 45. What’s Next… <ul><li>Introduction </li></ul><ul><li>Relocation </li></ul><ul><li>State of Art </li></ul><ul><li>Proposed Solutions </li></ul><ul><li>Results </li></ul><ul><li>Concluding Remarks and Future Work </li></ul>
    46. 46. Concluding Remarks <ul><li>Architectural support for relocation: </li></ul><ul><ul><li>Create an integrated HW/SW system to manage online relocation (1D and 2D) in reconfigurable architecture </li></ul></ul><ul><ul><li>Create efficient bitstream relocation solutions suitable for the target system: </li></ul></ul><ul><ul><ul><li>1D - 2D </li></ul></ul></ul><ul><ul><ul><li>HW – SW </li></ul></ul></ul><ul><li>Pubblications: </li></ul><ul><ul><li>International conferences: </li></ul></ul><ul><ul><ul><li>M. Morandi, M. Novati, M. D. Santambrogio, D. Sciuto, Core allocation and relocation management for a self dynamically reconfigurable architecture, ISVLSI 2008, IEEE Computer Society Annual Symposium on VLSI </li></ul></ul></ul><ul><ul><ul><li>S. Corbetta, F. Ferrandi, M. Morandi, M. Novati, M. D. Santambrogio, D. Sciuto, Two Novel Approaches to Online Partial Bitstream Relocation in a Dynamically Reconfigurable System, ISVLSI 2007, IEEE Computer Society Annual Symposium on VLSI </li></ul></ul></ul><ul><ul><li>IEEE Transaction on VLSI (Second Rewiew Phase): </li></ul></ul><ul><ul><ul><li>M. Morandi, M. Novati, M.D. Santambrogio, P Spoletini, D. Sciuto, Internal and External Bitstream Relocation for Partial Dynamic Reconfiguration, TSVLSI, IEEE Transactions on Very Large Scale Integration Systems </li></ul></ul></ul>
    47. 47. Future Work <ul><li>Validation tool for the chosen </li></ul><ul><ul><li>Reconfiguration model </li></ul></ul><ul><ul><li>Communication infrastructure </li></ul></ul><ul><li>Simulation framework </li></ul><ul><ul><li>Monitor the reconfigurable system evolution </li></ul></ul><ul><ul><li>Evaluate different placement policies and area constraints definitions </li></ul></ul>
    48. 48. General Information <ul><li>Webpage </li></ul><ul><ul><li>www.dresd.org/?q=polaris </li></ul></ul><ul><li>Mailing List </li></ul><ul><ul><li>[email_address] </li></ul></ul><ul><li>Contact </li></ul><ul><ul><li>To have more information regarding polaris: </li></ul></ul><ul><ul><ul><li>[email_address] </li></ul></ul></ul><ul><ul><li>For a complete list of information on how to contact us: </li></ul></ul><ul><ul><ul><li>www.dresd.org/?q=contact_polaris </li></ul></ul></ul>
    49. 49. Questions

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