0
Time-driven reconfiguration-aware floorplacer BY Alessio Montone [email_address] Thesis committee: S. Dutt (chair), A. Kho...
Rationale and Innovation <ul><li>Problem statement </li></ul><ul><ul><li>Given a reconfigurable architecture, find an on-c...
Aims <ul><ul><li>Considering the area assignment problem tailored for reconfigurable architectures, provide </li></ul></ul...
Outline <ul><li>Introduction </li></ul><ul><li>Floorplacement </li></ul><ul><li>The Proposed Approach </li></ul><ul><li>Ex...
INTRODUCTION
Reconfigurable Architectures - I <ul><li>On FPGAs </li></ul><ul><ul><li>Reconfigurable Devices </li></ul></ul><ul><ul><li>...
Reconfigurable Architectures - I <ul><ul><li>Total </li></ul></ul>
Reconfigurable Architectures - I <ul><ul><li>Total </li></ul></ul><ul><ul><li>Partial (Static) </li></ul></ul>
Reconfigurable Architectures - II <ul><ul><li>Partial Dynamic </li></ul></ul>
Area Assignment Problem <ul><li>Let consider a Reconfigurable Architecture </li></ul><ul><ul><li>Given  a scheduled task g...
Related Works - I <ul><li>[*] introduced the concept of 3D floorplanning for reconfigurable systems </li></ul><ul><ul><li>...
Related Works - II <ul><li>[*] is the state of art in 3D floorplanning </li></ul><ul><ul><li>Simulated Annealing over Tran...
FLOORPLACEMENT
Floorplanning vs. Placement Placement Floor plan Characteristic Floorplanning Placement # items <100 >10.000 Items (for FP...
Floorplacement - I <ul><li>Hierarchical Approach (Floorplanning + Partitioning) </li></ul>S. N. Adya, I. L. Markov,  Fixed...
Floorplacement - II <ul><li>Reconfigurable Functional Unit (RFU) </li></ul><ul><ul><li>A netlist obtained after post synth...
Floorplacement - III <ul><li>Resource Aware (i.e., not all positions are feasible) </li></ul><ul><ul><li>Device heterogene...
THE PROPOSED APPROACH
Proposed Problem Definition <ul><li>Aim </li></ul><ul><ul><li>Define RRs </li></ul></ul><ul><ul><li>For each task find </l...
Target Architecture and Devices <ul><li>Target Devices: Xilinx Virtex 4 - 5 </li></ul><ul><li>Target architecture based on...
Input
Proposed Approach: overview
1 st  Algorithm: Partitioning into RR <ul><li>Aim : identify the RRs and associate each RFU to one RR </li></ul><ul><li>Ho...
2 nd  Algorithm:TFiRR - I <ul><li>Temporal Floorplacement inside RR (TFiRR) </li></ul><ul><li>Aim : for each RR find a set...
2 nd  Algorithm:TFiRR - II <ul><li>Let consider an iteration: </li></ul>
2 nd  Algorithm:TFiRR - III <ul><li>Let consider an iteration: </li></ul>
2 nd  Algorithm:TFiRR - IV <ul><li>Let consider an iteration: </li></ul>
2 nd  Algorithm:TFiRR - V <ul><li>Let consider an iteration: </li></ul>
2 nd  Algorithm:TFiRR - VI
2 nd  Algorithm: TFiRR – Example
3 rd  Algorithm: RR floorplacement - I <ul><li>Simulated Annealing </li></ul><ul><ul><li>Objective Function </li></ul></ul...
3 rd  Algorithm: RR floorplacement - II <ul><li>Simulated Annealing: moves </li></ul><ul><ul><li>Swap two RRs </li></ul></...
3 rd  Algorithm: RR floorplacement – Example - I
3 rd  Algorithm: RR floorplacement – Example - II
Implementation <ul><li>Three simulated annealers written in C++ STL </li></ul>
Output Examples <ul><li>TFiRR </li></ul><ul><li>RR Floorplacement </li></ul>
EXPERIMENTAL RESULTS
Identification of the number of RRs
Partitioning’s impact on TFiRR <ul><li>Increasing the number of RFUs decreases the possibility to pick up the right one </...
Floorplacement – Success Rate <ul><li>Tests performed directly floorplacing RFUs </li></ul><ul><li>Execution time about 10...
Floorplacement – Aspect Ratio <ul><li>Tests performed directly floorplacing RFUs </li></ul>
COMPARISON WITH THE STATE OF THE ART
State of the art Authors Comm. Infrastructure Resource Aware Reconfiguration  Aware Device Limits Aware Bazargan et al. No...
Notes <ul><li>The comparsion is performed with respect to the description given by Yuh et al in [*] </li></ul><ul><li>Yuh’...
The Case Study <ul><li>A Reconfigurable Architecture (for Biomedical Purpose) on XC5VLX30T  </li></ul><ul><ul><li>Collecti...
The Proposed Solution <ul><li>It is a reconfigurable architecture with 2 static photos </li></ul>
Area assignments comparison <ul><li>Proposed solution </li></ul><ul><li>Yuh’s solution </li></ul>
Communication performances comparison <ul><li>Considering 100 M samples, 32 bit each, at 75 MHz.  The entire data are tran...
Conclusions - I <ul><li>An algorithm for the identification of area constraint for reconfigurable architectures has been i...
Conclusions - II <ul><li>Results have been published </li></ul><ul><ul><li>A. Montone, M.D. Santambrogio, D. Sciuto,  A De...
Future Works <ul><li>Take into consideration IOBs and inter modules communications </li></ul><ul><li>Partitioning consider...
Questions
Upcoming SlideShare
Loading in...5
×

UIC Thesis Montone

432

Published on

Published in: Business, Technology
0 Comments
0 Likes
Statistics
Notes
  • Be the first to comment

  • Be the first to like this

No Downloads
Views
Total Views
432
On Slideshare
0
From Embeds
0
Number of Embeds
0
Actions
Shares
0
Downloads
12
Comments
0
Likes
0
Embeds 0
No embeds

No notes for slide

Transcript of "UIC Thesis Montone"

  1. 1. Time-driven reconfiguration-aware floorplacer BY Alessio Montone [email_address] Thesis committee: S. Dutt (chair), A. Khokhar, M.D. Santambrogio UIC Thesis Defense: 05/08/2008
  2. 2. Rationale and Innovation <ul><li>Problem statement </li></ul><ul><ul><li>Given a reconfigurable architecture, find an on-chip position for each functional unit </li></ul></ul><ul><li>Innovative contribution: taking into account </li></ul><ul><ul><li>Target Device Heterogeneity </li></ul></ul><ul><ul><li>Target Device reconfiguation capabilities </li></ul></ul><ul><ul><li>Inter-FU Communication </li></ul></ul>
  3. 3. Aims <ul><ul><li>Considering the area assignment problem tailored for reconfigurable architectures, provide </li></ul></ul><ul><ul><li>a formalization of the problem, and </li></ul></ul><ul><ul><li>an approach (in 3 algorithms) for solving </li></ul></ul>
  4. 4. Outline <ul><li>Introduction </li></ul><ul><li>Floorplacement </li></ul><ul><li>The Proposed Approach </li></ul><ul><li>Experimental Results </li></ul><ul><li>Comparison with the state of the art </li></ul><ul><li>Conclusions and Future Works </li></ul><ul><li>Questions </li></ul>
  5. 5. INTRODUCTION
  6. 6. Reconfigurable Architectures - I <ul><li>On FPGAs </li></ul><ul><ul><li>Reconfigurable Devices </li></ul></ul><ul><ul><li>Heterogeneous </li></ul></ul><ul><ul><li>Reconfiguration Limits </li></ul></ul><ul><li>Different types of Reconfigurable Architectures: </li></ul><ul><ul><li>Total </li></ul></ul><ul><ul><li>Partial (Static) </li></ul></ul><ul><ul><li>Partial (Dynamic) </li></ul></ul>
  7. 7. Reconfigurable Architectures - I <ul><ul><li>Total </li></ul></ul>
  8. 8. Reconfigurable Architectures - I <ul><ul><li>Total </li></ul></ul><ul><ul><li>Partial (Static) </li></ul></ul>
  9. 9. Reconfigurable Architectures - II <ul><ul><li>Partial Dynamic </li></ul></ul>
  10. 10. Area Assignment Problem <ul><li>Let consider a Reconfigurable Architecture </li></ul><ul><ul><li>Given a scheduled task graph (TG) of the application </li></ul></ul><ul><ul><ul><li>Node: Reconfigurable Functional Unit (RFU) [*], A netlist obtained after post synthesis and technology mapping (i.e., before placement and routing) </li></ul></ul></ul><ul><ul><li>Aim : find an area assignment for each RFU </li></ul></ul>[*] K. Bazargan, R. Kastner, M.S.: 3-d floorplanning: Simulated annealing and greedy placement methods for reconfigurable computing systems . IEEE Rapid Systems Prototyping (1999)
  11. 11. Related Works - I <ul><li>[*] introduced the concept of 3D floorplanning for reconfigurable systems </li></ul><ul><ul><li>SA in order to solve HW/SW codesign problem </li></ul></ul><ul><ul><li>For each task choose between </li></ul></ul><ul><ul><ul><li>HW implementation </li></ul></ul></ul><ul><ul><ul><li>SW implementation </li></ul></ul></ul><ul><li>Limits </li></ul><ul><ul><li>No device limits considered </li></ul></ul><ul><ul><li>No communication infrastructure </li></ul></ul>[*] K. Bazargan, R. Kastner, M.S.: 3-d floorplanning: Simulated annealing and greedy placement methods for reconfigurable computing systems . IEEE Rapid Systems Prototyping (1999)
  12. 12. Related Works - II <ul><li>[*] is the state of art in 3D floorplanning </li></ul><ul><ul><li>Simulated Annealing over Transitive Closure Graph </li></ul></ul><ul><ul><li>Takes into account device reconfiguration limits </li></ul></ul><ul><li>Limits </li></ul><ul><ul><li>No heterogeneity considered </li></ul></ul><ul><ul><li>High overhead communication infrastructure solution [**] </li></ul></ul>[*] Ping-Hung Yuh, Chia-Lin Yang, Yao-Wen Chang, Hsin-Lung Chen : Temporal Floorplanning Using 3D-subTCG , Design Automation Conference, 2004 [**] S. P. Fekete, E. Kohler, and J. Teich: Optimal FPGA Module Placement with Temporal Precedence Constraints , Proc. DATE, 2001 .
  13. 13. FLOORPLACEMENT
  14. 14. Floorplanning vs. Placement Placement Floor plan Characteristic Floorplanning Placement # items <100 >10.000 Items (for FPGAs) IP-Core Slice, CLB Aim Find a position for each item obj. function depends mainly on Area mainly on Wirelength Constraints Items can be positioned everywhere There is a set of possible positions
  15. 15. Floorplacement - I <ul><li>Hierarchical Approach (Floorplanning + Partitioning) </li></ul>S. N. Adya, I. L. Markov, Fixed-outline Floorplanning: Enabling Hierarchical Design , IEEE Transaction on VLSI System, 2002 S. N. Adya, S. Chaturvedi, J. A. Roy, David A. Papa, I. L. Markov: Unification of Partitioning, Placement and Floorplanning , IEEE Intl. Conf. on CAD, 2004
  16. 16. Floorplacement - II <ul><li>Reconfigurable Functional Unit (RFU) </li></ul><ul><ul><li>A netlist obtained after post synthesis and technology mapping (i.e., before placement and routing) </li></ul></ul><ul><li>Reconfigurable Region (RR) </li></ul>
  17. 17. Floorplacement - III <ul><li>Resource Aware (i.e., not all positions are feasible) </li></ul><ul><ul><li>Device heterogeneity </li></ul></ul><ul><ul><li>Device Reconfiguration capabilities </li></ul></ul>
  18. 18. THE PROPOSED APPROACH
  19. 19. Proposed Problem Definition <ul><li>Aim </li></ul><ul><ul><li>Define RRs </li></ul></ul><ul><ul><li>For each task find </li></ul></ul><ul><ul><ul><li>find a RR </li></ul></ul></ul><ul><ul><ul><li>A position inside RR </li></ul></ul></ul><ul><li>Objective Function </li></ul><ul><ul><li>Min. Fragmentation </li></ul></ul><ul><li>Constraints </li></ul><ul><ul><li>Communication issues </li></ul></ul><ul><ul><li>Device limits </li></ul></ul>
  20. 20. Target Architecture and Devices <ul><li>Target Devices: Xilinx Virtex 4 - 5 </li></ul><ul><li>Target architecture based on EAPR design flow </li></ul>
  21. 21. Input
  22. 22. Proposed Approach: overview
  23. 23. 1 st Algorithm: Partitioning into RR <ul><li>Aim : identify the RRs and associate each RFU to one RR </li></ul><ul><li>How : partitioning the TG minimizing resource requirement variance of the RRs (moving and swapping nodes) </li></ul>Resource of type t required by RFU n , at static photo p
  24. 24. 2 nd Algorithm:TFiRR - I <ul><li>Temporal Floorplacement inside RR (TFiRR) </li></ul><ul><li>Aim : for each RR find a set of feasible width-height pairs </li></ul><ul><li>How : floorplacing RFUs inside corresponding RR </li></ul><ul><li>Assumption: RFUs’ height = height of the RR they belong to </li></ul><ul><li>Pseudo Code: </li></ul>
  25. 25. 2 nd Algorithm:TFiRR - II <ul><li>Let consider an iteration: </li></ul>
  26. 26. 2 nd Algorithm:TFiRR - III <ul><li>Let consider an iteration: </li></ul>
  27. 27. 2 nd Algorithm:TFiRR - IV <ul><li>Let consider an iteration: </li></ul>
  28. 28. 2 nd Algorithm:TFiRR - V <ul><li>Let consider an iteration: </li></ul>
  29. 29. 2 nd Algorithm:TFiRR - VI
  30. 30. 2 nd Algorithm: TFiRR – Example
  31. 31. 3 rd Algorithm: RR floorplacement - I <ul><li>Simulated Annealing </li></ul><ul><ul><li>Objective Function </li></ul></ul><ul><ul><li>Data Structure </li></ul></ul><ul><ul><ul><li>4 Constraint Lists (one per row) </li></ul></ul></ul>
  32. 32. 3 rd Algorithm: RR floorplacement - II <ul><li>Simulated Annealing: moves </li></ul><ul><ul><li>Swap two RRs </li></ul></ul><ul><ul><li>Move one RRs </li></ul></ul><ul><ul><li>Span over one more row </li></ul></ul><ul><ul><li>Un-Span over one less row </li></ul></ul><ul><li>After each move packing is performed (i.e., the floorplacement is compressed) </li></ul>
  33. 33. 3 rd Algorithm: RR floorplacement – Example - I
  34. 34. 3 rd Algorithm: RR floorplacement – Example - II
  35. 35. Implementation <ul><li>Three simulated annealers written in C++ STL </li></ul>
  36. 36. Output Examples <ul><li>TFiRR </li></ul><ul><li>RR Floorplacement </li></ul>
  37. 37. EXPERIMENTAL RESULTS
  38. 38. Identification of the number of RRs
  39. 39. Partitioning’s impact on TFiRR <ul><li>Increasing the number of RFUs decreases the possibility to pick up the right one </li></ul><ul><li>Partitioning is a precondition of the 3 rd algorithm in order to better exploit FPGA’s area (2D Floorplacement) </li></ul>TFiRR on Partitioned TG TFiRR on TG Execution Time 125ms 114ms 4m54s Width (normalized) 1.00 1.19 1.04
  40. 40. Floorplacement – Success Rate <ul><li>Tests performed directly floorplacing RFUs </li></ul><ul><li>Execution time about 100 ms (100K iterations) </li></ul>
  41. 41. Floorplacement – Aspect Ratio <ul><li>Tests performed directly floorplacing RFUs </li></ul>
  42. 42. COMPARISON WITH THE STATE OF THE ART
  43. 43. State of the art Authors Comm. Infrastructure Resource Aware Reconfiguration Aware Device Limits Aware Bazargan et al. No No Yes No Yuh et al. Limited, w/ High Overhead No Yes Yes Singhal et al. No No Yes No Feng et al. No Yes No No
  44. 44. Notes <ul><li>The comparsion is performed with respect to the description given by Yuh et al in [*] </li></ul><ul><li>Yuh’s approach does not support </li></ul><ul><ul><li>Multiple Resources </li></ul></ul><ul><ul><li>Existence of a Static side </li></ul></ul><ul><li>In order perform the comparison </li></ul><ul><ul><li>the case study has been chosen in order to avoid multiple resource limitation </li></ul></ul><ul><ul><li>Yuh’s approach has been extended to support a static side </li></ul></ul>[*] Ping-Hung Yuh, Chia-Lin Yang, Yao-Wen Chang, Hsin-Lung Chen : Temporal Floorplanning Using 3D-subTCG , Design Automation Conference, 2004
  45. 45. The Case Study <ul><li>A Reconfigurable Architecture (for Biomedical Purpose) on XC5VLX30T </li></ul><ul><ul><li>Collecting data from sensor </li></ul></ul><ul><ul><li>Elaborating them </li></ul></ul><ul><ul><li>Sending to a host computer thorough the net </li></ul></ul>
  46. 46. The Proposed Solution <ul><li>It is a reconfigurable architecture with 2 static photos </li></ul>
  47. 47. Area assignments comparison <ul><li>Proposed solution </li></ul><ul><li>Yuh’s solution </li></ul>
  48. 48. Communication performances comparison <ul><li>Considering 100 M samples, 32 bit each, at 75 MHz. The entire data are transferred by </li></ul><ul><ul><li>The Proposed Approach in 2.6 seconds </li></ul></ul><ul><ul><li>Yuh’s approach in 416.0 seconds </li></ul></ul>
  49. 49. Conclusions - I <ul><li>An algorithm for the identification of area constraint for reconfigurable architectures has been introduced </li></ul><ul><li>Novelties: taking into account </li></ul><ul><ul><li>Target device heterogeneity </li></ul></ul><ul><ul><li>Target device reconfiguration capabilities </li></ul></ul><ul><ul><li>Communication issues </li></ul></ul>
  50. 50. Conclusions - II <ul><li>Results have been published </li></ul><ul><ul><li>A. Montone, M.D. Santambrogio, D. Sciuto, A Design Workflow for the Identification of Area Constraints in Dynamic Reconfigurable Systems , IEEE International Symposium on Electronic Design, Test and Applications (DELTA), 2008 </li></ul></ul><ul><ul><li>A. Montone, M.D. Santambrogio, Area Constraint Evaluation for FPGAs , The Syndicated Q1-2008, A technical newsletter for FPGA, ASIC Verification and DSP Designers, Synplicity Incorporation </li></ul></ul><ul><li>Under revision: </li></ul><ul><ul><li>A Reconfiguration-aware Floorplacer for FPGAs, IEEE Field Programmable Logic (FPL), 2008 </li></ul></ul>
  51. 51. Future Works <ul><li>Take into consideration IOBs and inter modules communications </li></ul><ul><li>Partitioning considering clock regions </li></ul>
  52. 52. Questions
  1. A particular slide catching your eye?

    Clipping is a handy way to collect important slides you want to go back to later.

×