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UIC Thesis Candiloro
 

UIC Thesis Candiloro

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UIC Thesis Candiloro UIC Thesis Candiloro Presentation Transcript

  • Management and analysis of bitstream generators for Xilinx FPGAs BY Davide Candiloro [email_address] Thesis committee: John Lillis (chair), Marco D. Santambrogio, Piotr Gmytrasiewicz UIC Thesis Defense
  • Rationale and Main contribution
    • Xilinx software is mainly tailored to static designs
    • Absence of validation or support for partial dynamic reconfiguration techniques
    • -therefore-
    • Development of a novel flow for the debugging and validation of partial dynamic reconfigurable architectures on Xilinx FPGAs
      • Methodology to spot and address possible design flaws
    • Design of a framework to automate and ease the designer’s task independently from vendor software
  • Detailed Contribution
    • Automated constraint checking on Reconfigurable Regions
    • Guided error resolution and visual constraint editing
    • HW functionality area conflict monitoring
    • Exploration of the relocation possibilities for partial bitstreams
    • Analysis of the end result files of a PDR flow
    • Working on an architectural model and representation outside of Xilinx SW
  • Outline
    • FPGA technology
    • Partial dynamic reconfiguration, related issues, SoA
    • The proposed framework
      • Parser module
      • Reasoner module
      • Design alteration module
    • Case study
      • Description
      • Debugging and enhancement using REBIT
    • Contributions
    • Future works
  • Xilinx FPGA technology Three Xilinx families addressed Spartan 3 Virtex II Pro Virtex 4
    • Custom HW
    • Heterogeneous array
    • Per-resource numbering scheme
  • Xilinx FPGAs and Configuration Memory
  • Partial Dynamic Reconfiguration
    • static portion of design
    • several RRs where different RFUs are configured
    • communication via BUS Macros
    • Swap hardware at runtime, without disrupting the rest of the design. 2 key advantages :
      • efficient area use
      • adaptability of application
    • Application examples: adaptive control, image processing
  • Outline
    • FPGA technology
    • Partial dynamic reconfiguration, related issues, SoA
    • The proposed framework
      • Parser module
      • Reasoner module
      • Design alteration module
    • Case study
      • description
      • Debugging and enhancement using REBIT
    • Contributions
    • Future works
  • PDR flows and related issues
    • The flows require the manual definition of RRs, conforming to specific guidelines
      • The designer must refer correctly to the underlying architecture of the FPGA => error prone
    • Vendor software has been designed for static designs
      • There is no guarantee that the constraints for the RRs are respected by the Place and Route phase
      • This can inject further errors into the design: area conflicts and RR overflowing
    • Designer efforts are taken away from the actual application development
  • PDR issue 1: RR definition
    • The flows require constraints to be satisfied when defining RRs in the UCF ( User Constraints File ) file
    AREA_GROUP "RR1" RANGE = SLICE_X28Y64:SLICE_X41Y127; AREA_GROUP "RR1" RANGE = RAMB16_X2Y9:RAMB16_X2Y15;
  • PDR issue 2: Xilinx PAR programs
    • Place and Route built for static designs
    • Even if RR defined correctly, HW might overflow it
    • This situation is NOT reported to the designer
    • Can inject silent errors in the design due to configuration overwriting and area conflicts
  • State of the art
    • Planahead ® - 2008
      • Used to constrain the logic inside particular regions
      • Last version adds PDR support
      • An error situation is simply reported but
        • - not where - not how to overcome it
    • Floorplanner ® - 2008
      • Editor for the constraints of regions on the chip
      • Architecture-aware
      • NOT reconfiguration aware => guidelines not enforced
    • Chipscope ® - 2008
      • Used in debugging designs on Xilinx FPGAs
      • Only AFTER the design has been downloaded on board
    • Jbits ( discontinued ) - 2004/5
      • Provided low level access to configuration in bitstreams
  • Outline
    • FPGA technology
    • Partial dynamic reconfiguration, related issues, SoA
    • The proposed framework
      • Parser module
      • Reasoner module
      • Design alteration module
    • Case study
      • Description
      • Debugging and enhancement using REBIT
    • Contributions
    • Future works
  • Integration with the Earendil flow
    • Existing flow for defining FPGA reconfigurable apps
    • Proposed flow at the end of Earendil chain
    • Based upon reconfigurable architecture product files
    • May thus be inserted at the end of generic flows
  • The proposed Flow and Framework: Rebit C++ wxWidgets
  • Parser Module
    • Reads and parses input files to build the data model
      • RR definition
      • Bitstream occupation
      • Static photos
  • The configuration bitstream
    • Analogous structure between the three families
    • Occupation must be determined only on the basis of
      • Number of configuration words
      • Initial Frame Address Register (FAR) value
  • Frame addressing scheme (FAR)
    • Three families aggregation of datasheet information
    • Minimum (re)configuration unit = a frame
    • A column corresponds to an HW column (i.e. CLB column)
    • Bitstreams meaningful if composed by whole columns
    • FAR address is automatically incremented by the FPGA
    • How to determine the configured resources given a FAR address?
  • Implementation: area retrieval (1)
  • Assumptions on the configuration
    • Bitstreams show some regular features :
      • Gaps (PPCs) do not affect the number of frames needed to configure a column
      • Increasing the major address means moving from left to right columns on the FPGA
      • Hard-Cores paired with BRAMs are configured along with the BRAM interconnections
      • (V4) Row address increases from the center towards the edges, TOP/BOTTOM bit = 0 means top half
    • NOT documented by xilinx
    • Verified with FPGA Editor + bitstream inspection
  • Configuration memory maps Produced for each of the 4 FPGAs analyzed
    • For ANY frame allows to find the column configured on the device
    • Example for Spartan3 XC3S200
  • Implementation: area retrieval (2) SLICE X0Y0–X20Y41
  • Reasoner Module
    • Performs the constraint analysis on RRs
    • Occupation analysis for bitstream overflowing
    • Builds the conflict graph
  • Conflict Graph Conflict graph conflict=edge Incidence Matrix conflict=red which functionalities can be used at the same time?
  • Design Alteration Module Allows the user to perform modifications to the design 1) Redefining Reconfigurable Regions 2) Relocating partial bitstreams
  • The RPM grid
    • Model of the FPGAs used throughout the framework
    • Describes the available resources and relative positioning
    RPM = Relatively Placed Macros
  • Implementation: equivalent areas
    • Bitstream can be relocated in areas that
      • Have the same resources as the original
      • Preserve relative positions
    • Algorithm: sliding window
    • Partial grid is shifted onto global grid in all possible positions
    • If every element of the partial matches the underlying global a match is found
  • Outline
    • FPGA technology
    • Partial dynamic reconfiguration , related issues, SoA
    • The proposed framework
      • Parser module
      • Reasoner module
      • Design alteration module
    • Case study
      • Description
      • Debugging and enhancement using REBIT
    • Contributions
    • Future works
  • Demo description
    • Application
      • Edge detection on black and white digital images
        • Input: color digital images
        • Output: edge detected on the input images
    • Architecture
      • 2 IP-Cores
        • Filter (gray scale converter)
        • Edge Detector (E.D.)
      • Static area
        • GPP: PPC405
        • SW: standalone
      • Reconfigurable area
        • 1 reconfigurable regions
  • Data flow
    • sddd
    Input image Gray scale (Filter) Edge Detection (E.D.)
  • Performance analysis (1)
  • Reconfiguration performance
    • Area (Xilinx VIIP7)
      • System
        • Static area
          • Slices: 2100
        • Reconfigurable area
          • Constrained slices : 896
      • RFUs
        • Filter (Gray scale)
          • # Frames: 126
          • Bitstream size: 110 KB
        • Edge Detector (E.D.)
          • # Frames: 158
          • Bitstream size: 110 KB
    • Reconfiguration performance
      • Execution time: 0.31s
      • Rec. troughput :1,02 MB/sec
      • Rec. time: 0,1 sec
      • min data size: 32353 byte
        • min image size: 180x180
  • Performance analysis
  • Enhancement exploration
    • Is there any way in which we can enhance the application performance/flexibility?
    • Yes!
    • Exploring new design solutions using REBIT
    • (we will now see how)
  • Performance analysis
  • Outline
    • FPGA technology
    • Partial dynamic reconfiguration and related issues
    • The proposed framework
      • Parser module
      • Reasoner module
      • Design alteration module
    • Case study
      • Description
      • Debugging and enhancement using REBIT
    • Contributions
    • Future works
  • Case study: architecture
    • 2 image filters
    • 2 partial bitstrams
    • 1 RR
    • Synthesis finished, we now aim at:
      • Finding flaws in the design, if any
      • Correcting them
  • Case study: constraint validation
  • Case study: UCF editing
  • Case study: relocation
    • We have resolved the issues of the design…
    • Now we would like to explore new solutions
  • Case study : data model Conflict graph Feasible static photos Aim is to resolve every conflict within each of the static photos
  • Case study: area conflicts
  • Outline
    • FPGA technology
    • Partial dynamic reconfiguration and related issues
    • The proposed framework
      • Parser module
      • Reasoner module
      • Design alteration module
    • Case study description
    • Case study application
    • Contributions
    • Future works
  • Contributions of the work
    • Novel flow for the DRC of PDR architectures
    • Automation of the flow for the validation and debug of PDR architectures: no more manual steps
    • Visual editing and guided issue resolution
    • Configuration memory maps for the analyzed FPGAs
    • Relation of Xilinx bitstream format to the specific architecture
    • Development of a framework independent of Xilinx software that integrates knowledge of the architectural details
  • Future works
    • Adding support for new/other FPGAs to the system
    • Turn the reasoner module into an expert system , to develop further automation in the definition and validation of the system
    • Taking BUS Macros into account, i.e.: communication between different RFUs
    • Extend the data model with board data , not only chip
      • Develop methodologies to generate constraints based on IOB connections to the external board components
  • General Information
    • Webpage
      • www.dresd.org/?q=valerie
    • Mailing List
      • [email_address]
    • Contact
      • To have more information regarding valerie:
        • valerie@ dresd.org
      • For a complete list of information on how to contact us:
        • www.dresd.org/?q=contact_valerie
  • Questions? Thank you