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UIC Thesis Cancare

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  • 1. Modeling Methodologies for Dynamic Reconfigurable Systems Thesis Defense - May 2008 Fabio Cancare Thesis Committee: Tanya Berger-Wolf, Shantanu Dutt (Chair), Donatella Sciuto
  • 2. Rationale
    • Dynamic reconfiguration is a new and promising technique, it can be applied to cope with:
      • Lack of available resources
      • System adaptability
      • System reliability
    • Main drawback: implementing DR systems is a complex and time-consuming task
    • Model-based design paradigm allow the fast development of complex architecture
    Understand how it is possible to exploit the model-design paradigm in dynamic reconfigurable system implementation
  • 3. Innovative Contribution
    • Outline a model-based design flow for implementing large designs onto FPGAs with limited available resources
  • 4. Useful Novelties
    • Development of SysGen, a tool automating a portion of the low-level implementation phase
    • Implementation of a real-world application demanding for Dynamic Reconfigurable to enhance its perfomance
  • 5. Outline
    • Fundamental Concepts
    • Proposed Flow
      • High-level Modeling Phase
      • Low-level Implementation Phase
    • Case Study
    • Results
    • Conclusions and follows-up
  • 6. Outline
    • Fundamental Concepts
    • Proposed Flow
      • High-level Modeling Phase
      • Low-level Implementation Phase
    • Case Study
    • Results
    • Conclusions and follows-up
  • 7. Reconfigurable Computing “ Reconfigurable computing is intended to fill the gap between hardware and software, achieving potentially much higher performance than software, while maintaining a higher level of flexibility than hardware” (K. Compton and S. Hauck, Reconfigurable Computing: a Survey of Systems and Software , 2002)‏
  • 8. Reasons Behind
    • Applications often require performance which cannot be achieved by software
    • Applications often require to be flexible, modifiable, adaptable. Traditional hardware cannot achieve such results
    • Reconfigurable Computing techiniques are able to alter a concrete architecture once it has been deployed onto a high-performance device, in order to meet:
      • Resources constraints
      • Adaptability constraints
      • Reliability constraints
  • 9. Reconfigurable Computing Techniques
    • Targeted devices: PLDs (Programmable Logic Devices)‏
      • In particular, FPGAs (Fields Programmable Gate Arrays)‏
    • Several configuration techniques:
      • Static vs Dynamic
      • Partial vs Total
      • External vs Internal
  • 10. Useful Definitions
    • Core : a specific representation of a functionality. It is possible, for example, to have a core described in VHDL, in C or in an intermediate representation (e.g. a DFG)‏
    • IP-Core : a core described using a HDL combined with its communication infrastructure (i.e. the bus interface)‏
    • Reconfigurable Functional Unit : an IP-Core that can be plugged and/or unplugged at runtime in an already working architecture
    • Reconfigurable Region : a portion of the device area used to implement a reconfigurable core
    • Reconfigurable Slot : a high-level representation of a Reconfigurable Region
  • 11. Outline
    • Fundamental Concepts
    • Proposed Flow
      • High-level Modeling Phase
      • Low-level Implementation Phase
    • Case Study
    • Results
    • Conclusions and follows-up
  • 12. Flow Overview
    • Dynamic Partial Reconfiguration
    • Flow composed of two phases:
      • HLMP
      • LLIP
    • Support from system specification to system FPGA implementation
  • 13. High Level Modeling Phase
    • From the System Specification to the System Hardware Description
  • 14. HLMP – Tools and Techniques
    • Two techniques to model dynamic reconfigurable systems are proposed:
      • Reconfiguration Aware Modeling
      • Reconfiguration Unaware Modeling
  • 15. Simulink HDL Coder Compliant Models
  • 16. HLMP – Reconfiguration Aware Modeling
  • 17. HLMP – Reconfiguration Unaware Modeling
    • The first technique requires more knowledge but can lead to better results
  • 18. Low Level Implementation Phase
  • 19. System Generation
  • 20. LLIP – The Caronte Flow and SysGen
    • Main LLIP thesis contribution: SysGen
    SysGen
  • 21. Outline
    • Fundamental Concepts
    • Proposed Flow
      • High-level Modeling Phase
      • Low-level Implementation Phase
    • Case Study
    • Results
    • Conclusions and follows-up
  • 22. Real-world Application
    • Inpeco Corporation proposed to implement an embedded vision system exploiting dynamic reconfiguration
    • The goal is to provide functionalities such as:
      • Mapping of the test-tubes within a rack
      • Test-tube sample chromatic analysis
      • Test-tube lateral recognition
    • The system must also be as flexible as possible, since new functionalities may be required in the future
  • 23. Overall Description
  • 24. Real-world Application – System Model
  • 25. Outline
    • Fundamental Concepts
    • Proposed Flow
      • High-level Modeling Phase
      • Low-level Implementation Phase
    • Case Study
    • Results
    • Conclusions and follows-up
  • 26. Classical System
    • The static system implementation uses 96.9% of targeted device, a Xilinx XC4VFX12-FF668-10 FPGA, slices (and some functionalities are missing)‏
    FPGA Logical view FPGA Physical view Base Arch. RGB to grayscale Edge detection Circle detection Slot detection
  • 27. Dynamic Reconfigurable System
    • The dynamic reconfigurable implementation uses only 66.6% of available slices (26.0% of them can be reused)‏
    FPGA Logical view Physical view Static Area Base Arch. Rec. Area RFU Free Resource
  • 28. Occupation Data Static System Dynamic Reconfigurable System
  • 29. Classic System vs DR System
  • 30. Scientific Papers
    • A paper describing the improved version of the low-level implementation phase has been published in the RAW (Reconfigurable Architectures Workshop) 2008 proceedings:
    • A Design Flow Tailored for Self Dynamic Reconfigurable Architecture
    • (Marco D. Santambrogio, Donatella Sciuto and Fabio Cancare)‏
    • A paper describing the high-level modeling phase has been submitted at CODES+ISSS (International Conference on Hardware-Software Codesign and System Synthesis) 2008
  • 31. Outline
    • Fundamental Concepts
    • Proposed Flow
      • High-level Modeling Phase
      • Low-level Implementation Phase
    • Case Study
    • Results
    • Conclusions and follows-up
  • 32. Conclusions and Follow-ups
    • The model-based design paradigm has been successfully used as part of a dynamic reconfigurable system implementation flow
    • Two high-level modeling techniques were outlined
    • Enhancement of the Caronte low-level implementation phase
    • The proposed flow has been employed to produce a first version of an industrial application
    • Test the approach with other applications
    • For what concerns the case study, it is necessary to implement the other functionalities and to introduce DMA
  • 33. General Information
    • Webpage
      • www.dresd.org/?q=hlr
    • Mailing List
      • [email_address]
    • Contact
      • To have more information regarding HLR:
        • [email_address]
      • For a complete list of information on how to contact us:
        • www.dresd.org/?q=contact _hlr
  • 34. Any Question?
    • Thank you very much!

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