Thesis Giani UIC Slides EN

522 views

Published on

Published in: Education, Technology
0 Comments
0 Likes
Statistics
Notes
  • Be the first to comment

  • Be the first to like this

No Downloads
Views
Total views
522
On SlideShare
0
From Embeds
0
Number of Embeds
39
Actions
Shares
0
Downloads
11
Comments
0
Likes
0
Embeds 0
No embeds

No notes for slide
  • Thesis Giani UIC Slides EN

    1. 1. Core Identification for Reconfigurable Systems driven by Specification Self-Similarity Matteo Giani Univ. ID # 651157728 F. Balasa - A. A. Khokhar – D. Sciuto
    2. 2. Summary <ul><li>Motivations </li></ul><ul><li>Introduction </li></ul><ul><li>Aims </li></ul><ul><li>State of the Art </li></ul><ul><li>The Proposed Approach </li></ul><ul><ul><li>Rationale </li></ul></ul><ul><ul><li>Similarity Extraction </li></ul></ul><ul><ul><li>Specification Covering </li></ul></ul><ul><li>Implementation </li></ul><ul><li>Experimental results </li></ul><ul><li>Conclusions and Future Work </li></ul>
    3. 3. Motivations <ul><li>Area occupancy </li></ul><ul><ul><li>Image processing / robotics applications </li></ul></ul><ul><li>Survivability to changing requirements </li></ul><ul><ul><li>Evolving standards: cryptography, communications </li></ul></ul><ul><li>Reconfigurability for Reliability </li></ul><ul><ul><li>Single Event Upsets, Permanent Faults </li></ul></ul><ul><li>Designer constraints </li></ul><ul><ul><li>Unsatisfiable timing constraints given device area </li></ul></ul>
    4. 4. Reconfigurability: introduction
    5. 5. Reconfigurability: introduction
    6. 6. Reconfigurability: introduction
    7. 7. Reconfigurability: introduction
    8. 8. Reconfigurability: introduction
    9. 9. Reconfigurability: introduction
    10. 10. Reconfigurability: introduction Partial Total
    11. 11. Reconfigurability: introduction f i x Partial Total Embedded
    12. 12. MicroLAB’s System on Reconfigurable Chip Architecture
    13. 13. System on Reconfigurable Chip Architecture: physical constraints <ul><li>Area constraints: </li></ul><ul><ul><li>Trade-off between area used by fixed components and reconfigurable ones </li></ul></ul><ul><li>Communication issues: </li></ul><ul><ul><li>Bit-width of the communication infrastructure </li></ul></ul><ul><ul><li>Number of access points to the communication structure </li></ul></ul>
    14. 14. The Proposed Approach int test_code( int io , int * o1) { int a = 2, b = 10; Specification DFG Partitioned DFG Reconfigurable Implementation
    15. 15. Aims <ul><li>Definition of a specification partitioning approach, that: </li></ul><ul><ul><li>Aggregates elementary operations in the DFG into clusters suitable to be implemented as configurable modules </li></ul></ul><ul><ul><li>Identifies regular structures in the specification, aiming at generating reusable modules </li></ul></ul><ul><ul><ul><li>Save device area </li></ul></ul></ul><ul><ul><ul><li>Save reconfiguration time </li></ul></ul></ul>
    16. 16. State of the Art <ul><li>Temporal partitioning approaches </li></ul><ul><ul><li>Reconfigure the whole device at once </li></ul></ul><ul><ul><li>Impossible to hide reconfiguration times </li></ul></ul>
    17. 17. State of the Art <ul><li>Space-Time partitioning approaches </li></ul><ul><ul><li>Example </li></ul></ul>
    18. 18. State of the Art <ul><li>Common points among the different approaches </li></ul><ul><ul><li>Reconfiguration times badly affect the system’s performance </li></ul></ul><ul><ul><ul><li>Try to embed a loop in each partition </li></ul></ul></ul><ul><ul><ul><li>Try to minimize the need for reconfiguration </li></ul></ul></ul><ul><ul><li>Spatial partitioning approaches often rely on the designer for specification partitioning </li></ul></ul>
    19. 19. The Proposed Approach - Rationale <ul><li>Reconfiguration times impact heavily on the final solution’s latency </li></ul><ul><li>Reuse the configurable modules </li></ul><ul><li>Our approach: identify recurrent structures in the specification, automatically </li></ul>
    20. 20. The Proposed Approach int test_code( int io , int * o1) { int a = 2, b = 10; Specification DFG Partitioned DFG Reconfigurable Implementation
    21. 21. The Proposed Approach: Specification -> DFG <ul><li>The PandA framework </li></ul><ul><ul><li>Behavioral description </li></ul></ul><ul><ul><li>layer </li></ul></ul><ul><ul><li>Graph layer </li></ul></ul>
    22. 22. The Proposed Approach int test_code( int io , int * o1) { int a = 2, b = 10; Specification DFG Partitioned DFG Reconfigurable Implementation
    23. 23. The Proposed Approach: DFG Partitioning <ul><li>Objective: Partition the DFG identifying clusters that are repeated through the specification </li></ul><ul><li>Repeated structures -> Isomorphic Subgraphs </li></ul><ul><ul><li>Extraction of isomorphic subgraphs from a given graph is NP-complete </li></ul></ul><ul><ul><li>Need heuristics to be able to treat the problem </li></ul></ul>
    24. 24. The Proposed Approach: DFG Partitioning <ul><li>Our approach: two phases </li></ul><ul><ul><li>Template Identification </li></ul></ul><ul><ul><ul><li>Produce a collection of isomorphism equivalence classes, each containing some isomorphic subgraphs of the original specification </li></ul></ul></ul><ul><ul><li>Graph covering (template choice) </li></ul></ul><ul><ul><ul><li>Choose which among the identified templates are best suitable for implementation as (re)configurable modules </li></ul></ul></ul>
    25. 25. The Proposed Approach: Template Identification <ul><li>Two algorithms were considered for this phase: </li></ul><ul><ul><li>Reversed tree templates </li></ul></ul><ul><ul><ul><li>Copes with the complexity of the Isomorphic Subgraphs problem by restricting the shape of the subgraphs it identifies </li></ul></ul></ul><ul><ul><li>Free shape templates </li></ul></ul><ul><ul><ul><li>Copes with the complexity of the Isomorphic Subgraphs problem by expanding pairs of isomorphic subgraphs via a bipartite matching </li></ul></ul></ul>
    26. 26. Template Identification: Reversed-tree templates
    27. 27. Template Identification: Free-shape templates
    28. 28. Template Identification: Free-shape templates
    29. 29. Template Identification: Free-shape templates
    30. 30. Template Identification: Free-shape templates <ul><li>The algorithm produces a pair of isomorphic subgraphs for each run </li></ul><ul><ul><li>The produced pairs are used to build equivalence classes of isomorphic subgraphs, exploiting the transitivity of the isomorphism relation </li></ul></ul>
    31. 31. Template choice: metrics <ul><li>Largest Fit First </li></ul><ul><ul><li>Largest templates are best </li></ul></ul><ul><li>Most Frequent fit First </li></ul><ul><ul><li>Templates with the largest number of instances are best </li></ul></ul><ul><li>Communication Weight metrics </li></ul><ul><ul><li>E.g., #internal edges vs. #boundary edges ratio </li></ul></ul>
    32. 32. Implementation <ul><li>Implementation work was carried out as an extension to the PandA framework </li></ul><ul><ul><li>C++ </li></ul></ul><ul><ul><li>C++ STL </li></ul></ul><ul><ul><li>Boost Graph Library </li></ul></ul>
    33. 33. Experimental Results: Reversed-tree templates 40 6 6 FDCT 57 4 38 DES - des_encrypt 162 3 19 AES - decryptblock 151 3 16 AES - encryptblock #Templates Largest #Instances Largest Template Benchmark
    34. 34. Experimental Results: Free-shape templates 1470 2 62 FDCT 1802 2 100 DES - des_encrypt 11006 2 147 AES - decryptblock 6790 2 132 AES - encryptblock #Templates Largest #Instances Largest Template Benchmark
    35. 35. Experimental Results: Graph covering - free-shape 73.3 87.8 70.8 74.1 Cover % - Comm 6.4 sec 53.8 76.7 FDCT 8.3 sec 59.6 90.5 DES - des_encrypt 61 sec 51.7 85.31 AES - decryptblock 32.5 sec 32.7 74.3 AES - encryptblock CPU Time Cover % - MFF Cover % - LFF Benchmark
    36. 36. Experimental Results: Free-shape - AES - encryptblock <ul><li>Template size (nodes) vs. number of identified templates </li></ul>
    37. 37. Experimental Results: Free-shape - AES - encryptblock <ul><li>Template size (nodes) vs. number of instances of the most recurrent template </li></ul>
    38. 38. Experimental Results: Free-shape - AES - encryptblock <ul><li>Template size (nodes) vs. ratio between number of edges included in the clusters and number of edges cut by the cluster boundaries </li></ul>
    39. 39. Experimental Results: Free-shape - AES - encryptblock
    40. 40. Conclusions int test_code( int io , int * o1) { int a = 2, b = 10; Specification DFG Partitioned DFG Reconfigurable Implementation
    41. 41. References <ul><li>Purna, K. M. G. and Bhatia, D.: Temporal partitioning and scheduling data flow graphs for reconfigurable computers. IEEE Trans. Comput., 1999. </li></ul><ul><li>Ganesan, S. and Vemuri, R.: An integrated temporal partitioning and partial reconfiguration technique for design latency improvement, 2000. </li></ul><ul><li>Chowdary, A., Kale, S., Saripella, P. K., Sehgal, N. K., and Gupta, R. K.: Extraction of functional regularity in datapath circuits. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems,1999. </li></ul><ul><li>Bachl, S. and Brandenburg, F.-J.: Computing and drawing isomorphic subgraphs. In Graph Drawing, eds, S. G. Kobourov and M. T. Goodrich, 2002 </li></ul><ul><li>Donato, A., Ferrandi, F., Redaelli, M., Santambrogio, M. D., and Sciuto, D.: Caronte: A complete methodology for the implementation of partially dynamically self- reconfiguring systems on fpga platforms. In FCCM, IEEE Computer Society, 2005 </li></ul>
    42. 42. Conclusions, future work <ul><li>A partitioning approach was defined and implemented, to expose recurrent computing patterns in a system specification </li></ul><ul><ul><li>Starting point: C, SystemC specifications </li></ul></ul><ul><ul><li>Tests carried out on real-world examples </li></ul></ul><ul><li>Future Work </li></ul><ul><ul><li>Refinement of the template choice metrics: e.g. area fragmentation </li></ul></ul><ul><ul><li>Heuristics for fixed/reconfigurable modules choice </li></ul></ul><ul><ul><li>Online scheduling, placement of the reconfigurable cores </li></ul></ul>

    ×