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Rev1 HPPS Projects 2007

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Rev1 HPPS Projects 2007

Rev1 HPPS Projects 2007

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  • 1. H igh P erformance P rocessors and S ystems PdM – UIC joint master 2007 Instructor: Prof. Donatella Sciuto HPPS @ PdM – March 2007
  • 2. Outline
    • DReAMS
      • Alessandro Panella
      • Matteo Murgida
    • CITiES
      • Alessio Montone
      • Alessandro Meroni
      • Simone Corbetta
    • Operating System
      • Ivan Beretta
    • Design Flow
      • Antonio Piazzi
    • Polaris
      • Massimo Morandi
      • Marco Novati
    • HLR
      • Marco Maggioni
  • 3. What’s next
    • DReAMS
      • Alessandro Panella
      • Matteo Murgida
    • CITiES
      • Alessio Montone
      • Alessandro Meroni
      • Simone Corbetta
    • Operating System
      • Ivan Beretta
    • Design Flow
      • Antonio Piazzi
    • Polaris
      • Massimo Morandi
      • Marco Novati
    • HLR
      • Marco Maggioni
  • 4. D ynamic Re configurability A pplied to M ulti-FPGA S ystems
  • 5. DReAMS
    • Dynamic Reconfigurability
    • Applied to Multi-FPGA Systems
      • Branch of DRESD project
      • Inherits architectures and tools
    • Automatic workflow from VHDL system description to FPGA implementation
      • VHDL parsing and system simulation
      • System creation over a specific architecture
      • Bitstream creation and download onto FPGAs
  • 6. Multi-FPGA Partitioning Alessandro Panella [email_address]
  • 7. Project Organization
    • First Phase (15 Mar- 15 Apr)
      • Goals
        • State of the art analysis
        • Proposed approach: basic idea
    • Second Phase (15 Apr – 15 May)
      • Goal
        • Partitioning algorithm: development and implementation
    • Third Phase (15 May – 15 June)
      • Goal
        • Algorithm experimental evaluation
        • Physical evaluation using the Kmera (DIP) architecture
  • 8. First Phase: results
    • Analysis of several partitioning approaches
      • “ Classic” methods (KL, FM)
      • Iterative methods (Genetic, Tabu Search, Simulated Annealing)
      • Multilevel methods (METIS, hMETIS)
      • “ Structural” methods
    • Our approach (some hints)
      • Structural method
      • Exploit already existing tools to create the structural tree
      • Partitioning
        • Exploit the hyerarchy
        • Graph-covering approach
        • Focus on cutsize minimization
      • Pros
        • Modular fashion
        • Less communication problems
        • No need of “extremely” efficient algorithm
  • 9. What’s next…
    • Second Phase
      • Existing tools exloration (XST, EDK, Synplify Pro)
        • How to retrieve information?
        • How to build a structural tree?
        • How to use it?
      • Proposed algorithm
        • Definition
        • Implementation
        • Benchmark indentification
  • 10. What’s next
    • DReAMS
      • Alessandro Panella
      • Matteo Murgida
    • CITiES
      • Simone Corbetta
      • Alessandro Meroni
      • Alessio Montone
    • Operating System
      • Ivan Beretta
    • Design Flow
      • Antonio Piazzi
    • Polaris
      • Massimo Morandi
      • Marco Novati
    • HLR
      • Marco Maggioni
  • 11. Chimera Multi-FPGAs Architecture Definition Matteo Murgida [email_address]
  • 12. Project Organization
    • 1st Phase
      • Goals:
        • Digilent Spartan3- Starter Board study
        • Boards connection
    • 2nd Phase
      • Goals:
        • Distributed architecture description
        • Communication protocol definition and implementation
    • 3rd Phase
      • Goal:
        • Design a simple distribuited application to verify the correctness of the proposed approach
  • 13. First Phase: results
    • Choice of the A2 Expansion Connector to allow communication between two boards
    • Leds (located on one or two boards) control implemented both manually and via Microblaze
    • Configuration of the connector pins to support the future communication protocol
  • 14. What’s next…
    • Second phase organization…
      • Communication protocol design
      • Design the IP-Cores needed by the communication protocol
        • Distributed core design methodology - first definition
        • Reconstruction of the original data in the receiver
        • Implementation of the Call/Ack mechanism
      • Microblazes (one per board) data exchange
      • Application design and development to validate the proposed approach
  • 15. What’s next
    • DReAMS
      • Alessandro Panella
      • Matteo Murgida
    • CITiES
      • Alessio Montone
      • Alessandro Meroni
      • Simone Corbetta
    • Operating System
      • Ivan Beretta
    • Design Flow
      • Antonio Piazzi
    • Polaris
      • Massimo Morandi
      • Marco Novati
    • HLR
      • Marco Maggioni
  • 16. CITiES
  • 17. CITiES
  • 18. P rocessing E lements RE configuration I n R econfigurable A rchitectures Alessio Montone [email_address]
  • 19. Project Organization
    • First Phase
      • Time window: 15/March – 15/April
      • Goal:
        • bitstream structure analysis
        • memory mapping equations formalization
    • Second Phase
      • Time window: 15/April – 15/May
      • Goal: Implement mapping algorithm and equations
    • Third Phase
      • Time window: 15/May – 15/June
      • Goal: Harware Validation
  • 20. First Phase: results
    • Understanding of:
      • Bitstream Structure
      • Architectural Memory Mapping File (BMM)
      • Compiled source code (ELF)
    • Formalization of:
      • Code Splitting (on BRAM Blocks) Algorithm
      • BRAM Content Mapping Equations
  • 21. What’s next…
    • Second phase in details
      • Create a software that
        • Takes in input .bmm (BRAM used) and .elf (code) file
        • Outputs: memory configuration bitstream
        • Is device parametric
        • Is tailored for Xilinx Virtex II Pro Family FPGAs
  • 22. What’s next
    • DReAMS
      • Alessandro Panella
      • Matteo Murgida
    • CITiES
      • Alessio Montone
      • Alessandro Meroni
      • Simone Corbetta
    • Operating System
      • Ivan Beretta
    • Design Flow
      • Antonio Piazzi
    • Polaris
      • Massimo Morandi
      • Marco Novati
    • HLR
      • Marco Maggioni
  • 23. R econfiguration O riented Me trics Alessandro Meroni [email_address]
  • 24. Project Organization
    • First Phase
      • Time Window: 15/March - 15/April
      • Goal: Analysis of a well-known set of metrics
    • Second Phase
      • Time Window: 15/April - 15/May
      • Goal: Metrics definition and implementation
    • Third Phase
      • Time Window: 15/May - 15/June
      • Goal: Creation of a metrics Simulator
  • 25. First Phase: Results
    • Communication Achitectures analyzed
      • Point-to-point
      • Bus
      • Network-on-Chip
    • Performance Parameters evaluated
      • Latency, Bandwidth, Throughput
      • Topology
    • Cost Factors evaluated
      • Area usage
      • Power Consumption
    • Final Report that summerizes the results
  • 26. What’s next…
    • Second Phase
      • Metrics implementation and rules definition:
        • To improve the system performances
        • Tailored for the dynamic reconfiguration of the communication infrastructure, e.g.:
          • The creation of a new Processing Element
          • The change of the routing protocol exploited
      • Study and analysis of different simulators
        • NS2
  • 27. What’s next
    • DReAMS
      • Alessandro Panella
      • Matteo Murgida
    • CITiES
      • Alessandro Meroni
      • Alessio Montone
      • Simone Corbetta
    • Operating System
      • Ivan Beretta
    • Design Flow
      • Antonio Piazzi
    • Polaris
      • Massimo Morandi
      • Marco Novati
    • HLR
      • Marco Maggioni
  • 28. RE configurable C ommunication I nfrastructure F or E mbedded-systems Simone Corbetta [email_address]
  • 29. Project Organization
    • Goal : design a communication infrastructure tailored for reconfigurable FPGA-based embedded system
    • Organization : three phases
      • PHASE 1 (due to 12th April):
        • literature analysis on communication infrastructure paradigms and design choices
        • Survey
      • PHASE 2 (due to 17th May)
        • De Micheli architecture exploration
      • PHASE 3 (due to 17th June)
        • Communication infrastructure model definition
  • 30. First Phase: results
    • Literature analysis - Topics:
      • Communication infrastructure definition
      • CI design choices and trades-off
      • Understanding different CI paradigms
        • Advantages
        • Pitfalls
        • Improvements
      • Existing applications and solutions (both academic and commercial)
    • Survey : conveys study and analysis of different approaches.
      • The base for future work
  • 31. Next Phase
    • Networks-on-Chip
      • De Micheli state-of-the-art
      • VHDL description
      • Study, analysis
      • Improvements ( if any ...)
      • Tailoring for dynamically reconfigurable systems
    • Survey
      • Extension to specific De Micheli's NoC architecture
      • Communication infrastructure design methodology used in ReCIFE
  • 32. What’s next
    • DReAMS
      • Alessandro Panella
      • Matteo Murgida
    • CITiES
      • Alessio Montone
      • Alessandro Meroni
      • Simone Corbetta
    • Operating System
      • Ivan Beretta
    • Design Flow
      • Antonio Piazzi
    • Polaris
      • Massimo Morandi
      • Marco Novati
    • HLR
      • Marco Maggioni
  • 33. Development of an OS architecture-independent layer for dynamic reconfiguration Ivan Beretta [email_address]
  • 34. Project Organization
    • First Phase
      • Goal: State of the art and Boot process analysis
    • Second Phase
      • Goal: Implementation and comparison of the existing solutions
    • Third Phase
      • Goal: Definition of the new architecture-independent layer and testing
  • 35. First Phase: results
    • Analysis of the Caronte solution
      • Reconfiguration controller driver
      • IP-Core manager
    • Analysis of the DRESD-SW solution
      • Reconfiguration controller, MAC, LOL ,Reconfiguration Library
      • ROTFL Architecture
    • Caronte implementation study
      • Boot process
  • 36. What’s next…
    • Second phase:
      • Implementation of the DRESD operating system solution, based on ISE and EDK 9.1 version, on Xilinx Virtex II Pro VP7 and VP20
      • Previous solution comparison
        • Dynamic reconfiguration OS support abstraction layer: basic idea
  • 37. What’s next
    • DReAMS
      • Alessandro Panella
      • Matteo Murgida
    • CITiES
      • Alessio Montone
      • Alessandro Meroni
      • Simone Corbetta
    • Operating System
      • Ivan Beretta
    • Design Flow
      • Antonio Piazzi
    • Polaris
      • Massimo Morandi
      • Marco Novati
    • HLR
      • Marco Maggioni
  • 38. Design FLow Antonio Piazzi [email_address]
  • 39. Project organization
    • 1 st phase
      • Time window: 15 March – 15 April
      • Goal: Understand the execution of each previous tool (archgen, yara’s console script and inca)
    • 2 nd phase
      • Time window: 15 April – 15 May
      • Goal: Create an algorithm to merge each tool and a directory structure skeleton for each project type
    • 3 rd phase
      • Time window: 15 May – 15 June
      • Goal: Create and test the new tool with almost four architecture (2 YARA based and 2 InCA based) on Spartan and Virtex FPGA family
  • 40. First phase’s results
    • Study phase:
    • Archgen
      • Which are inputs and outputs and how this tool work
    • YaRA
      • Learn the directory structure and the console script which automates the work flow
    • InCA
      • Understand the early access reconfiguration flow proposed by Xilinx and how this tool complete its function
  • 41. The future is looking for us
    • Now : for each work flow and for each architecture we have to execute a file.
    • Tomorrow : Unique file to create an architecture and rebuild her workflow.
    Manual process Automated process Before After Planning VHDL gen. UCF and Com. Inf. Gen. Bitstream gen. Merging phase Planning VHDL gen. UCF and Com. Inf. Gen. Bitstream gen. Merging phase
  • 42. What’s next
    • DReAMS
      • Alessandro Panella
      • Matteo Murgida
    • CITiES
      • Alessio Montone
      • Alessandro Meroni
      • Simone Corbetta
    • Operating System
      • Ivan Beretta
    • Design Flow
      • Antonio Piazzi
    • Polaris
      • Massimo Morandi
      • Marco Novati
    • HLR
      • Marco Maggioni
  • 43. Polaris
  • 44. Effects of 2D Reconfiguration in a Reconfigurable System Massimo Morandi [email_address]
  • 45. Project Organization
    • First Phase:
      • General analysis of 2D reconfiguration
      • Detailed description of the new problems
    • Second Phase:
      • Analysis of possible solutions to those problems
      • Evaluation of alternatives
    • Third Phase:
      • Propose a new combined solution to effectively handle problems of 2D reconfiguration
  • 46. First Phase: results
    • Definition of the setting
    • Analysis of the advantages of 2D Reconfiguration
      • In area usage and performance
    • Definition and Analysis of:
      • the 2D-fragmentation problem
      • Bi-dimensional placement
      • Communication infrastructure creation in 2D vs 1D
      • Bitstream generation phase complexity increase
  • 47. What’s next…
    • Second phase:
      • Analysis of literature for proposed solutions to the problems defined in current phase
      • Selection of those that can be exploited in self partial dynamical run-time reconfiguration
      • Evaluation of different solutions to choose what is best suited to our problem
  • 48. What’s next
    • DReAMS
      • Alessandro Panella
      • Matteo Murgida
    • CITiES
      • Alessio Montone
      • Alessandro Meroni
      • Simone Corbetta
    • Operating System
      • Ivan Beretta
    • Design Flow
      • Antonio Piazzi
    • Polaris
      • Massimo Morandi
      • Marco Novati
    • HLR
      • Marco Maggioni
  • 49. Relocation for 2D Reconfigurable Systems Marco Novati [email_address]
  • 50. Project Organization
    • First Phase:
      • Examine Xilinx documentation of Virtex-4 and Virtex-5
      • Analyze the new bitstream structure
    • Second Phase:
      • Implement the new version of BiRF
    • Third Phase:
      • Test of BiRF²
      • Validate the results
  • 51. First Phase: results
      • Study of the new Virtex-4 and Virtex-5 FPGA:
        • Analysis of the new architecture:
          • New frame addressing
            • Possibility of addressing rows and columns
      • Generation and analysis of Virtex-4 and Virtex-5 bitstreams
  • 52. What’s next…
    • Implementation of BiRF²:
      • Define the functionality:
        • Determine fomulae for:
          • FAR calculation
          • CRC calculation
        • Create the new bitstream parser
      • Design the structure BiRF²
      • HW implementation
  • 53. What’s next
    • DReAMS
      • Alessandro Panella
      • Matteo Murgida
    • CITiES
      • Alessio Montone
      • Alessandro Meroni
      • Simone Corbetta
    • Operating System
      • Ivan Beretta
    • Design Flow
      • Antonio Piazzi
    • Polaris
      • Massimo Morandi
      • Marco Novati
    • HLR
      • Marco Maggioni
  • 54. H igh L evel R econfiguration Marco Maggioni marco.maggioni @dresd.org
  • 55. Project Organization
    • First Phase
      • Time window: 1 st month
      • Goal: Clustering
    • Second Phase
      • Time window: 2 nd month
      • Goal:Coloring
    • Third Phase
      • Time window: 3 rd month
      • Goal:Scheduling
    Clustered Graph Metric Circuit Representation Reconfigurable Clustered Graph Area Latency Rec. Time Power Isomorphic Target Architecture Database Gcc Frontend Partitioning Algorithm PandA Scheduling Algorithm
  • 56. First Phase: results
    • Theoretical Work
      • Redefinition of HLR workflow
        • Interfaces between various phases
        • Flexible clustering and scheduling algorithms
        • Suitable for future researches
    • Implementation of the Clustering phase
      • DFG Graph production
        • Used Panda --> 0.3 and 0.4
      • Clustering Algorithm
        • Used Isomorphic reconfigurable partitioning
  • 57. What’s next…
    • Second phase in details
      • Add to clustered graph reconfigurable info
        • Latency time
        • Reconfiguration time
        • Cluster area
        • Etc…
      • Definition of reconfigurable clustered graph structure
      • Implement a simple evaluation metric for latency times
      • Connect the flow with clustering phase