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RCW@DEI - ADL
RCW@DEI - ADL
RCW@DEI - ADL
RCW@DEI - ADL
RCW@DEI - ADL
RCW@DEI - ADL
RCW@DEI - ADL
RCW@DEI - ADL
RCW@DEI - ADL
RCW@DEI - ADL
RCW@DEI - ADL
RCW@DEI - ADL
RCW@DEI - ADL
RCW@DEI - ADL
RCW@DEI - ADL
RCW@DEI - ADL
RCW@DEI - ADL
RCW@DEI - ADL
RCW@DEI - ADL
RCW@DEI - ADL
RCW@DEI - ADL
RCW@DEI - ADL
RCW@DEI - ADL
RCW@DEI - ADL
RCW@DEI - ADL
RCW@DEI - ADL
RCW@DEI - ADL
RCW@DEI - ADL
RCW@DEI - ADL
RCW@DEI - ADL
RCW@DEI - ADL
RCW@DEI - ADL
RCW@DEI - ADL
RCW@DEI - ADL
RCW@DEI - ADL
RCW@DEI - ADL
RCW@DEI - ADL
RCW@DEI - ADL
RCW@DEI - ADL
RCW@DEI - ADL
RCW@DEI - ADL
RCW@DEI - ADL
RCW@DEI - ADL
RCW@DEI - ADL
RCW@DEI - ADL
RCW@DEI - ADL
RCW@DEI - ADL
RCW@DEI - ADL
RCW@DEI - ADL
RCW@DEI - ADL
RCW@DEI - ADL
RCW@DEI - ADL
RCW@DEI - ADL
RCW@DEI - ADL
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RCW@DEI - ADL

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  • 1. Architectural Description Languages: Past, Present, and Future Luca Fossati fossati@elet.polimi.it System Architectures Group October 29, 2008 Luca Fossati (SA Group) ADL: Past, Present, and Future October 29, 2008 1 / 44
  • 2. Outline 1 Overview of Architectural Description Languages 2 ADL based Design Methodologies 3 ADL: Most Important Examples 4 TRAP: TRansactional level Automatic Processor generator Luca Fossati (SA Group) ADL: Past, Present, and Future October 29, 2008 2 / 44
  • 3. ADL: Overview Outline 1 Overview of Architectural Description Languages What are They? Why? Classification 2 ADL based Design Methodologies 3 ADL: Most Important Examples 4 TRAP: TRansactional level Automatic Processor generator Luca Fossati (SA Group) ADL: Past, Present, and Future October 29, 2008 3 / 44
  • 4. ADL: Overview What are They? Architectural Description Languages: What are they? Architectural Description Languages High level specification of (processor) architectures used during their design, verification, implementation, simulation . . . Luca Fossati (SA Group) ADL: Past, Present, and Future October 29, 2008 4 / 44
  • 5. ADL: Overview What are They? Architectural Description Languages: What are they? Example Architecture Specification (User Manual) ADLs High level specification of (processor) architectures ADL Specification used for their design, verification, implementation, simulation . . . Model Test Toolkit Generation Generation Generation Hardware Prototype Test Programs Compiler, Simulator Validation Models Testbenches Assembler, Debugger ... ... ... Luca Fossati (SA Group) ADL: Past, Present, and Future October 29, 2008 5 / 44
  • 6. ADL: Overview What are They? Architectural Description Languages: What are they? ADLs capture the structure (hardware components and their connectivity) and the behavior (instruction-set) of processor architectures Luca Fossati (SA Group) ADL: Past, Present, and Future October 29, 2008 6 / 44
  • 7. ADL: Overview What are They? Architectural Description Languages: What are they? ADLs capture the structure (hardware components and their connectivity) and the behavior (instruction-set) of processor architectures Enable: high level processor modeling automatic analysis of processor architectures automatic prototype generation Luca Fossati (SA Group) ADL: Past, Present, and Future October 29, 2008 6 / 44
  • 8. ADL: Overview What are They? Architectural Description Languages: What are they? ADLs capture the structure (hardware components and their connectivity) and the behavior (instruction-set) of processor architectures Enable: high level processor modeling automatic analysis of processor architectures automatic prototype generation General Features Based on a simple specification: Formal and unambiguous semantics Easy correlation with the architecture manual Automatically produce tools for the design flow Compiler, Simulator, RTL code . . . Luca Fossati (SA Group) ADL: Past, Present, and Future October 29, 2008 6 / 44
  • 9. ADL: Overview Why? Architectural Description Languages: Why? Embedded Systems’ market stresses performance, customization, tight time-to-market, . . . Luca Fossati (SA Group) ADL: Past, Present, and Future October 29, 2008 7 / 44
  • 10. ADL: Overview Why? Architectural Description Languages: Why? Embedded Systems’ market stresses performance, customization, tight time-to-market, . . . Rapid Exploration and evaluation of system configuration is needed. Luca Fossati (SA Group) ADL: Past, Present, and Future October 29, 2008 7 / 44
  • 11. ADL: Overview Why? Architectural Description Languages: Why? Embedded Systems’ market stresses performance, customization, tight time-to-market, . . . Rapid Exploration and evaluation of system configuration is needed. Automation of the development process may help by: Keeping the model and its implementation consistent Providing a wide range of tools to aid the designer Luca Fossati (SA Group) ADL: Past, Present, and Future October 29, 2008 7 / 44
  • 12. ADL: Overview Why? Architectural Description Languages: Why? Embedded Systems’ market stresses performance, customization, tight time-to-market, . . . Rapid Exploration and evaluation of system configuration is needed. Automation of the development process may help by: Keeping the model and its implementation consistent Providing a wide range of tools to aid the designer A formal specification improves communication among team members It represents the first mapping from requirements to architectural components It enables evaluation of system’s target metrics Validation of early design decisions Luca Fossati (SA Group) ADL: Past, Present, and Future October 29, 2008 7 / 44
  • 13. ADL: Overview Classification Architectural Description Languages: Classification Architecture Description Languages (ADLs) Structural Mixed ADLs Behavioral ADLs (e.g. EXPRESSION, ADLs (e.g. LISA, nML) (e.g. ISDL) MIMOLA) Synthesis- Validation- Compilation- Simulation- oriented oriented oriented oriented Structural ADL Describes the low-level structure of the processor Helps achieving generality Suitable for hardware synthesis and RTL cycle-accurate simulation Unfit to efficiently model the ISA No compiler or functional simulator generation Luca Fossati (SA Group) ADL: Past, Present, and Future October 29, 2008 8 / 44
  • 14. ADL: Overview Classification Structural ADL RT-level description Describe in detail the structure of the basic processor elements (ALUs, registers, . . . ) Consistent work for the designer No close relation with the processor manual Overall ISA behavior not explicit it must be extracted from the structural description Difficult creation of tools which require behavioral information Luca Fossati (SA Group) ADL: Past, Present, and Future October 29, 2008 9 / 44
  • 15. ADL: Overview Classification Architectural Description Languages: Classification Architecture Description Languages (ADLs) Structural Mixed ADLs Behavioral ADLs (e.g. EXPRESSION, ADLs (e.g. MIMOLA) LISA, nML) (e.g. ISDL) Synthesis- Validation- Compilation- Simulation- oriented oriented oriented oriented Behavioral ADL Models the Instruction Set Architecture of the processor One-to-one correspondence with the architecture and instruction-set manual Suitable for compiler retargeting and functional simulation Luca Fossati (SA Group) ADL: Past, Present, and Future October 29, 2008 10 / 44
  • 16. ADL: Overview Classification Behavioral ADL High Level Description Focuses on the behavior rather than on its implementation Explicit specification of the instruction semantics Suitable for modeling the architecture functional behavior Detailed hardware structure is ignored Complex modeling of timing details Tedious and explicit specification of hazards, exceptions . . . Complex generation of synthesizable HDL code Luca Fossati (SA Group) ADL: Past, Present, and Future October 29, 2008 11 / 44
  • 17. ADL: Overview Classification Architectural Description Languages: Classification Architecture Description Languages (ADLs) Structural Mixed ADLs Behavioral ADLs (e.g. EXPRESSION, ADLs (e.g. MIMOLA) LISA, nML) (e.g. ISDL) Synthesis- Validation- Compilation- Simulation- oriented oriented oriented oriented Mixed ADL Capture both structural and behavioral details of the architecture Combine the benefits of Structural and Behavioral languages Luca Fossati (SA Group) ADL: Past, Present, and Future October 29, 2008 12 / 44
  • 18. ADL: Overview Classification Mixed ADL Suitable for a wide range of design automation tasks compiler retargeting functional, RTL, and cycle-accurate simulation architecture synthesis exploration of design choices Ammount of structural details kept to a minimum pipeline data and resource hazards register bypassing ... Luca Fossati (SA Group) ADL: Past, Present, and Future October 29, 2008 13 / 44
  • 19. ADL: Overview Classification Architectural Description Languages: Classification Objective-base classification Classification based on the primary purpose of the ADL, the objective for which it is optimized Architecture Description Languages (ADLs) Compilation-oriented ADL Simulation-oriented ADL Structural Mixed ADLs Behavioral ADLs (e.g. EXPRESSION, ADLs Synthesis-oriented ADL (e.g. MIMOLA) LISA, nML) (e.g. ISDL) Validation-oriented ADL Synthesis- Validation- Compilation- Simulation- oriented oriented oriented oriented Luca Fossati (SA Group) ADL: Past, Present, and Future October 29, 2008 14 / 44
  • 20. Design Methodologies Outline 1 Overview of Architectural Description Languages 2 ADL based Design Methodologies Overview Design Space Exploration Retargetable Compiler Generation Retargetable Simulator Generation Architecture Synthesis Validation 3 ADL: Most Important Examples 4 TRAP: TRansactional level Automatic Processor generator Luca Fossati (SA Group) ADL: Past, Present, and Future October 29, 2008 15 / 44
  • 21. Design Methodologies Overview ADL based Design Methodologies Embedded systems usually target narrow application classes Customization and heavy optimization is possible and needed Rapid exploration and evaluation of candidate architectures is necessary Luca Fossati (SA Group) ADL: Past, Present, and Future October 29, 2008 16 / 44
  • 22. Design Methodologies Overview ADL based Design Methodologies Embedded systems usually target narrow application classes Customization and heavy optimization is possible and needed Rapid exploration and evaluation of candidate architectures is necessary ADLs enable the automatic creation of development and support tools ADLs driven design allow to easily test and analyse different implementations and designs Luca Fossati (SA Group) ADL: Past, Present, and Future October 29, 2008 16 / 44
  • 23. Design Methodologies Design Space Exploration Design Space Exploration ADL Specification (Embedded Processor) Feedback (performance, power, code size...) Feedback (area, power, frequency ...) Hardware Compiler Simulator Generator Generator Generator Hardware Compiler Simulator Model Application Programs Luca Fossati (SA Group) ADL: Past, Present, and Future October 29, 2008 17 / 44
  • 24. Design Methodologies Retargetable Compiler Generation Retargetable Compiler Generation Definition A compiler is classified as retargetable if it can be adapted to generate code for different target processors with significant reuse of the compiler’s source code Necessary for exploiting the architecture’s custom features Luca Fossati (SA Group) ADL: Past, Present, and Future October 29, 2008 18 / 44
  • 25. Design Methodologies Retargetable Compiler Generation Retargetable Compiler Generation Definition A compiler is classified as retargetable if it can be adapted to generate code for different target processors with significant reuse of the compiler’s source code Necessary for exploiting the architecture’s custom features Various levels of retargetability: Instruction Set: code creation for different instruction sets Architectural details usually needed only for code optimizations e.g. Knowledge on pipeline structure may reduce stalls by enabling better scheduling Processor pipeline: generation of optimized code in front of changes in the processor pipeline Derived from the structural description of the processor’s pipeline Explicitly provided in Mixed ADLs Implicit in Structural ADLs Memory hierarchy: taken into account to optimize the runtime and the power consumption of processors Cache-Based systems (e.g. data-placement to reduce misses) Scratchpad-Based systems (automatic generation of code to manage scratchpads) Luca Fossati (SA Group) ADL: Past, Present, and Future October 29, 2008 18 / 44
  • 26. Design Methodologies Retargetable Compiler Generation Retargetable Compiler Generation Information necessary for compiler retargeting can be expressed in various ways: parameter based: microarchitectural parameters (operation latencies, number of functional units, number of registers, . . . ) are explicitly provided in the ADL (behavioral and mixed ADLs) structure based: the processor’s structure is described; microarchitectural parameters and pipeline details are automatically extracted (structural ADLs) the mapping between the target ISA and the compiler Intermediate Representation (IR) is usually explicitly provided e.g. GCC translates programs into RTL expressions ((plus:SI (reg:SI 2) (const int 10))) We have to provide mapping between ISA and RTL expressions Luca Fossati (SA Group) ADL: Past, Present, and Future October 29, 2008 19 / 44
  • 27. Design Methodologies Retargetable Simulator Generation Retargetable Simulator Generation Tradeoff-between retargetability and simulation speed: Limited retargetability: + high simulation speed - limited applicability in the design process Luca Fossati (SA Group) ADL: Past, Present, and Future October 29, 2008 20 / 44
  • 28. Design Methodologies Retargetable Simulator Generation Retargetable Simulator Generation Tradeoff-between retargetability and simulation speed: Limited retargetability: + high simulation speed - limited applicability in the design process Simulation is used in many phases of the development process: verification of system’s functionality verification of system’s timing behavior generation of quantitative metrics (power consumption, . . . ) Luca Fossati (SA Group) ADL: Past, Present, and Future October 29, 2008 20 / 44
  • 29. Design Methodologies Retargetable Simulator Generation Retargetable Simulator Generation Classification can be made on how the simulator structure refers to the processor’s: pin-accurate models the external processor interface bit-accurate precise description of the processor’s internal structure pipeline-accurate focuses on interaction among pipeline stages ... Luca Fossati (SA Group) ADL: Past, Present, and Future October 29, 2008 21 / 44
  • 30. Design Methodologies Retargetable Simulator Generation Retargetable Simulator Generation Classification can be made on how the simulator structure refers to the processor’s: pin-accurate models the external processor interface bit-accurate precise description of the processor’s internal structure pipeline-accurate focuses on interaction among pipeline stages ... Different abstraction levels: Functional: Simulates only the processor’s functionality Obtainable by modeling only the instructions set Cycle-accurate: Produces detailed timing information Requires the specification of some structural details Luca Fossati (SA Group) ADL: Past, Present, and Future October 29, 2008 21 / 44
  • 31. Design Methodologies Retargetable Simulator Generation Retargetable Simulator Generation IRQs, pins Phase- accurate model Pipelines Cycle- Structural Accuracy accurate model FU, registers y memories ac Instruction- accurate r cu Ac model Resources High-level Pseudo model Pseudo Processor Cycles Phases Instructions Instructions Temporal Accuracy Luca Fossati (SA Group) ADL: Past, Present, and Future October 29, 2008 22 / 44
  • 32. Design Methodologies Architecture Synthesis Architecture Synthesis Definition Generation of synthesizable HDL code of the described processor core Luca Fossati (SA Group) ADL: Past, Present, and Future October 29, 2008 23 / 44
  • 33. Design Methodologies Architecture Synthesis Architecture Synthesis Definition Generation of synthesizable HDL code of the described processor core Two approaches: Parametrized processor-core based (e.g. Tensilica): Partially customizable processor template A generic processor is configured changing cache size, register bank width . . . support tools (e.g. compiler, simulator) are automatically created Fully retargetable Customization of all the processor aspects Luca Fossati (SA Group) ADL: Past, Present, and Future October 29, 2008 23 / 44
  • 34. Design Methodologies Validation Validation Definition Assessment of the model’s correctness with respect to the specification Architecture Specification (Processor User Manual) Manual Problems verification Specification usually given in ADL Specification natural language (Golden Reference Model) Sim Generator Lack of a golden reference model HDL Generator Test-vector Simulator Generator ADL-driven validation: ADL lic Properties bo on specification as golden model at m lati Sy imu S different abstraction levels Same RTL output RTL Implementation ? Equivalenc Design e Checking Luca Fossati (SA Group) ADL: Past, Present, and Future October 29, 2008 24 / 44
  • 35. Design Methodologies Validation Validation Simulation Based: Test vectors are automatically generated from the ADL specification Output of the RTL implementation and of the simulator can be compared Model Checking Properties are created from the ADL specification Checked against the RTL implementation using model checkers and Symbolic simulators Equivalence Checking Formal techniques are used to prove that two versions of a design are equivalent or not Design versions need to be similar Can be used to check manually optimized with respect to the automatically generated golden model Luca Fossati (SA Group) ADL: Past, Present, and Future October 29, 2008 25 / 44
  • 36. Most Important Examples Outline 1 Overview of Architectural Description Languages 2 ADL based Design Methodologies 3 ADL: Most Important Examples Overview MIMOLA nML LISA Other Examples 4 TRAP: TRansactional level Automatic Processor generator Luca Fossati (SA Group) ADL: Past, Present, and Future October 29, 2008 26 / 44
  • 37. Most Important Examples Overview ADL: Most Important Examples MIMOLA: structural ADL Close to an HDL: its primary purpose is to create the hardware implementation of custom algorithms based on the PASCAL programming language nML: behavioral ADL minimizes the required amount of knowledge about the hardware structure used by the commercial tools Chess/Checkers LISA: mixed ADL contains information of both the structure and the instruction set of the target processor generates a variety of tools, from retargetable simulators to compilers and synthesisable HDL Others: EXPRESSION, MADL, ADL++, ArchC, . . . Luca Fossati (SA Group) ADL: Past, Present, and Future October 29, 2008 27 / 44
  • 38. Most Important Examples MIMOLA MIMOLA Machine Independent Micro-Programming Language Structural language designed for synthesis of Application Specific Processors Given a set of application specified using a high level language, MIMOLA creates an architecture emulating the overall structure of the applications If al algorithm for picture rotations is used, then a picture rotation processor will be created Enables the creation of: Cycle-accurate simulators Retargetable compilers Synthetizable HDL code Luca Fossati (SA Group) ADL: Past, Present, and Future October 29, 2008 28 / 44
  • 39. Most Important Examples MIMOLA MIMOLA Input: Pascal-like description of the behavior to be implemented Predefined available structural components Hints of the designer to create more efficient tools Same input language can be used for hardware components and program behavior Extension to Pascal for manual identification of parallelism Works as tool for high level synthesis It produces the hardware implementation of the specified behavior No instruction set will be used in the final design . . . Or produces a micro-code interpreter (as ASIP) The microcode is generated with the retargetable compiler It is also possible to directly describe hardware modules and call them from the application program Luca Fossati (SA Group) ADL: Past, Present, and Future October 29, 2008 29 / 44
  • 40. Most Important Examples MIMOLA MIMOLA: Example Algorithm definition: Definition of a module: Program Mult; module ALU(in a,b:word; var a, b, c: integer; fct s:(0), out f:word) begin begin a := 5; b := 7; c := 0; f <- case s of repeat 0: a + b c := c + a; b := b - 1; 1: a - b until b = 0; end; end. end; Luca Fossati (SA Group) ADL: Past, Present, and Future October 29, 2008 30 / 44
  • 41. Most Important Examples nML nML Behavioral language designed mainly for retargetable compilation Works at the abstraction of the programmer’s manual Requires the right ammount of knowledge of hardware structure Not too many details which complicate the description Enough details to assure high-quality results Used by the commercial tools Chess/Checkers compiler/cycle-accurate simulator Luca Fossati (SA Group) ADL: Past, Present, and Future October 29, 2008 31 / 44
  • 42. Most Important Examples nML nML Structural description: Models storage elements (memories, registers, . . . ) Connections are modeled by transitory storage pass a value from input to output without delay Transitories are also used to model resources that may lead to hardware conflicts at most one operation at a time can write to a transitory by allowing access to the memory only through a transitory we can enforce one access at a time Luca Fossati (SA Group) ADL: Past, Present, and Future October 29, 2008 32 / 44
  • 43. Most Important Examples nML nML Instruction-Set description: ISA structure specified using an attribute grammar Actions attributes are associated to instruction parts Implement the behavior of the instructions Model cycle accurate details (pipeline stages, hazards, . . . ) Instruction Set hierarchies employed to reduce verbosity of the description Different instruction parts can be combined with and or or rules Execution pipeline is explicitly modeled in the action attributes Behavior in front of Structural and Data hazards is explicitly specified Luca Fossati (SA Group) ADL: Past, Present, and Future October 29, 2008 33 / 44
  • 44. Most Important Examples nML nML: Example opn arith_mem_ind_instr (ar : arith_instr, mi : mem_ind_instr) { action { ar.action; mi.action; } syntax : ar.syntax quot;, quot; mi.syntax; image : ar.image::mi.image } Luca Fossati (SA Group) ADL: Past, Present, and Future October 29, 2008 34 / 44
  • 45. Most Important Examples nML nML: Example opn cond_branch (t : c_10, c : cond) { action { stage EX1: tT = t; switch (c){ case EQ: tC = eq(AS); ...... } } .... } Luca Fossati (SA Group) ADL: Past, Present, and Future October 29, 2008 35 / 44
  • 46. Most Important Examples LISA LISA Mixed language designed for retargetable compilation, simulation and HDL generation ASIP viewed first as an Instruction Set Architeture ISA description captures the syntax, encoding and behavior of the instructions On top we have the structural information Includes a timing model for each instruction ISA description is mapped on the structural details during model refinement Luca Fossati (SA Group) ADL: Past, Present, and Future October 29, 2008 36 / 44
  • 47. Most Important Examples LISA LISA Operations are the basic LISA building block Instruction descriptions are composed of several Operations Operations are connected by activations Operations can activate each other Behaviors are associated to Operations Described using the C programming language Various tools can be generated: Simulators (Interpreted, Compiler, . . . ) Retargetable Compiler Synthetizable HDL implementation Verification support tools (Equivalence Check, Test Vector Generation, . . . ) Luca Fossati (SA Group) ADL: Past, Present, and Future October 29, 2008 37 / 44
  • 48. Most Important Examples Other Examples Other Examples EXPRESSION Mixed-level ADL: it captures both structure and behavior Supports RISC, DSP, VLIW, and Superscalar architectures Enables retargetable compiler/simulator generation, design space exploration, synthesizable HDL generation, and functional verification MADL Aims at the creation of both the cycle-accurate simulators and compilers for a wide variety of architectures Used Operation State Machine (OSM) model to describe the processor special version of Extended Finite State Machines each state machine represents an ISA operation resources are modeled as tokens interaction between through tokens and OSMs control the progress of the operations this method encodes data dependencies, hazards, . . . Luca Fossati (SA Group) ADL: Past, Present, and Future October 29, 2008 38 / 44
  • 49. Most Important Examples Other Examples Other Examples ADL++ Behavioral language Initially thought for the generation of retargetable simulators, assemblers and disassemblers Targets complex architectures and Instruction Set, such as Intel IA-32 Based on the concept of templates: software module consisting of only the architecture-independent parts Decoupling of ISA and microarchitectural details it facilitates the extension of the ISA it facilitates the development of different microarchitectural implementations ArchC Behavioral Architectural Description Language based on SystemC Enables the generation of functional/cycle-accurate simulators and of assemblers Separates the instruction set from the microarchitectural description Instruction behavior is explicitly specified in C++ Luca Fossati (SA Group) ADL: Past, Present, and Future October 29, 2008 39 / 44
  • 50. TRAP Outline 1 Overview of Architectural Description Languages 2 ADL based Design Methodologies 3 ADL: Most Important Examples 4 TRAP: TRansactional level Automatic Processor generator Luca Fossati (SA Group) ADL: Past, Present, and Future October 29, 2008 40 / 44
  • 51. TRAP TRAP: TRansactional level Automatic Processor generator http://code.google.com/p/trap-gen/ Mixed ADL designed for the generation of fast and accurate Instruction Set Simulators Tight integration with SystemC and TLM 2.0 Language specified on top of Python Development still in progress: Only generation of functional simulators complete Full/Partial Retargeting of GCC compiler will be implemented enables true automatic design space exploration Automatic retargetable dynamic binary translation will be used to accelerate simulation Luca Fossati (SA Group) ADL: Past, Present, and Future October 29, 2008 41 / 44
  • 52. TRAP TRAP } Instruction Standalone Accurate Cycle Accurate ISA ISA Architecture Behavior Encoding Description Instruction TLM based Accurate Cycle Accurate Retargetable debugger Retargetable Compiler TRAP API ........ C++ Writer Python Luca Fossati (SA Group) ADL: Past, Present, and Future October 29, 2008 42 / 44
  • 53. TRAP TRAP Example: Architectural Description p r o c e s s o r = t r a p . P r o c e s s o r ( ' ARM7TDMI ' , s y s t e m c = F a l s e , i n s t r u c t i o n C a c h e = True ) processor . setLittleEndian () processor . setWordsize (4 , 8) p r o c e s s o r . s e t I S A ( ARMIsa . i s a ) regBank = t r a p . R e g i s t e r B a n k ( ' RB ' , 30 , 32 ) c p s r B i t M a s k = { ' N ' : ( 31 , 31 ) , ' Z ' : ( 30 , 30 ) , ' C ' : ( 29 , 29 ) , ' V ' : ( 28 , 28 ) , ' I ' : ( 7 , 7 ) , ' F ' : ( 6 , 6 ) , ' mode ' : ( 0 , 3 ) } c p s r = t r a p . R e g i s t e r ( ' CPSR ' , 32 , c p s r B i t M a s k ) r e g s = t r a p . A l i a s R e g B a n k ( ' REGS ' , 16 , ' RB [ 0−15 ] ' ) p r o c e s s o r . setMemory ( ' dataMem ' , 10 * 1024 * 1024 ) i r q = t r a p . I n t e r r u p t ( ' IRQ ' , p r i o r i t y = 0 ) processor . addIrq ( i rq ) p r o c e s s o r . s e t I R Q O p e r a t i o n ( ARMIsa . I R Q O p e r a t i o n ) Luca Fossati (SA Group) ADL: Past, Present, and Future October 29, 2008 43 / 44
  • 54. TRAP TRAP Example: ISA dataProc imm = t r a p . MachineCode ( [ ( ' cond ' , 4 ) , ( ' i d ' , 3 ) , ( ' opcode ' , 4 ) , ( ' s ' , 1 ) , ( ' r n ' , 4 ) , ( ' r d ' , 4 ) , ( ' r o t a t e ' , 4 ) , ( ' immediate ' , 8 ) ] ) dataProc imm . s e t V a r F i e l d ( ' r d ' , ( ' REGS ' , 0 ) ) dataProc imm . s e t B i t f i e l d ( ' i d ' , [ 0 , 0 , 1 ] ) opCode = c x x w r i t e r . Code ( ””” rd = rn + operand ; ””” ) a d c s h i f t i m m I n s t r = t r a p . I n s t r u c t i o n ( ' ADC si ' ) a d c s h i f t i m m I n s t r . setMachineCode ( dataProc imm shift , { ' opcode ' : [ 0 , 1 , 0 , 1 ] } , 'TODO ' ) a d c s h i f t i m m I n s t r . s e t C o d e ( opCode , ' e x e c u t e ' ) a d c s h i f t i m m I n s t r . a d d B e h a v i o r ( condCheckOp , ' e x e c u t e ' ) a d c s h i f t i m m I n s t r . a d d B e h a v i o r ( UpdatePSRSum , ' e x e c u t e ' , False ) a d c s h i f t i m m I n s t r . a d d T e s t ( { ' cond ' : 0xe , ' s ' : 0 , ' r n ' : 9 , ' r d ' : 10 , ' rm ' : 8 , ' s h i f t a m m ' : 0 , ' s h i f t o p ' : 0 } , { ' REGS [ 9 ] ' : 3 , ' REGS [ 8 ] ' : 3 } , { ' REGS [ 10 ] ' : 6 } ) Luca Fossati (SA Group) ADL: Past, Present, and Future October 29, 2008 44 / 44

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