RCIM 2008 - - ALTERA
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RCIM 2008 - - ALTERA

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RCIM 2008 - - ALTERA RCIM 2008 - - ALTERA Presentation Transcript

  • Altera FPGA strategy for a reconfigurable approach in industry application Reconfigurable Computing Italian Meeting 19 December 2008 Achille Montanaro Altera Account Manager © 2008 Altera Corporation—Public
  • This Decade: Programmable Solutions SOCs, FPGAs Logic design ASIC Fabless massively TTL integration methodology companies parallel arrays 300 Texas Instruments LSI Logic Broadcom Multi-core CPUs Sun Microsystems PMC-Sierra Motorola 275 DSPs Semiconductor TSMC Synopsys 250 Intel Mentor Graphics® 225 Billions ($) 200 175 150 125 100 75 50 25 70’s 80’s 90’s 00’s © 2008 Altera Corporation—Public Altera, Stratix, Arria, Cyclone, MAX, HardCopy, Nios, Quartus, and MegaCore are trademarks of Altera Corporation 2
  • Definition “reconfigurable HW in industry applications” What is reconfigurable HW architecture in real industry/telecom applications? “it is an architecture that doesn’t require on the fly Timing Analysis” Why? − Because most of product qualification are extensively done in Temperature Room Cycle and don’t let HW architecture changes © 2008 Altera Corporation—Public Altera, Stratix, Arria, Cyclone, MAX, HardCopy, Nios, Quartus, and MegaCore are trademarks of Altera Corporation 3
  • Programmable Solutions: 1985-2002 CPUs DSPs FPGAs Single cores Fine-grained arrays © 2008 Altera Corporation—Public Altera, Stratix, Arria, Cyclone, MAX, HardCopy, Nios, Quartus, and MegaCore are trademarks of Altera Corporation 4
  • Programmable Solutions: 2002-20XX CPUs DSPs Multi-cores Arrays FPGAs Single cores Multi-cores Coarse-grained Fine-grained Coarse-grained massively massively CPUs and DSPs parallel parallel processor arrays arrays with embedded hard IP blocks © 2008 Altera Corporation—Public Altera, Stratix, Arria, Cyclone, MAX, HardCopy, Nios, Quartus, and MegaCore are trademarks of Altera Corporation 5
  • Future trends © 2008 Altera Corporation—Public
  • Single-CPU Technology Limitations Transistors 10 billion Transistor Count 1 billion 100 million 10 million 1 million CPU Clock (MHz) 100 K Power (W) 10 K 1K 1975 2005 1985 1990 1970 2010 1980 1995 2000 © 2008 Altera Corporation—Public Altera, Stratix, Arria, Cyclone, MAX, HardCopy, Nios, Quartus, and MegaCore are trademarks of Altera Corporation 7
  • Parallel Speed-up: A Realistic View Speed-up 1024 Tasks with no data dependency Tasks with high data dependency 1 1 16 256 4 32 64 2 128 1024 8 512 Number of Processors © 2008 Altera Corporation—Public Altera, Stratix, Arria, Cyclone, MAX, HardCopy, Nios, Quartus, and MegaCore are trademarks of Altera Corporation 8
  • Future Architecture—Micro 2015 A Glimpse of Evolving Processor Architecture How All This Might Come Together in a Hypothetical Intel Future Architecture Is What We Call “Micro 2015”. This Hypothetical Micro 2015 Processor’s Features Include: Tens of billions of transistors in a single chip (as predicted by Built-in virtualization and trust mechanisms providing layers of Moore’s Law) abstraction to the applications and the OS to meet security, Billions of Transistors in a Single Chip Billions of Transistors in a Single Chip High-Speed Interconnects Linking Cores High-Speed Interconnects Linking Cores reliability, and manageability requirements. Reliable and reconfigurable circuit blocks with a built-in Within Groups & Among Groups CompatibilityGroups & software while providing teraflops of Within with existing Among Groups management infrastructure. Reconfigurable Circuits Blocks Reconfigurable Circuits Blocks supercomputer-like performance and new capabilities for new Parallelism at all levels that will be handled through an applications, workloads, and usage models abundant number of software and hardware threads. Chip- Parallelism at All Levels Parallelism at All Levels Level Multi-processing (CMP) will provide true parallelism with This is just one example of many possible architectural multiple low-power IA cores in a reconfigurable architecture scenarios since Micro 2015 is a composite of many capabilities that may or may not be incorporated into Software Compatibility With Existing Intel’s roadmap based with a built-in microkernel. Compatibility With Existing Software Special Purpose Low-Power Hardware Special Purpose Low-Power Hardware on current and future trends, requirements, and technological Engines for Real-Time Signal Processing Engines for Real-Time Signal Processing Special-purpose, low-power hardware engines for fixed constraints. Nonetheless, we believe it fairly represents the functions including, but not limited to, real-time signal overall shape of things to come. processing and graphics. Large High-Speed Global Reconfigurable High-speed High-Speed Global Reconfigurable Large interconnects linking cores within groups and among Paul Otellini, Intel President & CEO groups, as wellMemory On-Chip Memory Keynote Address, IDF On-Chip as special-purpose hardware and memory. The memory interconnect bandwidth will match the performance requirements of the processor and be in the multiple gigabytes per second range. www.intel.com/technology/computing/archinnov/platform2015/index.htm © 2008 Altera Corporation—Public Altera, Stratix, Arria, Cyclone, MAX, HardCopy, Nios, Quartus, and MegaCore are trademarks of Altera Corporation 9
  • 2015 Build The Future… Let’s Today! High-Speed Billions of Transistors High-Speed Billions of Transistors Interconnects Linking in a Single Chip Interconnects Linking in a Single Chip Cores Within Groups & Cores Within Groups & Among Groups Among Groups Reconfigurable Reconfigurable Circuit Blocks Circuit Blocks Large High-Speed Large High-Speed Global Reconfigurable Global Reconfigurable On-Chip Memory On-Chip Memory Parallelism at All Levels Parallelism at All Levels Special Purpose Low- Special Purpose Low- Power Hardware Power Hardware Compatibility With Compatibility With Engines for Real-Time Engines for Real-Time Existing Software Existing Software Signal Processing Signal Processing Standard HDL Design & Synthesis Stratix IV EP4SGX230 Available Now EP4SGX530 coming in few weeks © 2008 Altera Corporation—Public Altera, Stratix, Arria, Cyclone, MAX, HardCopy, Nios, Quartus, and MegaCore are trademarks of Altera Corporation 10
  • Multi-Core Systems on FPGAs Program memory Program memory Many programmable coarse-grained processors Functional units Functional units − Soft blocks in FPGA fabric Data memory Data memory − Each with local memory − Homogeneous or − Heterogeneous Programmable interconnect Software defined − C Compilation to Microcode © 2008 Altera Corporation—Public Altera, Stratix, Arria, Cyclone, MAX, HardCopy, Nios, Quartus, and MegaCore are trademarks of Altera Corporation 11
  • Modern FPGAs: Massively Parallel Stratix® IV device 680,000 logic elements 1,500 9-kbit memory blocks 64 144-k bits memory blocks 1,300 DSP blocks 1,100 programmable I/O blocks 48 transceivers © 2008 Altera Corporation—Public Altera, Stratix, Arria, Cyclone, MAX, HardCopy, Nios, Quartus, and MegaCore are trademarks of Altera Corporation 12
  • The Productivity Challenges Key Quartus II Software Advantage Team-based design and incremental Compile Design idea Can my engineers Can teams in different Will my system architecture Hardware design capture Construct systems quickly locations work on the same Meet my power budget? and easily? project? Hardware design RTL, Schematic SOPC TimeQuest Builder RTL Synthesis Are the power estimates Are we using the optimal reliable? system to close timing? Netlist “Fitting” (Map, Place, Route) Will the software Can my engineers reduce automatically optimize power, their compile times? Post-Fit Netlist and still meet timing? System-level Programming design Power management Team productivity Bitstream PowerPlay Software design Nios® II C2H Unique Quartus II C, C++ Can my software productivity technologies CPU software development engineers accelerate their save weeks to months of software code? engineering effort Object code © 2008 Altera Corporation—Public Altera, Stratix, Arria, Cyclone, MAX, HardCopy, Nios, Quartus, and MegaCore are trademarks of Altera Corporation 13
  • One Tool for All Your Design Needs CPLDs Low-cost FPGAs Structured Low-cost Transceiver FPGAs High-density, ASICs high-performance FPGAs Low Development Cost. Improved Productivity © 2008 Altera Corporation—Public Altera, Stratix, Arria, Cyclone, MAX, HardCopy, Nios, Quartus, and MegaCore are trademarks of Altera Corporation 14
  • Summary and Conclusions FPGA technology on 40nm allowing an incredible amount of reconfigurable silicon resources Universities are strongly encourage to take advantage and exploit innovation thanks this huge parallel technology available with low investment (no ASIC design) Reconfiguration must take into account industry constraints for practical applications − Cost of qualification for Time to Market and Productivity Reconfigurable block that take advantage of huge embedded memory are likely to be the most successfull example of reconfiguration in real industry applications © 2008 Altera Corporation—Public Altera, Stratix, Arria, Cyclone, MAX, HardCopy, Nios, Quartus, and MegaCore are trademarks of Altera Corporation 15