M etodologie   di  P rogettazine  H ardware e  S oftware   Reconfigurable Computing - Projects  -
EARENDIL <ul><li>Hail, Earendil, of mariners most renowned, the looked for that cometh at unawares, the longed for that co...
Earendil Design Flow: Basic Principles <ul><li>Modularity </li></ul><ul><ul><li>It is possible to use/design/manage a spec...
Earendil Design Flow: an Overview DRESD - HLR DRESD - BE
DRESD - HLR
DRESD - BE
DRESD Project examples
DRESD Project examples <ul><li>HLR </li></ul><ul><ul><li>Some theoretical aspects </li></ul></ul><ul><li>YaRA </li></ul><u...
DRESD Project examples <ul><li>HLR </li></ul><ul><ul><li>Some theoretical aspects </li></ul></ul><ul><li>YaRA </li></ul><u...
Reconfigurable Hardware: why?
Reconfigurable Hardware: why?
Motivations <ul><li>Increasing need for behavioral flexibility in embedded systems design </li></ul><ul><ul><li>Support of...
Aims <ul><li>Define and implement a partitioning approach to produce descriptions of module-based reconfigurable systems f...
Core Generation <ul><li>Process the specification graph, producing a set of clusters possibly to be used as configurable m...
Core Generation <ul><li>Result of the core generation phase: </li></ul><ul><li>Choice of which of the identified cores to ...
Cover Generation
Cover Generation
Cover Generation: Result
DRESD Project examples <ul><li>HLR </li></ul><ul><ul><li>Some theoretical aspects </li></ul></ul><ul><li>YaRA </li></ul><u...
YaRA: the embedded 1D approach
YaRA: fixed side
YaRA: FPGA Layers Clock Modulo  Riconf. Macro  HW PPC-405 BRAM e Moltiplicatori 18x18 Parte  Fissa CLB x CLB y Layer
DRESD Project examples <ul><li>HLR </li></ul><ul><ul><li>Some theoretical aspects </li></ul></ul><ul><li>YaRA </li></ul><u...
The Acheronte flow
DRESD Project examples <ul><li>HLR </li></ul><ul><ul><li>Some theoretical aspects </li></ul></ul><ul><li>YaRA </li></ul><u...
How to extend YaRA and Acheronte <ul><li>The “YaRA” side: </li></ul><ul><ul><li>HW-IPCM </li></ul></ul><ul><ul><li>D-ICAP ...
D-ICAP: DRESD - ICAP <ul><li>Objectives </li></ul><ul><ul><li>Define the DRESD – ICAP core, characterized by the following...
BiRF: Bitstream Relocation Filter <ul><li>Objectives </li></ul><ul><ul><li>Automatic replacement of a reconfiguration bits...
<ul><li>Objectives </li></ul><ul><ul><li>Realize a framework able to automatically generate an IP-Core starting from an al...
EDK System Creator <ul><li>Objectives </li></ul><ul><ul><li>Given a known EDK system architecture and a generic IP-Core de...
BUBA <ul><li>Objectives </li></ul><ul><ul><li>Assign the placement constraints for a reconfigurable core to be used with t...
ComIC <ul><li>Objectives </li></ul><ul><ul><li>Create the communication infrastructure for a given instance of the YARA ar...
ADG: Automatic Driver Generator <ul><li>Objectives </li></ul><ul><ul><li>Complete the IP-Core Generator tool work with the...
BAnMaT: Bitstream Analizer Manipulator Tool <ul><li>Objectives </li></ul><ul><ul><li>Bitstream analyzer </li></ul></ul><ul...
DRESD Project examples <ul><li>HLR </li></ul><ul><ul><li>Some theoretical aspects </li></ul></ul><ul><li>YaRA </li></ul><u...
Linux and reconfiguration  software architecture
Socket communication
Devices communication
Architectural Layers
R econfiguration  O f  T he  F PGA with  L inux <ul><li>Reconfiguration Manager </li></ul><ul><ul><li>Module Manager </li>...
L oad  O n  L inux <ul><li>Device Driver Manager </li></ul><ul><ul><li>Kernel module loading </li></ul></ul><ul><ul><li>Ke...
DRESD Project examples <ul><li>HLR </li></ul><ul><ul><li>Some theoretical aspects </li></ul></ul><ul><li>YaRA </li></ul><u...
Microlinux
Microlinux structure Kernel Source RamDisk image zImage.elf zImage.initrd.elf U-Boot & Bitstream Deployment on the board
Microlinux on Xilinx Virtex II Pro Virtex II Pro S D R A M F L A S H Driver Kernel APs MicroLinux boot image copy load boo...
Development framework and compilation chain Xilinx Platform Studio Xparameters.h ./genMicroLinux Kernel Image   <ul><li>Mo...
DRESD Project examples <ul><li>HLR </li></ul><ul><ul><li>Some theoretical aspects </li></ul></ul><ul><li>YaRA </li></ul><u...
SyCERS -  Objectives <ul><li>Define a novel model to describe reconfigurable systems </li></ul><ul><ul><li>Based on know H...
TLM e SystemC <ul><li>In TLM the system is first described at an high level of abstraction where communication details are...
The SyCERS methodology Specification Model Component Assembly Model Bus Functional Model <ul><li>Define the system functio...
A reconfigurable component using  SystemC <ul><li>It’s not possible to instantiate an sc_module during the simulation phas...
Reconfigurable component behavior
DRESD online <ul><li>http://www.dresd.org/ </li></ul><ul><li>http://www.dresd.org/forum/ </li></ul><ul><li>tel.elet.polimi...
Questions
END? <ul><li>Are you ready to see how deep the rabbit-hole goes?… </li></ul>
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MPHS (a.a. 06/07) - Reconfigurable Computing: Available Projects

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MPHS RC Prj

  1. 1. M etodologie di P rogettazine H ardware e S oftware Reconfigurable Computing - Projects -
  2. 2. EARENDIL <ul><li>Hail, Earendil, of mariners most renowned, the looked for that cometh at unawares, the longed for that cometh beyond hope! Hail Earendil, bearer of light before the Sun and Moon! Splendour of the Children of Earth, star in the darkness, jewel in the sunset, radiant in the morning! </li></ul><ul><li>But Earendil came, shining with white flame, and about Vingilot were gathered all the great birds of heaven. </li></ul><ul><li>[...]and a guard is set for ever on those walls, and Earendil keeps watch upon the ramparts of the sky. </li></ul><ul><li>J.R.R. Tolkien, Silmarillion </li></ul>
  3. 3. Earendil Design Flow: Basic Principles <ul><li>Modularity </li></ul><ul><ul><li>It is possible to use/design/manage a specific tool or the entire flow </li></ul></ul><ul><li>Scalability </li></ul><ul><ul><li>Easy to add or remove modules/projects </li></ul></ul><ul><li>Portability </li></ul><ul><ul><li>Earendil runs on different platforms: Linux, Mac OS X, Windows </li></ul></ul><ul><li>Ubiquity </li></ul><ul><ul><li>Decentralized collaboration to design and develop the Earendil project </li></ul></ul>
  4. 4. Earendil Design Flow: an Overview DRESD - HLR DRESD - BE
  5. 5. DRESD - HLR
  6. 6. DRESD - BE
  7. 7. DRESD Project examples
  8. 8. DRESD Project examples <ul><li>HLR </li></ul><ul><ul><li>Some theoretical aspects </li></ul></ul><ul><li>YaRA </li></ul><ul><ul><li>The reconfigurable architecture </li></ul></ul><ul><li>Acheronte </li></ul><ul><ul><li>The back-end design flow </li></ul></ul><ul><li>YaRA and Acheronte extension </li></ul><ul><li>LINUX </li></ul><ul><ul><li>Reconfiguration operating System support </li></ul></ul><ul><ul><li>Microlinux </li></ul></ul><ul><li>SyCERS </li></ul><ul><ul><li>The simulation framework </li></ul></ul><ul><li>LimboWARE </li></ul><ul><ul><li>Reconfigurable computing, some new idea </li></ul></ul><ul><li>VIRGIL </li></ul><ul><ul><li>A new possible flow </li></ul></ul>
  9. 9. DRESD Project examples <ul><li>HLR </li></ul><ul><ul><li>Some theoretical aspects </li></ul></ul><ul><li>YaRA </li></ul><ul><ul><li>The reconfigurable architecture </li></ul></ul><ul><li>Acheronte </li></ul><ul><ul><li>The back-end design flow </li></ul></ul><ul><li>YaRA and Acheronte extension </li></ul><ul><li>LINUX </li></ul><ul><ul><li>Reconfiguration operating System support </li></ul></ul><ul><ul><li>Microlinux </li></ul></ul><ul><li>SyCERS </li></ul><ul><ul><li>The simulation framework </li></ul></ul><ul><li>LimboWARE </li></ul><ul><ul><li>Reconfigurable computing, some new idea </li></ul></ul><ul><li>VIRGIL </li></ul><ul><ul><li>A new possible flow </li></ul></ul>
  10. 10. Reconfigurable Hardware: why?
  11. 11. Reconfigurable Hardware: why?
  12. 12. Motivations <ul><li>Increasing need for behavioral flexibility in embedded systems design </li></ul><ul><ul><li>Support of new standards, e.g. in media processing </li></ul></ul><ul><ul><li>Addition of new features </li></ul></ul><ul><li>Applications too large to fit on the device all at once </li></ul><ul><li>Current configurable devices allow us to obtain this </li></ul><ul><ul><li>FPGAs </li></ul></ul><ul><li>However, we need a way to process a specification to make it suitable for reconfigurable implementation </li></ul>
  13. 13. Aims <ul><li>Define and implement a partitioning approach to produce descriptions of module-based reconfigurable systems from a specification </li></ul><ul><li>In particular: </li></ul><ul><ul><li>Propose an algorithm to produce partitioning candidates </li></ul></ul><ul><ul><li>Propose criteria to evaluate the candidates </li></ul></ul><ul><ul><li>Use a proven scheduling and allocation approach for reconfigurable systems to complete the flow </li></ul></ul>
  14. 14. Core Generation <ul><li>Process the specification graph, producing a set of clusters possibly to be used as configurable modules </li></ul><ul><li>Self-similarity: rationale </li></ul><ul><ul><li>Configuring modules onto an FPGA takes time </li></ul></ul><ul><ul><li>Identifying recurrent structures allows us to reuse them </li></ul></ul><ul><ul><li>Gain in reconfiguration time, thus better performance </li></ul></ul><ul><li>Extracting regularity means detecting isomorphism </li></ul>
  15. 15. Core Generation <ul><li>Result of the core generation phase: </li></ul><ul><li>Choice of which of the identified cores to use </li></ul><ul><ul><li>Policies: LFF, MFF… </li></ul></ul><ul><li>Greedy approach: choose the winning core, then eliminate the overlapping ones </li></ul>
  16. 16. Cover Generation
  17. 17. Cover Generation
  18. 18. Cover Generation: Result
  19. 19. DRESD Project examples <ul><li>HLR </li></ul><ul><ul><li>Some theoretical aspects </li></ul></ul><ul><li>YaRA </li></ul><ul><ul><li>The reconfigurable architecture </li></ul></ul><ul><li>Acheronte </li></ul><ul><ul><li>The back-end design flow </li></ul></ul><ul><li>YaRA and Acheronte extension </li></ul><ul><li>LINUX </li></ul><ul><ul><li>Reconfiguration operating System support </li></ul></ul><ul><ul><li>Microlinux </li></ul></ul><ul><li>SyCERS </li></ul><ul><ul><li>The simulation framework </li></ul></ul><ul><li>LimboWARE </li></ul><ul><ul><li>Reconfigurable computing, some new idea </li></ul></ul><ul><li>VIRGIL </li></ul><ul><ul><li>A new possible flow </li></ul></ul>
  20. 20. YaRA: the embedded 1D approach
  21. 21. YaRA: fixed side
  22. 22. YaRA: FPGA Layers Clock Modulo Riconf. Macro HW PPC-405 BRAM e Moltiplicatori 18x18 Parte Fissa CLB x CLB y Layer
  23. 23. DRESD Project examples <ul><li>HLR </li></ul><ul><ul><li>Some theoretical aspects </li></ul></ul><ul><li>YaRA </li></ul><ul><ul><li>The reconfigurable architecture </li></ul></ul><ul><li>Acheronte </li></ul><ul><ul><li>The back-end design flow </li></ul></ul><ul><li>YaRA and Acheronte extension </li></ul><ul><li>LINUX </li></ul><ul><ul><li>Reconfiguration operating System support </li></ul></ul><ul><ul><li>Microlinux </li></ul></ul><ul><li>SyCERS </li></ul><ul><ul><li>The simulation framework </li></ul></ul><ul><li>LimboWARE </li></ul><ul><ul><li>Reconfigurable computing, some new idea </li></ul></ul><ul><li>VIRGIL </li></ul><ul><ul><li>A new possible flow </li></ul></ul>
  24. 24. The Acheronte flow
  25. 25. DRESD Project examples <ul><li>HLR </li></ul><ul><ul><li>Some theoretical aspects </li></ul></ul><ul><li>YaRA </li></ul><ul><ul><li>The reconfigurable architecture </li></ul></ul><ul><li>Acheronte </li></ul><ul><ul><li>The back-end design flow </li></ul></ul><ul><li>YaRA and Acheronte extension </li></ul><ul><li>LINUX </li></ul><ul><ul><li>Reconfiguration operating System support </li></ul></ul><ul><ul><li>Microlinux </li></ul></ul><ul><li>SyCERS </li></ul><ul><ul><li>The simulation framework </li></ul></ul><ul><li>LimboWARE </li></ul><ul><ul><li>Reconfigurable computing, some new idea </li></ul></ul><ul><li>VIRGIL </li></ul><ul><ul><li>A new possible flow </li></ul></ul>
  26. 26. How to extend YaRA and Acheronte <ul><li>The “YaRA” side: </li></ul><ul><ul><li>HW-IPCM </li></ul></ul><ul><ul><li>D-ICAP </li></ul></ul><ul><ul><li>BiRF </li></ul></ul><ul><ul><li>IP-Core Generator Tool </li></ul></ul><ul><ul><li>EDK System Creator </li></ul></ul><ul><li>The “Acheronte” side: </li></ul><ul><ul><li>BUBA </li></ul></ul><ul><ul><li>ComIC </li></ul></ul><ul><ul><li>ADG </li></ul></ul><ul><ul><li>BAnMaT </li></ul></ul>
  27. 27. D-ICAP: DRESD - ICAP <ul><li>Objectives </li></ul><ul><ul><li>Define the DRESD – ICAP core, characterized by the following parameters: </li></ul></ul><ul><ul><ul><li>Support for different bus infrastructure </li></ul></ul></ul><ul><ul><ul><li>Custom buffer memory dimension </li></ul></ul></ul><ul><ul><ul><li>Support DMA communication </li></ul></ul></ul><ul><li>Rationale </li></ul><ul><ul><li>Create a tool able to design a specific D-ICAP IP-Core according to the listed parameters </li></ul></ul>
  28. 28. BiRF: Bitstream Relocation Filter <ul><li>Objectives </li></ul><ul><ul><li>Automatic replacement of a reconfiguration bitstream </li></ul></ul><ul><ul><li>HW implementation of such a filter to speed-up its execution </li></ul></ul><ul><li>Rationale </li></ul><ul><ul><li>Target: reduce the amount of memory used to store partial bitstreams in dynamically self reconfiguring systems based on column-wise approach </li></ul></ul><ul><ul><li>Methodology: bitstream relocation </li></ul></ul><ul><ul><li>Solution: an hardware filter created to perform internal bitstream relocation </li></ul></ul>
  29. 29. <ul><li>Objectives </li></ul><ul><ul><li>Realize a framework able to automatically generate an IP-Core starting from an already existing core, provided by the user. </li></ul></ul><ul><ul><li>Support the PLB, OPB and the Wishbone BUS infrastructure </li></ul></ul><ul><ul><li>Fully support the YARA architecture </li></ul></ul><ul><ul><li>EDK compatible </li></ul></ul><ul><li>Rationale </li></ul><ul><ul><li>Reduce the overall IP-Core design time; </li></ul></ul><ul><ul><li>Speedup the reconfigurable cores generation phase in the Acheronte workflow; </li></ul></ul><ul><ul><li>Increment cores reuse with different communication infrastructures. </li></ul></ul>IP-Core Generator Tool
  30. 30. EDK System Creator <ul><li>Objectives </li></ul><ul><ul><li>Given a known EDK system architecture and a generic IP-Core description </li></ul></ul><ul><ul><ul><li>Automatic binding of the two inputs into a downloadable and executable bitstream </li></ul></ul></ul><ul><ul><li>Fully support the YARA architecture </li></ul></ul><ul><li>Rationale </li></ul><ul><ul><li>Speedup the creation of the YaRA fixed side according to the specific IP-core belonging to the input specification </li></ul></ul><ul><ul><li>Full-automatic support to the YaRA fixed side generation phase, combining it with the IPGen tool </li></ul></ul>
  31. 31. BUBA <ul><li>Objectives </li></ul><ul><ul><li>Assign the placement constraints for a reconfigurable core to be used with the YARA architecture </li></ul></ul><ul><ul><li>Find the best floorplanning constraints according with different optimization function, e.g. #AssignedCLBs/#UsedCLBs </li></ul></ul><ul><li>Rationale </li></ul><ul><ul><li>Automatic generation of the correct placement constraints into the UCF file for a self reconfigurable architecture </li></ul></ul>
  32. 32. ComIC <ul><li>Objectives </li></ul><ul><ul><li>Create the communication infrastructure for a given instance of the YARA architecture </li></ul></ul><ul><ul><li>Automatic XDL description manipulation to define the correct MacroHW for the bus infrastructure </li></ul></ul><ul><li>Rationale </li></ul><ul><ul><li>Provide a full-automatic support to the generation phase of the communication infrastructure </li></ul></ul>
  33. 33. ADG: Automatic Driver Generator <ul><li>Objectives </li></ul><ul><ul><li>Complete the IP-Core Generator tool work with the creation of the correct driver for a given IP-Core </li></ul></ul><ul><ul><li>Create the basic infrastructure for both the standalone and the OS version of the driver </li></ul></ul>
  34. 34. BAnMaT: Bitstream Analizer Manipulator Tool <ul><li>Objectives </li></ul><ul><ul><li>Bitstream analyzer </li></ul></ul><ul><ul><li>Easy API to manage the bitstream file </li></ul></ul><ul><ul><li>Difference bitstream file checker </li></ul></ul><ul><ul><li>Reconfiguration bitstream debugger </li></ul></ul>
  35. 35. DRESD Project examples <ul><li>HLR </li></ul><ul><ul><li>Some theoretical aspects </li></ul></ul><ul><li>YaRA </li></ul><ul><ul><li>The reconfigurable architecture </li></ul></ul><ul><li>Acheronte </li></ul><ul><ul><li>The back-end design flow </li></ul></ul><ul><li>YaRA and Acheronte extension </li></ul><ul><li>LINUX </li></ul><ul><ul><li>Reconfiguration operating System support </li></ul></ul><ul><ul><li>Microlinux </li></ul></ul><ul><li>SyCERS </li></ul><ul><ul><li>The simulation framework </li></ul></ul><ul><li>LimboWARE </li></ul><ul><ul><li>Reconfigurable computing, some new idea </li></ul></ul><ul><li>VIRGIL </li></ul><ul><ul><li>A new possible flow </li></ul></ul>
  36. 36. Linux and reconfiguration software architecture
  37. 37. Socket communication
  38. 38. Devices communication
  39. 39. Architectural Layers
  40. 40. R econfiguration O f T he F PGA with L inux <ul><li>Reconfiguration Manager </li></ul><ul><ul><li>Module Manager </li></ul></ul><ul><ul><li>Allocation Manager </li></ul></ul><ul><ul><li>Positioning Manager </li></ul></ul>
  41. 41. L oad O n L inux <ul><li>Device Driver Manager </li></ul><ul><ul><li>Kernel module loading </li></ul></ul><ul><ul><li>Kernel module unloading </li></ul></ul><ul><li>Device Manager </li></ul><ul><ul><li>Add device (/dev/…) </li></ul></ul><ul><ul><li>Remove device </li></ul></ul>
  42. 42. DRESD Project examples <ul><li>HLR </li></ul><ul><ul><li>Some theoretical aspects </li></ul></ul><ul><li>YaRA </li></ul><ul><ul><li>The reconfigurable architecture </li></ul></ul><ul><li>Acheronte </li></ul><ul><ul><li>The back-end design flow </li></ul></ul><ul><li>YaRA and Acheronte extension </li></ul><ul><li>LINUX </li></ul><ul><ul><li>Reconfiguration operating System support </li></ul></ul><ul><ul><li>Microlinux </li></ul></ul><ul><li>SyCERS </li></ul><ul><ul><li>The simulation framework </li></ul></ul><ul><li>LimboWARE </li></ul><ul><ul><li>Reconfigurable computing, some new idea </li></ul></ul><ul><li>VIRGIL </li></ul><ul><ul><li>A new possible flow </li></ul></ul>
  43. 43. Microlinux
  44. 44. Microlinux structure Kernel Source RamDisk image zImage.elf zImage.initrd.elf U-Boot & Bitstream Deployment on the board
  45. 45. Microlinux on Xilinx Virtex II Pro Virtex II Pro S D R A M F L A S H Driver Kernel APs MicroLinux boot image copy load boot contiene Absolute physical addresses
  46. 46. Development framework and compilation chain Xilinx Platform Studio Xparameters.h ./genMicroLinux Kernel Image <ul><li>Modular </li></ul><ul><li>Scalable </li></ul><ul><li>Small </li></ul>eMdev :
  47. 47. DRESD Project examples <ul><li>HLR </li></ul><ul><ul><li>Some theoretical aspects </li></ul></ul><ul><li>YaRA </li></ul><ul><ul><li>The reconfigurable architecture </li></ul></ul><ul><li>Acheronte </li></ul><ul><ul><li>The back-end design flow </li></ul></ul><ul><li>YaRA and Acheronte extension </li></ul><ul><li>LINUX </li></ul><ul><ul><li>Reconfiguration operating System support </li></ul></ul><ul><ul><li>Microlinux </li></ul></ul><ul><li>SyCERS </li></ul><ul><ul><li>The simulation framework </li></ul></ul><ul><li>LimboWARE </li></ul><ul><ul><li>Reconfigurable computing, some new idea </li></ul></ul><ul><li>VIRGIL </li></ul><ul><ul><li>A new possible flow </li></ul></ul>
  48. 48. SyCERS - Objectives <ul><li>Define a novel model to describe reconfigurable systems </li></ul><ul><ul><li>Based on know HDL (no new languages) </li></ul></ul><ul><ul><li>To be used in the early first stage of the project; to consider the reconfiguration at the system level </li></ul></ul><ul><li>Propose a complete framework for the simulation and the design of reconfigurable systems </li></ul><ul><ul><li>Providing system specification that can be simulated </li></ul></ul><ul><ul><li>Allowing fast parameters setting, e.g. number of reconfigurable blocks, reconfigurable time </li></ul></ul><ul><ul><li>Taking into account the software side of the final system </li></ul></ul>
  49. 49. TLM e SystemC <ul><li>In TLM the system is first described at an high level of abstraction where communication details are hidden </li></ul><ul><li>The key concept of TLM is the separation of functionality definitions from communication details </li></ul><ul><ul><li>to achieve this TLM uses through the concept of channel </li></ul></ul><ul><ul><ul><li>DEF.: SystemC channel is a class that implements one or more SystemC interface classes. A channel implements all the methods of the inherited interface classes. </li></ul></ul></ul><ul><ul><ul><li>DEF.: A SystemC port is a class template with and inheriting from a SystemC interface. Ports allow access of channels across module boundaries. </li></ul></ul></ul><ul><ul><ul><li>DEF.: A SystemC interface is an abstract class that provides only pure virtual declarations of methods referenced by SystemC channels and ports. </li></ul></ul></ul><ul><li>SystemC, starting from the 2.0 version, support TLM using the following structures: </li></ul>write() read() module A pA->write(v) module B v=pB->read() channel pA pB sc_interface sc_port
  50. 50. The SyCERS methodology Specification Model Component Assembly Model Bus Functional Model <ul><li>Define the system functionality </li></ul><ul><ul><li>No information regarding the final implementation </li></ul></ul><ul><li>Solution space exploration </li></ul><ul><ul><li>Provides the functionalities implementation details </li></ul></ul><ul><ul><li>No information regarding the communication </li></ul></ul><ul><li>Computed solution validation via the simulation </li></ul>
  51. 51. A reconfigurable component using SystemC <ul><li>It’s not possible to instantiate an sc_module during the simulation phase </li></ul><ul><li>It’s possible to modify the SC_THREAD and the SC_METHOD via: </li></ul><ul><ul><li>function pointer </li></ul></ul><ul><ul><li>sc_mutex </li></ul></ul><ul><li>Configuration </li></ul><ul><ul><ul><li>Combined with the reconfiguration time </li></ul></ul></ul><ul><li>Elaboration </li></ul><ul><ul><ul><li>Provided with the elaboration time </li></ul></ul></ul>*g() Reconfigurable Component (sc_module) Configuration (function pointer) mutex
  52. 52. Reconfigurable component behavior
  53. 53. DRESD online <ul><li>http://www.dresd.org/ </li></ul><ul><li>http://www.dresd.org/forum/ </li></ul><ul><li>tel.elet.polimi.it/dwl </li></ul>
  54. 54. Questions
  55. 55. END? <ul><li>Are you ready to see how deep the rabbit-hole goes?… </li></ul>
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