M etodologie   di  P rogettazine  H ardware e  S oftware   Reconfigurable Computing - Overview  -
Outline <ul><li>Reconfigurable Computing </li></ul><ul><ul><li>An overview </li></ul></ul><ul><ul><li>FPGA </li></ul></ul>...
What’s next… <ul><li>Reconfigurable Computing </li></ul><ul><ul><li>An overview </li></ul></ul><ul><ul><li>FPGA </li></ul>...
Reconfiguration <ul><li>The process of physically altering the location or functionality of network or system elements. Au...
Reconfiguration in everyday life <ul><li>Soccer </li></ul>Hockey Football (Partial – Static) (Complete – Static) (Partial ...
Where we are working Partial Total
Where we are working Partial Embedded f i x
Where we are working Single Device Distributed System
FPGA: overview CLB IOB Switch Box
FPGA: CLB VCC Switch Box SLICE TBUF Y X 67 66 75 74 SLICE_X66Y74
FPGA: CLB-coordinates
FPGA: Column-wise Structure <ul><li>5 kinds of column: Clock, RAM, I-RAM, I/O, CLB </li></ul><ul><li>Composed of a variabl...
FPGA: Configuration Bitstreams Represents initial module location Cyclic Redundancy Check is also involved
FPGA: Frames-coordinates
Architecture Model <ul><li>Due to technology limitations (or  specification  limitations?) the smallest reconfigurable por...
Architecture Model <ul><li>Each reconfigurable unit contains </li></ul><ul><li>Also, it can contain  execution units  requ...
Architecture Model <ul><li>Reconfiguration takes an affine time with respect to the size (in CLBs) of the reconfigured are...
Specification <ul><li>We are given a directed acyclic graph (DAG) </li></ul><ul><li>where O is the set of operations and P...
Temporal partitioning <ul><li>Temporal partitioning </li></ul><ul><ul><li>No partial reconfiguration: all the chip is runn...
Temporal partitioning <ul><li>Can be highly suboptimal: </li></ul>
Time-Space partitioning
Loops <ul><li>Tasks being repeated several times are commonly exploited to hide reconfiguration overhead. </li></ul>
Questions
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MPHD RC Overview

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MPHS (a.a. 06/07) - Reconfigrauble Computing Design: a Brief Overview

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MPHD RC Overview

  1. 1. M etodologie di P rogettazine H ardware e S oftware Reconfigurable Computing - Overview -
  2. 2. Outline <ul><li>Reconfigurable Computing </li></ul><ul><ul><li>An overview </li></ul></ul><ul><ul><li>FPGA </li></ul></ul><ul><ul><li>Configuration bitstream </li></ul></ul><ul><ul><li>Partitioning and scheduling </li></ul></ul><ul><li>MicroLAB </li></ul><ul><li>MPHS Projects </li></ul><ul><ul><li>Earendil </li></ul></ul><ul><ul><li>LimboWARE </li></ul></ul><ul><ul><li>VIRGIL </li></ul></ul><ul><ul><li>YaRA with Leon </li></ul></ul><ul><ul><li>DRPC </li></ul></ul><ul><ul><li>Scheduling for reconfigurable architecture </li></ul></ul><ul><ul><li>Linux and reconfiguration </li></ul></ul><ul><li>DRESD </li></ul><ul><ul><li>Philosophy </li></ul></ul><ul><ul><li>Team and meeting </li></ul></ul><ul><ul><li>Web </li></ul></ul><ul><ul><li>In the world </li></ul></ul><ul><li>Questions? </li></ul>
  3. 3. What’s next… <ul><li>Reconfigurable Computing </li></ul><ul><ul><li>An overview </li></ul></ul><ul><ul><li>FPGA </li></ul></ul><ul><ul><li>Configuration bitstream </li></ul></ul><ul><ul><li>Partitioning and scheduling </li></ul></ul><ul><li>MicroLAB </li></ul><ul><li>MPHS Projects </li></ul><ul><ul><li>Earendil </li></ul></ul><ul><ul><li>LimboWARE </li></ul></ul><ul><ul><li>VIRGIL </li></ul></ul><ul><ul><li>YaRA with Leon </li></ul></ul><ul><ul><li>DRPC </li></ul></ul><ul><ul><li>Scheduling for reconfigurable architecture </li></ul></ul><ul><ul><li>Linux and reconfiguration </li></ul></ul><ul><li>DRESD </li></ul><ul><ul><li>Philosophy </li></ul></ul><ul><ul><li>Team and meeting </li></ul></ul><ul><ul><li>Web </li></ul></ul><ul><ul><li>In the world </li></ul></ul><ul><li>Questions? </li></ul>
  4. 4. Reconfiguration <ul><li>The process of physically altering the location or functionality of network or system elements. Automatic configuration describes the way sophisticated networks can readjust themselves in the event of a link or device failing, enabling the network to continue operation. </li></ul><ul><li>Gerald Estrin, 1960 </li></ul>
  5. 5. Reconfiguration in everyday life <ul><li>Soccer </li></ul>Hockey Football (Partial – Static) (Complete – Static) (Partial – Dynamic)
  6. 6. Where we are working Partial Total
  7. 7. Where we are working Partial Embedded f i x
  8. 8. Where we are working Single Device Distributed System
  9. 9. FPGA: overview CLB IOB Switch Box
  10. 10. FPGA: CLB VCC Switch Box SLICE TBUF Y X 67 66 75 74 SLICE_X66Y74
  11. 11. FPGA: CLB-coordinates
  12. 12. FPGA: Column-wise Structure <ul><li>5 kinds of column: Clock, RAM, I-RAM, I/O, CLB </li></ul><ul><li>Composed of a variable number of frames </li></ul><ul><li>Double addressing: Major Address, Minor Address </li></ul>Major Address CLB Column
  13. 13. FPGA: Configuration Bitstreams Represents initial module location Cyclic Redundancy Check is also involved
  14. 14. FPGA: Frames-coordinates
  15. 15. Architecture Model <ul><li>Due to technology limitations (or specification limitations?) the smallest reconfigurable portion is a column 1 CLB wide --> |U|=68 reconfigurable units : </li></ul>1 CLB … FPGA
  16. 16. Architecture Model <ul><li>Each reconfigurable unit contains </li></ul><ul><li>Also, it can contain execution units requiring </li></ul><ul><li>CLBs </li></ul>
  17. 17. Architecture Model <ul><li>Reconfiguration takes an affine time with respect to the size (in CLBs) of the reconfigured area: </li></ul><ul><li>Or, in terms of clock cycles: </li></ul>
  18. 18. Specification <ul><li>We are given a directed acyclic graph (DAG) </li></ul><ul><li>where O is the set of operations and P are the precedences. </li></ul><ul><li>We also add a start node o S and a sink node o E so that all the other nodes are dominated by o S as post-dominated by o E . </li></ul>
  19. 19. Temporal partitioning <ul><li>Temporal partitioning </li></ul><ul><ul><li>No partial reconfiguration: all the chip is running, then it is stopped, totally reconfigured, and then runs again. </li></ul></ul>
  20. 20. Temporal partitioning <ul><li>Can be highly suboptimal: </li></ul>
  21. 21. Time-Space partitioning
  22. 22. Loops <ul><li>Tasks being repeated several times are commonly exploited to hide reconfiguration overhead. </li></ul>
  23. 23. Questions
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