DRESD In a Nutshell July07

DRESD in a Nutshell D ynamic R econfigurability in E mbedded S ystem D esign DRESD @ PdM – July 2007

Outline
MicroLAB
Reconfiguration
Motivations
Basic Definition
Reconfiguration in everyday life
SoC
New frontiers
DRESD
Philosophy
DRESD @ PdM
DRESD in the World
What you can do…
DRESD – Main Pojects

What’s next…
MicroLAB
Reconfiguration
Motivations
Basic Definition
SoC
New frontiers
DRESD
Philosophy
DRESD @ PdM
DRESD in the World
What you can do…

MicroLAB organization:
Thesis works: 50-60 /year
Class Projects: 80-100 /year
PhD students: 8
Researchers: 4
Professors: 8
MicroLAB Workstations:
Linux: 26
Windows: 3
Laptop (Linux/Win): 20
SUN: 15
MicroLAB

What’s next…
MicroLAB
Reconfiguration
Motivations
Basic Definition
SoC
New frontiers
DRESD
Philosophy
DRESD @ PdM
DRESD in the World
What you can do…

Motivations
Increasing need for behavioral flexibility in embedded systems design
Support of new standards, e.g. in media processing
Addition of new features
Applications too large to fit on the device all at once
Speedup the overall computation of the final system
However, we need a way to process a specification to make it suitable for reconfigurable implementation

Reconfiguration
The process of physically altering the location or functionality of network or system elements. Automatic configuration describes the way sophisticated networks can readjust themselves in the event of a link or device failing, enabling the network to continue operation.
Gerald Estrin, 1960

Soccer
Hockey Football (Complete – Static) (Partial – Dynamic) (Partial – Static)

SoC Reconfiguration f i x Partial Total Embedded

Different Scenarios... Single Device Distributed System

New frontiers
Architectures
Quantum computing
Reconfigurable computing is not equal to Xilinx
Nanotechnologies
Models and paradigms
Is the turing machine enough?
RDL: Reconfiguration Description language
Applications
Start from real worls needs
Benchmarking...
Knowledge about all these disciplines will help transform reconfigurable computing from an art to a science.

What’s next…
MicroLAB
Reconfiguration
Motivations
Basic Definition
SoC
New frontiers
DRESD
Philosophy
DRESD @ PdM
DRESD in the World
What you can do…
Questions?

DRESD Philosophy
Do or do not! There’s no try!
Master Yoda
I need to believe that something
extraordinary is possible!
Alicia Nash

DRESD @ PdM
and many more…

DRESD in regular curricula @ PdM a.a. 06/07
Undergraduate classes
Logic Synthesis (projects)
Graduate classes
SW Laboratory (projects)
Computer Architecture (projects)
High Performance Processors and Systems (projects and regular class)
Soft Computing (projects)
IA and Robotics Lab (projects)
Hardware Design Methodologies (projects)
Hardware and Software Design Methodologies (projects)
Embedded Systems (projects)

Students Overview
Undergraduate degree
03/04: 7 - 04/05: 18 - 05/06: 33
Total (06/07): 19
3° year: 19
Master degree
Total: 20
4° year: 14
5° year: 6
PhD involved in DRESD
Minor
2°year: 1
Major
1°year: 1
3° year: 1

DRESD in the WORLD @ June ‘07
Europe
Paderborn University and HNI
EPFL
USA
UIC
Northwestern
Companies
Synplicity
ImpulseC
Siemens

What you can do…
Meeting
Regular meeting every two weeks
DRESD Beer
3D-DRESD: the DRESD official meeting, July/August
Funding, materials (i.e., boards, tools), sponsorship
Web: www.dresd.org
Mailing List: [email_address]

What’s next…
MicroLAB
Reconfiguration
Motivations
Basic Definition
SoC
New frontiers
DRESD
Philosophy
DRESD @ PdM
DRESD in the World
What you can do…

DRESD – Main Projects
Blanket - architectures
Caronte – design flow
CITiES – communication infrastructure
DReAMS – multi-FPGAs
HLR – theoretical aspects
OSyRiS – operating system support
Polaris – placement and relocation
RDL - modeling and system specification
R4R - reliability
SyCERS – simulation
... Retargetable Compiler
... EHW – evolvable HW

Blanket
YaRA - Y ara is not a nother R econfigurable A rchitecture
Support relocation
Different communciation infrastructures
Hard/Soft-Core
Internal/External Reconfiguration
HARPE
Harvard-based Processing
Element Tailored for Partial
Dynamic Reconfigurable
Architectures

Caronte

CITiES
GOALS:
Define a suitable approach ( methodology ) to the design of a complete communication-centric FPGA-based reconfigurable architecture
Communication infrastructure design
Computational layer design
Metrics-driven design choices
MOTIVATIONS :
Allow the implementation of application-adaptable reconfigurable architectures in order to achieve:
Flexibility
Reliability
Performance

DReAMS
Dynamic Reconfigurability
Applied to Multi-FPGA Systems
Branch of DRESD project
Inherits architectures and tools
Automatic workflow from VHDL system description to FPGA implementation
VHDL parsing and system simulation
System creation over a specific architecture
Bitstream creation and download onto FPGAs

HLR
What is H igh L evel R econfiguration...?
Theoretical approach to dynamic reconfiguration...
Vision ... Reconfigurability has many advantages...
Mission ... Exploit these advantages to obtain best performance...
How ...? Adapting a system to this execution model managing complexity and drawbacks...

OSyRiS
Provide software support for dynamic partial reconfiguration on Systems-on-Chip running an operating system (i.e., LINUX ) .
Issues:
OS customization for specific architectures
Partial reconfiguration process management from the OS
Addition and removal of hardware reconfigurable components
Automatic loading and unloading of specific drivers for the IP-Cores upon components configuration/deconfiguration
Easier programming interface for specific drivers

Polaris
Create an integrated HW/SW system to manage relocation (1D and 2D) in reconfigurable architecture
Maintain information on FPGA status
Decide of how to efficiently allocate tasks
Provide support for effective task allocation
Perform bitstream relocation

RDL
R econfiguration D esign L anguage
Reconfiguration as an explicit feature in the system design
How to model a reconfigurable architecture
How to model/use reconfiguration at design-time
From DD (Desing Descriptio) to Bitstream

R4R
Designing reliable systems implemented on FPGAs, able to cope with the effects of faults caused by radiations
Appling already known and well studied detection and recovery techniques to novel scenarios
Exploiting dynamic partial reconfiguration to trigger the reconfiguration of the affected portion of the architecture
… while the rest of the system is still working
… without need to entirely reprogrammed the system

SyCERS
Define a novel model to describe reconfigurable systems
Based on know HDL (no new languages)
To be used in the early first stage of the project; to consider the reconfiguration at the system level
Propose a complete framework for the simulation and the design of reconfigurable systems
Providing system specification that can be simulated
Allowing fast parameters setting, e.g. number of reconfigurable blocks, reconfigurable time
Taking into account the software side of the final system

END?
Are you ready to see how deep the rabbit-hole goes?…

DRESD In a Nutshell July07

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