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Blanket project presentation


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  • 1. Blanket Team [email_address] Blanket Reconfigurable architecture and (IP) runtime reconfiguration support in D ynamic R econfigurability in E mbedded S ystem D esign
  • 2. Outline
    • Rationale
    • Objectives
    • Project Description
    • Subprojects:
      • YaRA, HARPE, ReCPU, SCAR, IPs
    • Blanket in DRESD
    • General information
  • 3. Rationale
    • Flexibility : many emerging products in communication, computing and consumer electronics demand that their functionality remains flexible also after the system has been manufactured.
      • Support of new standards, e.g. in media processing
      • Addition of new features
    • Cost reduction and reusability : While a ready-made FPGA can be bought for $500, an application-specific IC, or ASIC, can cost anywhere from $4 million to $50 million. “If you make a mistake on an FPGA, hey, you just reprogram it. “ Dean Collins, deputy director of DARPA's Microsystems Technology Office and program manager for the Trust in IC initiative.
    • Performance and runtime customization : reconfigurable computing is intended to fill the gap between hardware and software, achieving potentially much higher performance than software, while maintaining a higher level of flexibility than hardware. Therefore it is possible to apply reconfigurable solutions to systems such as:
      • biomedical implants i.e., an artificial art control
      • telecommunications i.e., adaptive intelligent routers
      • Moreover: intelligent nanorobot control, artificial audio and vision, intelligent transducers at bio-electronic interfaces,…
  • 4. Objectives
    • Exploit dynamic reconfigurability for different target reconfigurable architectures
    • Design innovative applicative solutions, with the corresponding architecture, towards real world needs
      • Explore novel architectural paradigms e.g, DNA computing, bio-inspired system
    • Increase the reconfiguration performance via novel techniques, i.e. runtime reconfigurable cores relocation
  • 5. Project Description
    • Blanket is a project related to the definition of novel reconfigurable architectures
    • Blanket can be seen as organized in mainly three different parts:
      • Generic reconfigurable architecture
        • YaRA (SoC, MultiFPGA)
        • HARPE (Multicore)
      • Application specific reconfigurable architecture
        • ReCPU (Regular Expression CPU)
        • SCAR (a sort of reconfigurable ASIP)
      • IP design to enhance the reconfiguration capabilities or to effectively use the reconfiguration at runtime
        • DRC , BiRF , C* ,...
  • 6. YaRA
    • YaRA : Y et a nother R econfigurable A rchitecture
    • The basic reconfigurable architecture defined
      • a Static area : a basic Harvard architecture
      • a Reconfigurable area : a device area composed of several reconfigurable regions
    YaRA v1: 1D, Whishbone BUS-based YaRA v2: 2D,CoreConnect-based
  • 7. HARPE
    • HARPE : a HAR vard-based P rocessing E lement tailored for partial dynamic reconfigurable architectures
      • marBram : a framework for the creation of memory configuration bitstreams
    • Propose a stand-alone processing element (PE)
      • Harvard Architecture
        • Soft-Processor
      • Suits reconfigurable architectures
      • Easily Configurable
        • User-Logic
        • Software (not supported by Xilinx tools)
    Bitstream File
  • 8. ReCPU
    • ReCPU : a new parallel and pipelined architecture for regular expression matching
    • Regular Expressions ( RE ) as a programming language
      • A RE is a sequence of instructions to be executed by the ReCPU processor
  • 9. SCAR
    • SCAR : S oft C ore A daptable a R chitecture
      • NaHA : Nios adaptable Harvard-based Architecture
      • What’s next: Leon, MicroBlaze...
    • Propose an adaptable Harvard-based architecture able to meet at the best the specific needs of an application that has to be executed on a reconfigurable device
  • 10. IPs
    • DRC : D RESD/ D ynamic R econfiguration C ontroller
      • Adaptable self-reconfiguration controllers
    • BiRF : Bi tstream R elocation F ilter
      • IP-Core used to implement runtime bitstream relocation
      • Relocation solution suitable for different target architecture (BiRF, BiRF 2 , …)
    • C* : all the runtime reconfiguration support in a unique pipelined reconfiguration controller
  • 11. Blanket in DRESD
    • Blanket and Caronte
      • marBram : a framework for the creation of memory configuration bitstreams
      • LimboWARE : postpone the decision of whether executing a task in HW or in SW moving it at run-time
      • VIRGIL : codesing framework
      • DRCGen : automatic tool to define the best DRC according to the working scenario
    • Blanket and CITiES
      • PEReIRA : active reconfigurable functional unit
      • YaRA (v3): a NoC based reconfigurable architecture
    • Blanket and HERA
      • YaRA (v2+): a 2D tile based reconfigurable architecture to implement online evolution
    • Blanket and OSyRIS
      • OS and architecture
    • Blanket and Polaris
      • C* and BiRF : IPs for runtime relocation
  • 12. General Information
    • Webpage
      • /blanket
    • Mailing List
      • [email_address]
    • Contact
      • To have more information regarding Polaris:
        • [email_address]
      • For a complete list of information on how to contact us: