Reconfigurable Computing: Systems historical contextualization Reasons behind FPGA(s)-based solution Marco D. Santambrogio...
Outline <ul><li>Basic Idea </li></ul><ul><li>A bird’s eye view on the Reconfigurable Computing </li></ul><ul><li>The roadm...
What’s next <ul><li>Basic Idea </li></ul><ul><li>A bird’s eye view on the Reconfigurable Computing </li></ul><ul><li>The r...
Reconfiguration <ul><li>The process of physically altering the location or functionality of network or system elements. Au...
Reconfigurable Computing <ul><li>Reconfigurable computing is defined as the study of computation using reconfigurable devi...
What’s next <ul><li>Basic Idea </li></ul><ul><li>A bird’s eye view on the Reconfigurable Computing </li></ul><ul><ul><li>T...
The RC Dawn <ul><li>The Estrin Fix-Plus Machine, 1959 </li></ul><ul><li>The Ramming Machine, 1977 </li></ul><ul><li>Harten...
Data Flow Machine (!FPGA) <ul><li>The Pact XPP Device </li></ul><ul><li>The NEC-DRP Architecture </li></ul><ul><li>The pic...
The Academic Efforts <ul><li>The Reconfigurable Architecture Workstation (RAW) - MIT </li></ul><ul><li>The Matrix Architec...
What are the drivers for this choice? <ul><li>Time: How long does it take to compute the answer? </li></ul><ul><li>Area: H...
What’s next <ul><li>Basic Idea </li></ul><ul><li>A bird’s eye view on the Reconfigurable Computing </li></ul><ul><li>The r...
The 90% – 10% Rule <ul><li>90% of the execution is spent in  10% of the code </li></ul><ul><ul><li>Inner loops in algorith...
Programmable System on a Chip <ul><li>No longer just a bunch of reconfigurable elements </li></ul><ul><li>DSPs, GPP, recon...
Multi-FPGA <ul><li>Heterogeneous Multi-FPGA system </li></ul>
What’s next <ul><li>Basic Idea </li></ul><ul><li>A bird’s eye view on the Reconfigurable Computing </li></ul><ul><li>The r...
Commercial FPGA Companies Lattice official webiste
Reconfigurable Multi-FPGA (taxonomy)  and FPGA vendors
Reconfigurable SoC (taxonomy)  and FPGA vendors
Xilinx FPGA and Configuration Memory
Questions
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3rd 3DDRESD: RC historical contextualization

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3rd 3DDRESD: RC historical contextualization

  1. 1. Reconfigurable Computing: Systems historical contextualization Reasons behind FPGA(s)-based solution Marco D. Santambrogio: marco.santambrogio@polimi.it 3DDRESD 3rd Edition, Goglio 2008
  2. 2. Outline <ul><li>Basic Idea </li></ul><ul><li>A bird’s eye view on the Reconfigurable Computing </li></ul><ul><li>The roadmap </li></ul><ul><li>Reasons behind Xilinx </li></ul>
  3. 3. What’s next <ul><li>Basic Idea </li></ul><ul><li>A bird’s eye view on the Reconfigurable Computing </li></ul><ul><li>The roadmap </li></ul><ul><li>Reasons behind Xilinx </li></ul>
  4. 4. Reconfiguration <ul><li>The process of physically altering the location or functionality of network or system elements. Automatic configuration describes the way sophisticated networks can readjust themselves in the event of a link or device failing, enabling the network to continue operation. </li></ul><ul><li>Gerald Estrin, 1960 </li></ul>
  5. 5. Reconfigurable Computing <ul><li>Reconfigurable computing is defined as the study of computation using reconfigurable devices </li></ul><ul><li>Christophe Bobda, 2007 </li></ul>Processor FPGA Full Custom Compilation time Performance low high low high
  6. 6. What’s next <ul><li>Basic Idea </li></ul><ul><li>A bird’s eye view on the Reconfigurable Computing </li></ul><ul><ul><li>The RC dawn and the FPGA revolution </li></ul></ul><ul><ul><li>Some !FPGA architecture </li></ul></ul><ul><ul><li>The accademic efforts </li></ul></ul><ul><ul><li>Choose the optimal hardware platform for a given application </li></ul></ul><ul><li>The roadmap </li></ul><ul><li>Reasons behind Xilinx </li></ul>
  7. 7. The RC Dawn <ul><li>The Estrin Fix-Plus Machine, 1959 </li></ul><ul><li>The Ramming Machine, 1977 </li></ul><ul><li>Hartenstein’s XPuter , 1980 </li></ul><ul><li>mid-1980s: the FPGA revolution/era </li></ul><ul><ul><li>The PAM Machine, SPLASH II, PRISM, Garp, DISC, DPGA </li></ul></ul>
  8. 8. Data Flow Machine (!FPGA) <ul><li>The Pact XPP Device </li></ul><ul><li>The NEC-DRP Architecture </li></ul><ul><li>The picoChip Reconfigurable Device </li></ul><ul><li>PicoChip solution: </li></ul><ul><ul><li>Array of heterogeneous processors </li></ul></ul><ul><ul><li>Communication flexibility between processors achieved through reconfigurable technology </li></ul></ul>Array Processing Element Switch Matrix Inter-picoArray Interface
  9. 9. The Academic Efforts <ul><li>The Reconfigurable Architecture Workstation (RAW) - MIT </li></ul><ul><li>The Matrix Architecture - MIT </li></ul><ul><li>The Reconfigurable Multimedia Array Coprocessor (REMARC) - Stanford </li></ul><ul><li>MorphoSys - University of California, Irvine </li></ul><ul><li>Chimaera – Northwestern </li></ul><ul><li>PipeRench - CMU </li></ul><ul><li>RaPiD - University of Washington </li></ul><ul><li>Garp – UC Berkeley </li></ul><ul><li>Bee2- UC Berkeley </li></ul>
  10. 10. What are the drivers for this choice? <ul><li>Time: How long does it take to compute the answer? </li></ul><ul><li>Area: How much silicon space is required to determined the answer? </li></ul><ul><li>Costs: How much does it costs (performance, $)? </li></ul><ul><li>Power: How much does it consume? </li></ul><ul><li>Processor generally fixes computing area. Problem evaluated over time through instructions. </li></ul><ul><li>FPGA can create flexible amount of computing area. Effectively, the configuration memory is the computing instruction. </li></ul>
  11. 11. What’s next <ul><li>Basic Idea </li></ul><ul><li>A bird’s eye view on the Reconfigurable Computing </li></ul><ul><li>The roadmap </li></ul><ul><ul><li>The 90% – 10% Rule </li></ul></ul><ul><ul><li>Programmable System on a Chip </li></ul></ul><ul><ul><li>Multi-FPGA </li></ul></ul><ul><li>Reasons behind Xilinx </li></ul>
  12. 12. The 90% – 10% Rule <ul><li>90% of the execution is spent in 10% of the code </li></ul><ul><ul><li>Inner loops in algorithms </li></ul></ul><ul><ul><li>Computational intense code </li></ul></ul><ul><li>10% of the execution is spent in 90% of the code </li></ul><ul><ul><li>Exceptions </li></ul></ul><ul><ul><li>User interaction </li></ul></ul><ul><li>The 10% computational intense code has to be executed as hardware on reconfigurable devices </li></ul><ul><li>The 90% exception code is run as executable files on processors </li></ul>
  13. 13. Programmable System on a Chip <ul><li>No longer just a bunch of reconfigurable elements </li></ul><ul><li>DSPs, GPP, reconfigurable elements, etc. etc... </li></ul>
  14. 14. Multi-FPGA <ul><li>Heterogeneous Multi-FPGA system </li></ul>
  15. 15. What’s next <ul><li>Basic Idea </li></ul><ul><li>A bird’s eye view on the Reconfigurable Computing </li></ul><ul><li>The roadmap </li></ul><ul><li>Reasons behind Xilinx </li></ul>
  16. 16. Commercial FPGA Companies Lattice official webiste
  17. 17. Reconfigurable Multi-FPGA (taxonomy) and FPGA vendors
  18. 18. Reconfigurable SoC (taxonomy) and FPGA vendors
  19. 19. Xilinx FPGA and Configuration Memory
  20. 20. Questions

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