3rd 3DDRESD: Floorplacer
Upcoming SlideShare
Loading in...5
×
 

3rd 3DDRESD: Floorplacer

on

  • 449 views

 

Statistics

Views

Total Views
449
Views on SlideShare
449
Embed Views
0

Actions

Likes
0
Downloads
4
Comments
0

0 Embeds 0

No embeds

Accessibility

Categories

Upload Details

Uploaded via as Microsoft PowerPoint

Usage Rights

© All Rights Reserved

Report content

Flagged as inappropriate Flag as inappropriate
Flag as inappropriate

Select your reason for flagging this presentation as inappropriate.

Cancel
  • Full Name Full Name Comment goes here.
    Are you sure you want to
    Your message goes here
    Processing…
Post Comment
Edit your comment

3rd 3DDRESD: Floorplacer 3rd 3DDRESD: Floorplacer Presentation Transcript

  • Time-driven reconfiguration-aware floorplacer BY Alessio Montone [email_address] NDDRESD Baceno, Goglio – Jul 29, 2008
  • Rationale and Innovation
    • Problem statement
      • Given a reconfigurable architecture, find an on-chip position for each functional unit
    • Innovative contribution: taking into account
      • Target Device Heterogeneity
      • Target Device reconfiguation capabilities
      • Inter-FU Communication
  • Aims
      • Considering the area assignment problem tailored for reconfigurable architectures, provide
      • a formalization of the problem, and
      • an approach (in 3 algorithms) for solving
  • Outline
    • Introduction
    • Floorplacement
    • The Proposed Approach
    • Experimental Results
    • Comparison with the state of the art
    • Conclusions and Future Works
    • Questions
  • INTRODUCTION
  • Introduction: Simulated Annealing
    • Metropolis Physics
      • An improving move is always accepted
      • A peggiorative move accepted with a decreasing probability
    • N. Metropolis, A.W. Rosenbluth, M.N. Rosenbluth, A.H. Teller, and E. Teller. "Equations of State Calculations by Fast Computing Machines". Journal of Chemical Physics, 1953
    • Sëma Kachalo, Hsiao-Mei Lu, and Jie Liang, Protein Folding Dynamics via Quantification of Kinematic Energy Landscape , Physical Review Letters, 2006
  • Reconfigurable Architectures - I
    • On FPGAs
      • Reconfigurable Devices
      • Heterogeneous
      • Reconfiguration Limits
    • Different types of Reconfigurable Architectures:
      • Total
      • Partial (Static)
      • Partial (Dynamic)
  • Reconfigurable Architectures - II
      • Partial Dynamic
  • Area Assignment Problem
    • Let consider a Reconfigurable Architecture
      • Given a scheduled task graph (TG) of the application
        • Node: Reconfigurable Functional Unit (RFU) [*], A netlist obtained after post synthesis and technology mapping (i.e., before placement and routing)
      • Aim : find an area assignment for each RFU
    [*] K. Bazargan, R. Kastner, M.S.: 3-d floorplanning: Simulated annealing and greedy placement methods for reconfigurable computing systems . IEEE Rapid Systems Prototyping (1999)
  • Related Works - I
    • [*] introduced the concept of 3D floorplanning for reconfigurable systems
      • SA in order to solve HW/SW codesign problem
      • For each task choose between
        • HW implementation
        • SW implementation
    • Limits
      • No device limits considered
      • No communication infrastructure
    [*] K. Bazargan, R. Kastner, M.S.: 3-d floorplanning: Simulated annealing and greedy placement methods for reconfigurable computing systems . IEEE Rapid Systems Prototyping (1999)
  • Related Works - II
    • [*] is the state of art in 3D floorplanning
      • Simulated Annealing over Transitive Closure Graph
      • Takes into account device reconfiguration limits
    • Limits
      • No heterogeneity considered
      • High overhead communication infrastructure solution [**]
    [*] Ping-Hung Yuh, Chia-Lin Yang, Yao-Wen Chang, Hsin-Lung Chen : Temporal Floorplanning Using 3D-subTCG , Design Automation Conference, 2004 [**] S. P. Fekete, E. Kohler, and J. Teich: Optimal FPGA Module Placement with Temporal Precedence Constraints , Proc. DATE, 2001 .
  • FLOORPLACEMENT
  • Floorplanning vs. Placement Placement Floor plan Characteristic Floorplanning Placement # items <100 >10.000 Items (for FPGAs) IP-Core Slice, CLB Aim Find a position for each item obj. function depends mainly on Area mainly on Wirelength Constraints Items can be positioned everywhere There is a set of possible positions
  • Floorplacement - I
    • Hierarchical Approach (Floorplanning + Partitioning)
    S. N. Adya, I. L. Markov, Fixed-outline Floorplanning: Enabling Hierarchical Design , IEEE Transaction on VLSI System, 2002 S. N. Adya, S. Chaturvedi, J. A. Roy, David A. Papa, I. L. Markov: Unification of Partitioning, Placement and Floorplanning , IEEE Intl. Conf. on CAD, 2004
  • Floorplacement - II
    • Reconfigurable Functional Unit (RFU)
      • A netlist obtained after post synthesis and technology mapping (i.e., before placement and routing)
    • Reconfigurable Region (RR)
  • Floorplacement - III
    • Resource Aware (i.e., not all positions are feasible)
      • Device heterogeneity
      • Device Reconfiguration capabilities
  • THE PROPOSED APPROACH
  • Proposed Problem Definition
    • Aim
      • Define RRs
      • For each task find
        • find a RR
        • A position inside RR
    • Objective Function
      • Min. Fragmentation
    • Constraints
      • Communication issues
      • Device limits
  • Target Architecture and Devices
    • Target Devices: Xilinx Virtex 4 - 5
    • Target architecture based on EAPR design flow
  • Input
  • Proposed Approach: overview
  • 1 st Algorithm: Partitioning into RR
    • Aim : identify the RRs and associate each RFU to one RR
    • How : partitioning the TG minimizing resource requirement variance of the RRs (moving and swapping nodes)
    Resource of type t required by RFU n , at static photo p
  • 2 nd Algorithm:TFiRR - I
    • Temporal Floorplacement inside RR (TFiRR)
    • Aim : for each RR find a set of feasible width-height pairs
    • How : floorplacing RFUs inside corresponding RR
    • Assumption: RFUs’ height = height of the RR they belong to
    • Pseudo Code:
  • 2 nd Algorithm:TFiRR - II
    • Let consider an iteration:
  • 2 nd Algorithm:TFiRR - III
    • Let consider an iteration:
  • 2 nd Algorithm:TFiRR - IV
    • Let consider an iteration:
  • 2 nd Algorithm:TFiRR - V
    • Let consider an iteration:
  • 2 nd Algorithm:TFiRR - VI
  • 2 nd Algorithm: TFiRR – Example
  • 3 rd Algorithm: RR floorplacement - I
    • Simulated Annealing
      • Objective Function
      • Data Structure
        • 4 Constraint Lists (one per row)
  • 3 rd Algorithm: RR floorplacement - II
    • Simulated Annealing: moves
      • Swap two RRs
      • Move one RRs
      • Span over one more row
      • Un-Span over one less row
    • After each move packing is performed (i.e., the floorplacement is compressed)
  • 3 rd Algorithm: RR floorplacement – Example - I
  • 3 rd Algorithm: RR floorplacement – Example - II
  • Implementation
    • Three simulated annealers written in C++ STL
  • Output Examples
    • TFiRR
    • RR Floorplacement
  • EXPERIMENTAL RESULTS
  • Identification of the number of RRs
  • Partitioning’s impact on TFiRR
    • Increasing the number of RFUs decreases the possibility to pick up the right one
    • Partitioning is a precondition of the 3 rd algorithm in order to better exploit FPGA’s area (2D Floorplacement)
    TFiRR on Partitioned TG TFiRR on TG Execution Time 125ms 114ms 4m54s Width (normalized) 1.00 1.19 1.04
  • Floorplacement – Success Rate
    • Tests performed directly floorplacing RFUs
    • Execution time about 100 ms (100K iterations)
  • Floorplacement – Aspect Ratio
    • Tests performed directly floorplacing RFUs
  • COMPARISON WITH THE STATE OF THE ART
  • State of the art Authors Comm. Infrastructure Resource Aware Reconfiguration Aware Device Limits Aware Bazargan et al. No No Yes No Yuh et al. Limited, w/ High Overhead No Yes Yes Singhal et al. No No Yes No Feng et al. No Yes No No
  • Notes
    • The comparsion is performed with respect to the description given by Yuh et al in [*]
    • Yuh’s approach does not support
      • Multiple Resources
      • Existence of a Static side
    • In order perform the comparison
      • the case study has been chosen in order to avoid multiple resource limitation
      • Yuh’s approach has been extended to support a static side
    [*] Ping-Hung Yuh, Chia-Lin Yang, Yao-Wen Chang, Hsin-Lung Chen : Temporal Floorplanning Using 3D-subTCG , Design Automation Conference, 2004
  • The Case Study
    • A Reconfigurable Architecture (for Biomedical Purpose) on XC5VLX30T
      • Collecting data from sensor
      • Elaborating them
      • Sending to a host computer thorough the net
  • The Proposed Solution
    • It is a reconfigurable architecture with 2 static photos
  • Area assignments comparison
    • Proposed solution
    • Yuh’s solution
  • Communication performances comparison
    • Considering 100 M samples, 32 bit each, at 75 MHz. The entire data are transferred by
      • The Proposed Approach in 2.6 seconds
      • Yuh’s approach in 416.0 seconds
  • Conclusions - I
    • An algorithm for the identification of area constraint for reconfigurable architectures has been introduced
    • Novelties: taking into account
      • Target device heterogeneity
      • Target device reconfiguration capabilities
      • Communication issues
  • Conclusions - II
    • Results have been published
      • A. Montone, M.D. Santambrogio, D. Sciuto, A Design Workflow for the Identification of Area Constraints in Dynamic Reconfigurable Systems , IEEE International Symposium on Electronic Design, Test and Applications (DELTA), 2008
      • A. Montone, M.D. Santambrogio, Area Constraint Evaluation for FPGAs , The Syndicated Q1-2008, A technical newsletter for FPGA, ASIC Verification and DSP Designers, Synplicity Incorporation
  • Future Works
    • Take into consideration IOBs and inter modules communications
    • Partitioning considering clock regions
  • Questions