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3rd 3DDRESD: BiRF 3rd 3DDRESD: BiRF Presentation Transcript

  • 1D and 2D Bitstream Relocation for Partially Dynamically Reconfigurable Architecture BY Marco Novati [email_address] 3-Day DRESD: July 29, 2008
  • Aims
    • Architectural support for relocation:
      • Create an integrated HW/SW system to manage online relocation (1D and 2D) in reconfigurable architecture
      • Create efficient bitstream relocation solutions suitable for the target system:
        • 1D - 2D
        • HW – SW
  • Outline
    • Introduction
    • Relocation
    • State of Art
    • Proposed Solutions
    • Results
    • Concluding Remarks and Future Work
  • What’s Next…
    • Introduction
      • Reconfigurable Architecture
      • Xilinx FPGAs
    • Relocation
    • State of Art
    • Proposed Solutions
    • Results
    • Concluding Remarks and Future Work
  • Reconfigurable architecture
    • A basic reconfigurable architecture consists of:
      • a Static area : a basic Harward architecture
      • a Reconfigurable area : an device area composed by several reconfigurable regions
  • Xilinx FPGAs and Configuration Memory
  • Frame Addressing: Virtex, Virtex-E * Inspired to Virtex Series Configuration Architecture User Guide
  • Frame Addressing: Virtex2pro * Taken from Virtex-II Pro and Virtex-II Pro X FPGA User Guide
  • Frame Addressing: Virtex 4-5 (1/2)
    • New Frame Addressing:
      • Possibility of addressing rows and columns
    * Inspired to Virtex 4 & 5 Configuration Architecture User Guide
  • Frame Addressing: Virtex 4-5 (2/2) * Inspired to Virtex 4 & 5 Configuration Architecture User Guide
  • What’s Next…
    • Introduction
    • Relocation
    • State of Art
    • Proposed Solutions
    • Results
    • Concluding Remarks and Future Work
  • Relocation: Rationale
    • Bitstreams relocation technique to:
      • speedup the overall system execution
      • reduce the amount of memory used to store partial bitstreams
      • assign at runtime the bitstreams placement
  • Relocation: The Problem
  • Relocation: Scenario
  • Relocation: Motivation
  • What’s Next…
    • Introduction
    • Relocation
    • State of Art
      • PARBIT
      • BITPOS
      • BAnMaT
      • REPLICA
    • Proposed Solutions
    • Results
    • Concluding Remarks and Future Work
  • PARBIT
    • [E. Horta and John W. Lockwood, ”PARBIT: A Tool to Transform Bitfiles to Implement Partial Reconfiguration of Field Programmable Gate Arrays (FPGAs)”, Washington University, Technical Report, July 2001.]
    • Features:
      • PureC software
      • Enables the generation of the partial bitstream file
      • Small modifications, altering only the parts related to the location on the device.
    • CONS:
      • Only offline
      • Only 1D reconfiguration
  • BITPOS
    • [Yana E. Krasteva, Eduardo de la Torre, Teresa Riesgo and Didier Joly, ”Virtex II FPGA Bitstream Maniplation: Application to Reconfiguration Control Systems”, 2006 International Conference on Field Programmable Logic and Applications, August 2006.]
    • Features:
      • Extract an area from a configuration file
      • Generate the new relocated bitstream
    • CONS:
      • Only offline
      • Only Virtex II, Virtex II Pro [1D]
  • BAnMaT
    • [D. Deori, ”BAnMaT: un Framework per l’Analisi e la Manipolazione di un Bitstream Orientato alla Riconfigurabilita Parziale”, DEI, Milano, Politecnico di Milano, 2006]
    • Features:
      • Bitstream correctness check
      • Perform modification on a configuration bitstream
      • Permits to bypass synthesis process from the VHDL
    • CONS:
      • Only offline manipulation
  • REPLICA
    • [H. Kalte, G. Lee, M. Porrmann and U. Rckert, ”REPLICA: A Bitstream Manipulation Filter for Module Relocation in Partial Reconfigurable Systems”, The 12th Reconfigurable Architectures Workshop (RAW 2005), 2005.]
    • Features:
      • Hardware filter that exploit relocation
      • Necessary manipulations during the download process
      • Relocation hiding
    • CONS:
      • Only for external reconfigurable system
      • Only 1D relocation
      • Maximum frequency of 50 MHz
  • What’s Next…
    • Introduction
    • Relocation
    • State of Art
    • Polaris
    • Proposed Solutions
      • Polaris
      • Target Architecture
      • Proposed Relocation Solutions
    • Results
    • Concluding Remarks and Future Work
  • Polaris: Motivations
    • Complete workflow to generate a self dynamically reconfigurable architecture that:
      • Supports 1D and 2D reconfiguration
      • Has “good” area constraints for cores
      • Performs Runtime task placement decisions
      • Exploits internal and fast Core relocation
    • Starting from specification of:
      • Target application
      • Target device info
      • Reconfiguration model
      • Communication Infrastructure
  • Polaris Overview
    • Workflow to manage allocation and relocation of tasks in self dynamically reconfigurable architectures
    • Final goal: complete architecture (bitstreams and code) generation
  • Target Architecture: YaRA
  • PPC Based YaRA STATIC AREA
  • Proposed Relocation Solutions
    • Runtime Support for Self Dynamical Runtime 1D and 2D Reconfiguration
      • Xilinx Virtex, Virtex-E, Virtex2pro [1D]
      • Xilinx Virtex-4 and Virtex-5 [2D]
    • Relocation, different solutions:
      • Software:
        • BAnMaT Lite
      • Hardware:
        • BiRF [1D]
        • BiRF Square [2D]
  • Configuration Bitstream
  • BiRF & BiRF Square Block Diagram
  • The Parser
  • CRC Calculation
    • Particular CRC value, used by Xilinx tools
    • Two version of BiRF and BiRF Square:
      • By using the “predefined” values
      • With actual CRC calculation
    • X 16 + X 15 + X 2 + 1 [1D]
    • X 32 + X 28 + X 27 + X 26 + X 25 + X 23 + X 22 + X 20 + X 19 + X 18 + X 14 + X 13 + X 11 + X 10 + X 9 + X 8 + X 6 + 1 [2D]
  • What’s Next…
    • Introduction
    • Relocation
    • State of Art
    • Proposed Solutions
    • Results
      • Synthesis Results
      • Relocation Solutions Results
    • Concluding Remarks and Future Work
  • Synthesis Results: Area FPGA BiRF BiRF Square Family Model Generic Version Optimized Version Generic Version Optimized Version Virtex II Pro vp7 11.6 % 3.6 % − − Virtex II Pro vp20 5.8 % 1.8 % − − Virtex II Pro vp30 4.2 % 1.3 % − − Virtex 4 vlx40 − − 2.2 % 0.9 % Virtex 4 vlx60 − − 1.5 % 0.6 % Virtex 4 vlx100 − − 0.8 % 0.3 % Virtex 5 vlx50 − − 1.1 % 0.8 % Virtex 5 vlx85 − − 0.6 % 0.4 % Virtex 5 vlx110 − − 0.5 % 0.3 %
  • Synthesis Results: Time Performances
    • BiRF:
      • On a Virtex2pro with speed grade -5
        • General purpose version: max frequency of 101 MHz
        • Specific version: max frequency of 136 MHz
    • BiRF Square:
      • On a Virtex-4 with speed grade -12
        • General purpose version: max frequency of 160 MHz
        • Specific version: max frequency of 290 MHz
      • On a Virtex-5 with speed grade -3
        • General purpose version: max frequency of 226 MHz
        • Specific version: max frequency of 304 MHz
  • Relocation Solutions Results (1/2)
    • BiRF, BiRF Square, BAnMaT Lite
      • Permit to support relocation in a self partially and dynamically 1D or 2D reconfigurable system
      • The occupation ratio is relatively small
      • Frequency more than acceptable
      • Reduction of internal memory requirements
    • Throughput:
      • BiRF: 6 MB/s
      • BiRF Square: 7.3 MB/s
      • BAnMaT Lite: 2.6 MB/s
  • Relocation Solutions Results (2/2)
    • A total configuration file size is about 1 MB
    • Considering an architecture:
      • 1/3 of the area as fixed part
      • 2/3 as reconfigurable part with 6 slots
    • With such hypothesis
      • Size of a partial bitstream will be about 110 KB
      • Relocation time of about:
        • 18 ms with BiRF
        • 15 ms with BiRF Square
        • 42 ms with BAnMaT Lite
  • Relocation Time Results (1/4)
  • Relocation Time Results (2/4)
    • FPU1: clock time 0.01 ms, required for 3.65 s (7 add, 3 sub, 10 mul, 1 square root and 4 div)
      • Feasible RR assignment: (0,0) and (6,0)
    • JPEG: a complete JPEG Hardware Compressor, compression rate 24 img(352x288)/s, required for 3 seconds (72 img 352x288)
      • Feasible RR assignment: (0,0), (0,1), (6,0) and (6,1)
    • FPU2: clock time 0.01 ms, required for 3.13 s (6 add, 5 sub, 8 mul and 4 div)
      • Feasible RR assignment: (0,0) and (6,0)
    • 3DES: a Triple-DES 64-bit block cipher, required for 1 second, in order to process a file of 72 MB
      • Feasible RR assignment: (0,0),(1,0), (3,0) and (3,1)
  • Relocation Time Results (3/4)
  • Relocation Time Results (4/4)
  • What’s Next…
    • Introduction
    • Relocation
    • State of Art
    • Proposed Solutions
    • Results
    • Concluding Remarks and Future Work
  • Concluding Remarks
    • Architectural support for relocation:
      • Create an integrated HW/SW system to manage online relocation (1D and 2D) in reconfigurable architecture
      • Create efficient bitstream relocation solutions suitable for the target system:
        • 1D - 2D
        • HW – SW
    • Pubblications:
      • International conferences:
        • M. Morandi, M. Novati, M. D. Santambrogio, D. Sciuto, Core allocation and relocation management for a self dynamically reconfigurable architecture, ISVLSI 2008, IEEE Computer Society Annual Symposium on VLSI
        • S. Corbetta, F. Ferrandi, M. Morandi, M. Novati, M. D. Santambrogio, D. Sciuto, Two Novel Approaches to Online Partial Bitstream Relocation in a Dynamically Reconfigurable System, ISVLSI 2007, IEEE Computer Society Annual Symposium on VLSI
      • IEEE Transaction on VLSI (Second Rewiew Phase):
        • M. Morandi, M. Novati, M.D. Santambrogio, P Spoletini, D. Sciuto, Internal and External Bitstream Relocation for Partial Dynamic Reconfiguration, TSVLSI, IEEE Transactions on Very Large Scale Integration Systems
  • Future Work
    • Validation tool for the chosen
      • Reconfiguration model
      • Communication infrastructure
    • Simulation framework
      • Monitor the reconfigurable system evolution
      • Evaluate different placement policies and area constraints definitions
  • General Information
    • Webpage
      • www.dresd.org/?q=polaris
    • Mailing List
      • [email_address]
    • Contact
      • To have more information regarding polaris:
        • [email_address]
      • For a complete list of information on how to contact us:
        • www.dresd.org/?q=contact_polaris
  • Questions