D ynamic  R econfigurability   in E mbedded  S ystem  D esign - Prima Edizione della 3-Giorni DRESD -  31/07 - 1-2/08, 200...
Outline <ul><li>Something about DRESD </li></ul><ul><ul><li>DRESD philosophy </li></ul></ul><ul><ul><li>DRESD team </li></...
Outline <ul><li>Something about DRESD </li></ul><ul><ul><li>DRESD philosophy </li></ul></ul><ul><ul><li>DRESD team </li></...
DRESD Philosophy <ul><li>Do or do not! There’s no try!   </li></ul><ul><li>Master Yoda </li></ul><ul><li>I need to believe...
DRESD Team <ul><li>People </li></ul><ul><ul><li>30 Undergraduate students </li></ul></ul><ul><ul><li>12 Graduate students ...
Where we are working: Reconfiguration f i x Total Embedded
DRESD in the WORLD <ul><li>Europe </li></ul><ul><ul><li>Paderborn University and HNI </li></ul></ul><ul><li>USA: </li></ul...
Progetti di RLA 03/04 Campione di 30 Studenti
Progetti di RLA 04/05 Campione di 75 Studenti
Progetti di RLA 05/06 Campione di 33 Studenti
Some results:  Conferences <ul><li>Papers: 10 </li></ul><ul><li>Journal: 1 </li></ul><ul><li>Conferences Organization: </l...
Some results:  Partnerships <ul><li>Industries: </li></ul><ul><ul><li>Italian-European: </li></ul></ul><ul><ul><ul><li>Sie...
DRESD and HNI <ul><li>Partitioning and Scheduling </li></ul><ul><li>Static Scheduling for Reconfigurable Architecture </li...
DRESD and UIC <ul><li>Memory </li></ul><ul><li>JHDL </li></ul>
<ul><li>AC2SWA - Adaptive Computing to SW acceleration: </li></ul><ul><li>AC4C - Adaptive Computing for Codesign: </li></u...
Outline <ul><li>Something about DRESD </li></ul><ul><ul><li>DRESD philosophy </li></ul></ul><ul><ul><li>DRESD team </li></...
Caronte <ul><li>Who </li></ul><ul><ul><li>Marco D. Santambrogio </li></ul></ul><ul><ul><li>Donatella Sciuto </li></ul></ul...
DRESD: The Caronte Flow
HW-SSP Sequencing
DRESD: The Caronte Architecture
DRESD and Linux <ul><li>Who </li></ul><ul><ul><li>Alberto Donato </li></ul></ul><ul><ul><li>Vincenzo Frascino </li></ul></...
Software Architecture <ul><li>Composed of two main elements: </li></ul><ul><ul><li>Driver to support partial reconfigurati...
The ICAP Kernel Module <ul><li>Implements a device driver, adds kernel support for the Xilinx ICAP component. </li></ul><u...
The IP-Core Manager <ul><li>A LINUX kernel module which implements a unified infrastructure for the management of the IP-C...
The IP-Core Manager: Hierarchy <ul><li>The IP-Core Manager acts as a  layer  between the operating system kernel and the l...
Caronte: Standalone Vs Linux Table 2 - Original Caronte vs. Caronte with Linux on the XC2VP7 FPGA 4 50 2 50 2 DCM s 44 72 ...
Distributed scenarios
Outline <ul><li>Something about DRESD </li></ul><ul><ul><li>DRESD philosophy </li></ul></ul><ul><ul><li>DRESD team </li></...
SyCERS <ul><li>Who </li></ul><ul><ul><li>Francesco Bruschi </li></ul></ul><ul><ul><li>Carlo Amicucci </li></ul></ul><ul><u...
TLM e SystemC <ul><li>Separare la definizione delle funzionalità del sistema  dalla definizione dei dettagli di comunicazi...
The SyCERS methodology Specification Model Component Assembly Model Bus Functional Model <ul><li>Define the system functio...
A reconfigurable component  using  SystemC <ul><li>It’s not possible to instantiate an sc_module during the simulation pha...
Reconfigurable component behaviour
Caronte Models Control Code (SystemC) Compiler GCC Configurations BlackBox (SystemC) Configuration Control  Process Schedu...
Theoretical Aspects <ul><li>Who </li></ul><ul><ul><li>Gianpaolo Agosta </li></ul></ul><ul><ul><li>Francesco Bruschi </li><...
Reconfigurable Hardware: why?
Reconfigurable Hardware: why?
Partitioning problem
The Acheronte Flow <ul><li>Who </li></ul><ul><ul><li>Elisa Malvicini </li></ul></ul><ul><ul><li>Alessio Montone </li></ul>...
Acheronte: il flusso per la creazione di YaRA .:: Obiettivi .:: Caronte .:: YaRA > Parte fissa > Moduli riconf. > Infrastr...
YaRA <ul><li>Who </li></ul><ul><ul><li>Fabio Cancarè </li></ul></ul><ul><ul><li>Alessio Montone </li></ul></ul><ul><ul><li...
YaRA: the embedded 1D approach
YaRA: parte fissa
YaRA: FPGA Layers Clock Modulo  Riconf. Macro  HW PPC-405 BRAM e Moltiplicatori 18x18 Parte  Fissa .:: Obiettivi .:: Caron...
Caronte Vs YaRA Utilizzo tecnologie standard Intercambiabilità dei moduli Continuazione della comunicazione durante la ric...
How to extend YaRA and Acheronte <ul><li>The “YaRA” side: </li></ul><ul><ul><li>D-ICAP </li></ul></ul><ul><ul><li>D-WBM </...
D-ICAP: DRESD - ICAP <ul><li>Who </li></ul><ul><ul><li>Chiara Sandionigi </li></ul></ul><ul><ul><li>Marco Santambrogio </l...
D-WBM: DRESD - Wishbone BUSMacro <ul><li>Who </li></ul><ul><ul><li>Daniele </li></ul></ul><ul><ul><li>Valentina </li></ul>...
BiRF: Bitstream Relocation Filter <ul><li>Who </li></ul><ul><ul><li>Simone Corbetta </li></ul></ul><ul><ul><li>Massimo Mor...
<ul><li>Who </li></ul><ul><ul><li>Matteo Murgida </li></ul></ul><ul><ul><li>Alessandro Panella </li></ul></ul><ul><ul><li>...
EDK System Creator <ul><li>Who </li></ul><ul><ul><li>Roberto Palazzo </li></ul></ul><ul><ul><li>Marco Santambrogio </li></...
RCPCG: Reconfigurable Core Placer Constraints Generator <ul><li>Who </li></ul><ul><ul><li>Cristiana Bolchini </li></ul></u...
ADG: Automatic Driver Genarator <ul><li>Who </li></ul><ul><ul><li>Maurizio Sala </li></ul></ul><ul><ul><li>Vincenzo Rana <...
BAnMaT:  Bitstream Analizer Manipulator Tool <ul><li>Who </li></ul><ul><ul><li>Simone Corbetta </li></ul></ul><ul><ul><li>...
RecOnDemand <ul><li>Who </li></ul><ul><ul><li>Fabrizio Ferrandi </li></ul></ul><ul><ul><li>Alessandro Mele </li></ul></ul>...
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3DD 1e 31 Luglio Apertura

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3DD 1e 31 Luglio Apertura

  1. 1. D ynamic R econfigurability in E mbedded S ystem D esign - Prima Edizione della 3-Giorni DRESD - 31/07 - 1-2/08, 2006 Hotel Villa Gina Goglio
  2. 2. Outline <ul><li>Something about DRESD </li></ul><ul><ul><li>DRESD philosophy </li></ul></ul><ul><ul><li>DRESD team </li></ul></ul><ul><ul><li>Where we are working </li></ul></ul><ul><ul><li>Some results </li></ul></ul><ul><ul><ul><li>Projects and Thesis </li></ul></ul></ul><ul><ul><ul><li>Conferences </li></ul></ul></ul><ul><ul><ul><li>Partnerships </li></ul></ul></ul><ul><li>DRESD project: the beginning </li></ul><ul><ul><li>Caronte </li></ul></ul><ul><ul><ul><li>Flow </li></ul></ul></ul><ul><ul><ul><li>Architecture </li></ul></ul></ul><ul><ul><li>DRESD and Linux: the software architecture </li></ul></ul><ul><ul><ul><li>ICAP kernel module </li></ul></ul></ul><ul><ul><ul><li>The IP-Core Manager </li></ul></ul></ul><ul><li>DRESD project: what we are doing </li></ul><ul><ul><li>SyCERS </li></ul></ul><ul><ul><li>Some theoretical aspects </li></ul></ul><ul><ul><li>The complete approach </li></ul></ul><ul><ul><ul><li>The Acheronte flow </li></ul></ul></ul><ul><ul><ul><li>YaRA </li></ul></ul></ul><ul><ul><ul><li>How to extend YARA and the Acheronte flow </li></ul></ul></ul>
  3. 3. Outline <ul><li>Something about DRESD </li></ul><ul><ul><li>DRESD philosophy </li></ul></ul><ul><ul><li>DRESD team </li></ul></ul><ul><ul><li>Where we are working </li></ul></ul><ul><ul><li>Some results </li></ul></ul><ul><ul><ul><li>Projects and Thesis </li></ul></ul></ul><ul><ul><ul><li>Conferences </li></ul></ul></ul><ul><ul><ul><li>Partnerships </li></ul></ul></ul><ul><li>DRESD project: the beginning </li></ul><ul><ul><li>Caronte </li></ul></ul><ul><ul><ul><li>Flow </li></ul></ul></ul><ul><ul><ul><li>Architecture </li></ul></ul></ul><ul><ul><li>DRESD and Linux: the software architecture </li></ul></ul><ul><ul><ul><li>ICAP kernel module </li></ul></ul></ul><ul><ul><ul><li>The IP-Core Manager </li></ul></ul></ul><ul><li>DRESD project: what we are doing </li></ul><ul><ul><li>SyCERS </li></ul></ul><ul><ul><li>Some theoretical aspects </li></ul></ul><ul><ul><li>The complete approach </li></ul></ul><ul><ul><ul><li>The Acheronte flow </li></ul></ul></ul><ul><ul><ul><li>YaRA </li></ul></ul></ul><ul><ul><ul><li>How to extend YARA and the Acheronte flow </li></ul></ul></ul>
  4. 4. DRESD Philosophy <ul><li>Do or do not! There’s no try! </li></ul><ul><li>Master Yoda </li></ul><ul><li>I need to believe that something </li></ul><ul><li>extraordinary is possible! </li></ul><ul><li>Alicia Nash </li></ul>
  5. 5. DRESD Team <ul><li>People </li></ul><ul><ul><li>30 Undergraduate students </li></ul></ul><ul><ul><li>12 Graduate students </li></ul></ul><ul><ul><li>2 PhD </li></ul></ul><ul><ul><li>3 Researchers </li></ul></ul><ul><ul><li>4 Professors </li></ul></ul><ul><li>Meeting </li></ul><ul><ul><li>Regular meeting every two weeks </li></ul></ul><ul><ul><li>DRESD Weekend, August </li></ul></ul>
  6. 6. Where we are working: Reconfiguration f i x Total Embedded
  7. 7. DRESD in the WORLD <ul><li>Europe </li></ul><ul><ul><li>Paderborn University and HNI </li></ul></ul><ul><li>USA: </li></ul><ul><ul><li>UIC </li></ul></ul><ul><ul><li>Northwestern </li></ul></ul>
  8. 8. Progetti di RLA 03/04 Campione di 30 Studenti
  9. 9. Progetti di RLA 04/05 Campione di 75 Studenti
  10. 10. Progetti di RLA 05/06 Campione di 33 Studenti
  11. 11. Some results: Conferences <ul><li>Papers: 10 </li></ul><ul><li>Journal: 1 </li></ul><ul><li>Conferences Organization: </li></ul><ul><ul><li>Chair: 1 </li></ul></ul><ul><ul><li>PC: 4 </li></ul></ul><ul><ul><li>Reviewer: 6 + 1 TVLSI </li></ul></ul>
  12. 12. Some results: Partnerships <ul><li>Industries: </li></ul><ul><ul><li>Italian-European: </li></ul></ul><ul><ul><ul><li>Siemens Mobile, Contacts: Ferrara Giovanna </li></ul></ul></ul><ul><ul><ul><li>ATMEL, Contact: Ben Altieri, Piergiovanni Bazzana, Pier Stanislao, Chiara Nencioni </li></ul></ul></ul><ul><ul><ul><li>ST – Microelectronics, Contact: Davide Pandini </li></ul></ul></ul><ul><ul><ul><li>DA Sistemi, Contact: Chiara Coppola, Andrea Zucchetti </li></ul></ul></ul><ul><ul><li>American: </li></ul></ul><ul><ul><ul><li>Xilinx Inc., Contact: Jeff Weintraub, Monica Maccan </li></ul></ul></ul><ul><ul><ul><li>ImpulseC, Contacts: David Buechner, David Pellerin </li></ul></ul></ul><ul><li>Italian Universities: </li></ul><ul><ul><li>Collegio Sant’Anna, Contact: prof. Marco Di Natale </li></ul></ul><ul><ul><li>Università degli studi di Milano, Contacts: prof. Roberto Cordone </li></ul></ul><ul><li>European Universities: </li></ul><ul><ul><li>ALaRI, contacts: prof.ssa Mariagiovanna Sami, prof. Umberto Bondi </li></ul></ul><ul><ul><li>Paderborn e Heinz Nixdoerf Institute, contact: prof. Mario Porman </li></ul></ul><ul><ul><li>Universitaet Karlsruhe, Contact: prof. Juergen Becker </li></ul></ul><ul><li>Noth American Universities: </li></ul><ul><ul><li>UIC, contacts: prof. John Lillis, prof. Florin Balasa, prof. Shantanu Dutt, Lynn Thomas </li></ul></ul><ul><ul><li>Northwestern, contacts: prof. Seda Ogrenci Memik, Pam Mitchell, Rene Hall </li></ul></ul><ul><ul><li>Indiana University Purdue University Indianapolis, Contact: John Lee </li></ul></ul>
  13. 13. DRESD and HNI <ul><li>Partitioning and Scheduling </li></ul><ul><li>Static Scheduling for Reconfigurable Architecture </li></ul><ul><li>Placement and Scheduling </li></ul><ul><li>Linux on Raptor2000 </li></ul><ul><li>Dynamic Driver Generation for Custom IPs </li></ul><ul><li>Distributed reconfigurable scenarios </li></ul><ul><ul><li>Cluster Based and Network Based </li></ul></ul>
  14. 14. DRESD and UIC <ul><li>Memory </li></ul><ul><li>JHDL </li></ul>
  15. 15. <ul><li>AC2SWA - Adaptive Computing to SW acceleration: </li></ul><ul><li>AC4C - Adaptive Computing for Codesign: </li></ul>DRESD and Northwestern
  16. 16. Outline <ul><li>Something about DRESD </li></ul><ul><ul><li>DRESD philosophy </li></ul></ul><ul><ul><li>DRESD team </li></ul></ul><ul><ul><li>Where we are working </li></ul></ul><ul><ul><li>Some results </li></ul></ul><ul><ul><ul><li>Projects and Thesis </li></ul></ul></ul><ul><ul><ul><li>Conferences </li></ul></ul></ul><ul><ul><ul><li>Partnerships </li></ul></ul></ul><ul><li>DRESD project: the beginning </li></ul><ul><ul><li>Caronte </li></ul></ul><ul><ul><ul><li>Flow </li></ul></ul></ul><ul><ul><ul><li>Architecture </li></ul></ul></ul><ul><ul><li>DRESD and Linux: the software architecture </li></ul></ul><ul><ul><ul><li>ICAP kernel module </li></ul></ul></ul><ul><ul><ul><li>The IP-Core Manager </li></ul></ul></ul><ul><li>DRESD project: what we are doing </li></ul><ul><ul><li>SyCERS </li></ul></ul><ul><ul><li>Some theoretical aspects </li></ul></ul><ul><ul><li>The complete approach </li></ul></ul><ul><ul><ul><li>The Acheronte flow </li></ul></ul></ul><ul><ul><ul><li>YaRA </li></ul></ul></ul><ul><ul><ul><li>How to extend YARA and the Acheronte flow </li></ul></ul></ul>
  17. 17. Caronte <ul><li>Who </li></ul><ul><ul><li>Marco D. Santambrogio </li></ul></ul><ul><ul><li>Donatella Sciuto </li></ul></ul><ul><ul><li>Fabrizio Ferrandi </li></ul></ul><ul><li>Objectives </li></ul><ul><ul><li>Propose a novel embedded partial reconfigurable architecture (RSoC) </li></ul></ul><ul><ul><li>Define a complete methodology to port a generic application on the proposed architecture </li></ul></ul>
  18. 18. DRESD: The Caronte Flow
  19. 19. HW-SSP Sequencing
  20. 20. DRESD: The Caronte Architecture
  21. 21. DRESD and Linux <ul><li>Who </li></ul><ul><ul><li>Alberto Donato </li></ul></ul><ul><ul><li>Vincenzo Frascino </li></ul></ul><ul><ul><li>Paolo Martino </li></ul></ul><ul><ul><li>Vincezo Rana </li></ul></ul><ul><ul><li>Marco Santambrogio </li></ul></ul><ul><ul><li>Guido Serra </li></ul></ul><ul><li>Objectives </li></ul><ul><ul><li>Provide software support for dynamic partial reconfiguration on Systems-on-Chip running the LINUX operating system . </li></ul></ul><ul><ul><li>Issues: </li></ul></ul><ul><ul><ul><li>Partial reconfiguration process management from the OS </li></ul></ul></ul><ul><ul><ul><li>Addition and removal of hardware reconfigurable components </li></ul></ul></ul><ul><ul><ul><li>Automatic loading and unloading of specific drivers for the IP-Cores upon components configuration/deconfiguration </li></ul></ul></ul><ul><ul><ul><li>Easier programming interface for specific drivers </li></ul></ul></ul>
  22. 22. Software Architecture <ul><li>Composed of two main elements: </li></ul><ul><ul><li>Driver to support partial reconfiguration </li></ul></ul><ul><ul><li>Manager for the IP-Cores devices </li></ul></ul><ul><li>The software architecture provides: </li></ul><ul><ul><li>Access to ICAP component from userspace </li></ul></ul><ul><ul><li>Interface between IP-Cores low-level drivers and kernel </li></ul></ul><ul><ul><li>Access to reconfigurable devices from userspace processes </li></ul></ul>
  23. 23. The ICAP Kernel Module <ul><li>Implements a device driver, adds kernel support for the Xilinx ICAP component. </li></ul><ul><ul><li>Access from userspace via standard device node mechanism (i.e. /dev/icap) </li></ul></ul><ul><ul><li>Masks hardware details </li></ul></ul><ul><ul><li>Reconfiguration data provided in the form of partial bitstream files </li></ul></ul>
  24. 24. The IP-Core Manager <ul><li>A LINUX kernel module which implements a unified infrastructure for the management of the IP-Cores. </li></ul><ul><ul><li>IP-Cores Plug-and-Play </li></ul></ul><ul><ul><li>Runtime loading of specific IP-Cores drivers </li></ul></ul><ul><ul><li>Management of operations common to all drivers </li></ul></ul><ul><ul><li>Access to reconfigurable components from userspace </li></ul></ul><ul><ul><li>Standardize and simplify </li></ul></ul><ul><ul><li>writing of specific drivers </li></ul></ul>
  25. 25. The IP-Core Manager: Hierarchy <ul><li>The IP-Core Manager acts as a layer between the operating system kernel and the low-level device drivers. </li></ul><ul><li>The low-level drivers contain: </li></ul><ul><ul><li>system calls implementation </li></ul></ul><ul><ul><li>devices initialization and shutdown functions </li></ul></ul><ul><li>The drivers also contain a stub : </li></ul><ul><ul><li>provides standard kernel module interface </li></ul></ul><ul><ul><li>provides module initialization and shutdown functions </li></ul></ul>
  26. 26. Caronte: Standalone Vs Linux Table 2 - Original Caronte vs. Caronte with Linux on the XC2VP7 FPGA 4 50 2 50 2 DCM s 44 72 32 72 32 Block RAM 396 42 168 27 107 Bonded IOBs 4928 45 2262 36 1818 Occupied Slices 9856 22 2173 17 1727 4-input LUTs 9856 24 2369 18 1843 Slice Flip Flops Perc .(%) Elem. Perc .(%) Elem. Total Available Caronte Linux Orignal Caronte Resource
  27. 27. Distributed scenarios
  28. 28. Outline <ul><li>Something about DRESD </li></ul><ul><ul><li>DRESD philosophy </li></ul></ul><ul><ul><li>DRESD team </li></ul></ul><ul><ul><li>Where we are working </li></ul></ul><ul><ul><li>Some results </li></ul></ul><ul><ul><ul><li>Projects and Thesis </li></ul></ul></ul><ul><ul><ul><li>Conferences </li></ul></ul></ul><ul><ul><ul><li>Partnerships </li></ul></ul></ul><ul><li>DRESD project: the beginning </li></ul><ul><ul><li>Caronte </li></ul></ul><ul><ul><ul><li>Flow </li></ul></ul></ul><ul><ul><ul><li>Architecture </li></ul></ul></ul><ul><ul><li>DRESD and Linux: the software architecture </li></ul></ul><ul><ul><ul><li>ICAP kernel module </li></ul></ul></ul><ul><ul><ul><li>The IP-Core Manager </li></ul></ul></ul><ul><li>DRESD project: what we are doing </li></ul><ul><ul><li>SyCERS </li></ul></ul><ul><ul><li>Some theoretical aspects </li></ul></ul><ul><ul><li>The complete approach </li></ul></ul><ul><ul><ul><li>The Acheronte flow </li></ul></ul></ul><ul><ul><ul><li>YaRA </li></ul></ul></ul><ul><ul><ul><li>How to extend YARA and the Acheronte flow </li></ul></ul></ul>
  29. 29. SyCERS <ul><li>Who </li></ul><ul><ul><li>Francesco Bruschi </li></ul></ul><ul><ul><li>Carlo Amicucci </li></ul></ul><ul><ul><li>Fabrizio Ferrandi </li></ul></ul><ul><ul><li>Chiara Sandionigi </li></ul></ul><ul><ul><li>Marco Santambrogio </li></ul></ul><ul><ul><li>Donatella Sciuto </li></ul></ul><ul><ul><li>Stefano Viazzi </li></ul></ul><ul><li>Objectives </li></ul><ul><ul><li>Define a novel model to describe reconfigurable systems </li></ul></ul><ul><ul><ul><li>Based on know HDL (no new languages) </li></ul></ul></ul><ul><ul><ul><li>To be used in the early first stage of the project; to consider the reconfiguration at the system level </li></ul></ul></ul><ul><ul><li>Propose a complete framework for the simulation and the design of reconfigurable systems </li></ul></ul><ul><ul><ul><li>Providing system specification that can be simulated </li></ul></ul></ul><ul><ul><ul><li>Allowing fast parameters setting, e.g. number of reconfigurable blocks, reconfigurable time </li></ul></ul></ul><ul><ul><ul><li>Taking into account the software side of the final system </li></ul></ul></ul>
  30. 30. TLM e SystemC <ul><li>Separare la definizione delle funzionalità del sistema dalla definizione dei dettagli di comunicazione </li></ul><ul><li>Attraverso la definizione di un Canale di comunicazione </li></ul><ul><ul><li>DEF.: un canale implementa una serie di interfacce che sono esposte ai componenti funzionali connessi attraverso di esso. </li></ul></ul><ul><ul><li>DEF.: un’ interfaccia espone i metodi che possono essere invocati dal componente funzionale per comunicare. </li></ul></ul><ul><li>SystemC, dalla versione 2.0, permette di utilizzare la TLM per mezzo dei costrutti: </li></ul>write() read() module A pA->write(v) module B v=pB->read() channel pA pB sc_interface sc_port
  31. 31. The SyCERS methodology Specification Model Component Assembly Model Bus Functional Model <ul><li>Define the system functionality </li></ul><ul><ul><li>No information regarding the final implementation </li></ul></ul><ul><li>Solution space exploration </li></ul><ul><ul><li>Provides the functionalities implementation details </li></ul></ul><ul><ul><li>No information regarding the communication </li></ul></ul><ul><li>Computed solution validation via the simulation </li></ul>
  32. 32. A reconfigurable component using SystemC <ul><li>It’s not possible to instantiate an sc_module during the simulation phase </li></ul><ul><li>It’s possible to modify the SC_THREAD and the SC_METHOD via: </li></ul><ul><ul><li>function pointer </li></ul></ul><ul><ul><li>sc_mutex </li></ul></ul><ul><li>Configuration </li></ul><ul><ul><ul><li>Combined with the reconfiguration time </li></ul></ul></ul><ul><li>Elaboration </li></ul><ul><ul><ul><li>Provided with the elaboration time </li></ul></ul></ul>*g() Reconfigurable Component (sc_module) Configuration (function pointer) mutex
  33. 33. Reconfigurable component behaviour
  34. 34. Caronte Models Control Code (SystemC) Compiler GCC Configurations BlackBox (SystemC) Configuration Control Process Scheduler and Controller Memory Model Cross Compiler GCC Control Code (C/C++) Modello Memoria BlackBoxes Model CoreConnect PowerPC ISS Open SystemC PowerPC core models
  35. 35. Theoretical Aspects <ul><li>Who </li></ul><ul><ul><li>Gianpaolo Agosta </li></ul></ul><ul><ul><li>Francesco Bruschi </li></ul></ul><ul><ul><li>Roberto Cordone </li></ul></ul><ul><ul><li>Fabrizio Ferrandi </li></ul></ul><ul><ul><li>Chiara Fornoni </li></ul></ul><ul><ul><li>Matteo Giani </li></ul></ul><ul><ul><li>Francesco Redaelli </li></ul></ul><ul><ul><li>Massimo Redaelli </li></ul></ul><ul><ul><li>Marco Santambrogio </li></ul></ul><ul><ul><li>Paola Spoletini </li></ul></ul><ul><li>Objectives </li></ul><ul><ul><li>Partitioning </li></ul></ul><ul><ul><li>Scheduling </li></ul></ul><ul><ul><li>HLS Metrics </li></ul></ul><ul><ul><li>Floorplanning </li></ul></ul>
  36. 36. Reconfigurable Hardware: why?
  37. 37. Reconfigurable Hardware: why?
  38. 38. Partitioning problem
  39. 39. The Acheronte Flow <ul><li>Who </li></ul><ul><ul><li>Elisa Malvicini </li></ul></ul><ul><ul><li>Alessio Montone </li></ul></ul><ul><ul><li>Antonio Piazzi </li></ul></ul><ul><ul><li>Marco Santambrogio </li></ul></ul><ul><li>Objectives </li></ul><ul><ul><li>Extend the Caronte flow to support different FPGAs </li></ul></ul><ul><ul><li>Define a complete automated version of the Flow </li></ul></ul><ul><ul><li>Extend the Caronte flow to support different architectural solution, e.g YARA, Raptor2000 </li></ul></ul>
  40. 40. Acheronte: il flusso per la creazione di YaRA .:: Obiettivi .:: Caronte .:: YaRA > Parte fissa > Moduli riconf. > Infrastruttura di comunicaz. .:: Acheronte .:: Test .:: Conclusioni .:: Sviluppi futuri .::Domande
  41. 41. YaRA <ul><li>Who </li></ul><ul><ul><li>Fabio Cancarè </li></ul></ul><ul><ul><li>Alessio Montone </li></ul></ul><ul><ul><li>Antonio Piazzi </li></ul></ul><ul><ul><li>Marco Santambrogio </li></ul></ul><ul><li>Objectives </li></ul><ul><ul><li>Extend the Caronte architecture to support the linear placement solution </li></ul></ul><ul><ul><li>Solve the communication constraints of the previous architecture </li></ul></ul><ul><ul><li>Present an architecture that can be easily portend on different board, e.g Raptor2000 </li></ul></ul>
  42. 42. YaRA: the embedded 1D approach
  43. 43. YaRA: parte fissa
  44. 44. YaRA: FPGA Layers Clock Modulo Riconf. Macro HW PPC-405 BRAM e Moltiplicatori 18x18 Parte Fissa .:: Obiettivi .:: Caronte .:: YaRA > Parte fissa > Moduli riconf. > Infrastruttura di comunicaz. .:: Acheronte .:: Test .:: Conclusioni .:: Sviluppi futuri .::Domande CLB x CLB y Layer
  45. 45. Caronte Vs YaRA Utilizzo tecnologie standard Intercambiabilità dei moduli Continuazione della comunicazione durante la riconfigurazione N° di moduli Riconfigurabilità Interna Riconfigurabilità Parziale e Dinamica Anche diverse decine  2 YaRA Caronte
  46. 46. How to extend YaRA and Acheronte <ul><li>The “YaRA” side: </li></ul><ul><ul><li>D-ICAP </li></ul></ul><ul><ul><li>D-WBM </li></ul></ul><ul><ul><li>BiRF </li></ul></ul><ul><ul><li>IP-Core Generator Tool </li></ul></ul><ul><ul><li>EDK System Creator </li></ul></ul><ul><li>The “Acheronte” side: </li></ul><ul><ul><li>RCPCG </li></ul></ul><ul><ul><li>ADG </li></ul></ul><ul><ul><li>BAnMaT </li></ul></ul><ul><ul><li>RecOnDemand </li></ul></ul>
  47. 47. D-ICAP: DRESD - ICAP <ul><li>Who </li></ul><ul><ul><li>Chiara Sandionigi </li></ul></ul><ul><ul><li>Marco Santambrogio </li></ul></ul><ul><ul><li>Riccardo Somaglia </li></ul></ul><ul><ul><li>Paolo Tornese </li></ul></ul><ul><li>Objectives </li></ul><ul><ul><li>Define the DRESD – ICAP core, characterized by: </li></ul></ul><ul><ul><ul><li>Support DMA communication </li></ul></ul></ul><ul><ul><ul><li>HW-IPCM integration </li></ul></ul></ul>
  48. 48. D-WBM: DRESD - Wishbone BUSMacro <ul><li>Who </li></ul><ul><ul><li>Daniele </li></ul></ul><ul><ul><li>Valentina </li></ul></ul><ul><ul><li>Fabio Cancarè </li></ul></ul><ul><ul><li>Marco Santambrogio </li></ul></ul><ul><li>Objectives </li></ul><ul><ul><li>Create the communication infrastructure for a given instance of the YARA architecture </li></ul></ul><ul><ul><li>Automatic XDL description manipulation to define the correct MacroHW for the bus infrastructure </li></ul></ul>
  49. 49. BiRF: Bitstream Relocation Filter <ul><li>Who </li></ul><ul><ul><li>Simone Corbetta </li></ul></ul><ul><ul><li>Massimo Morandi </li></ul></ul><ul><ul><li>Marco Novati </li></ul></ul><ul><ul><li>Marco Santambrogio </li></ul></ul><ul><li>Objectives </li></ul><ul><ul><li>Automatic replacement of a reconfiguration bitstream </li></ul></ul><ul><ul><li>HW implementation of such a filter to speed-up its execution </li></ul></ul>
  50. 50. <ul><li>Who </li></ul><ul><ul><li>Matteo Murgida </li></ul></ul><ul><ul><li>Alessandro Panella </li></ul></ul><ul><ul><li>Vincenzo Rana </li></ul></ul><ul><ul><li>Marco Santambrogio </li></ul></ul><ul><ul><li>Donatella Sciuto </li></ul></ul><ul><li>Objectives </li></ul><ul><ul><li>Create an EDK compatible IPCore given the VHDL description of the core </li></ul></ul><ul><ul><li>Support the PLB, OPB and the Wishbone BUS infrastructure </li></ul></ul><ul><ul><li>Fully support the YARA architecture </li></ul></ul>IP-Core Generator Tool
  51. 51. EDK System Creator <ul><li>Who </li></ul><ul><ul><li>Roberto Palazzo </li></ul></ul><ul><ul><li>Marco Santambrogio </li></ul></ul><ul><li>Objectives </li></ul><ul><ul><li>Given a known EDK system architecture and a generic IPCore description </li></ul></ul><ul><ul><ul><li>Automatic binding of the two inputs into a downloadable and executable bitstream </li></ul></ul></ul><ul><ul><li>Fully support the YARA architecture </li></ul></ul>
  52. 52. RCPCG: Reconfigurable Core Placer Constraints Generator <ul><li>Who </li></ul><ul><ul><li>Cristiana Bolchini </li></ul></ul><ul><ul><li>Stefano </li></ul></ul><ul><ul><li>Gilulia </li></ul></ul><ul><ul><li>Marco Santambrogio </li></ul></ul><ul><li>Objectives </li></ul><ul><ul><li>Assign the placement constraints for a reconfigurable core to be used with the YARA architecture </li></ul></ul><ul><ul><li>Find the best floorplanning constraints according with different optimization function, e.g. #AssignedCLBs/#UsedCLBs </li></ul></ul>
  53. 53. ADG: Automatic Driver Genarator <ul><li>Who </li></ul><ul><ul><li>Maurizio Sala </li></ul></ul><ul><ul><li>Vincenzo Rana </li></ul></ul><ul><ul><li>Marco Santambrogio </li></ul></ul><ul><ul><li>Nicolas Tagliani </li></ul></ul><ul><li>Objectives </li></ul><ul><ul><li>Complete the IP-Core Generator tool work with the creation of the correct driver for a given IP-Core </li></ul></ul><ul><ul><li>Create the basic infrastructure for both the standalone and the OS version of the driver </li></ul></ul>
  54. 54. BAnMaT: Bitstream Analizer Manipulator Tool <ul><li>Who </li></ul><ul><ul><li>Simone Corbetta </li></ul></ul><ul><ul><li>Marco Santambrogio </li></ul></ul><ul><li>Objectives </li></ul><ul><ul><li>Bitstream analyzer </li></ul></ul><ul><ul><li>Easy API to manage the bistream file </li></ul></ul><ul><ul><li>Difference bitstream file checker </li></ul></ul><ul><ul><li>Reconfiguration bitstream debugger </li></ul></ul>
  55. 55. RecOnDemand <ul><li>Who </li></ul><ul><ul><li>Fabrizio Ferrandi </li></ul></ul><ul><ul><li>Alessandro Mele </li></ul></ul><ul><ul><li>Vincenzo Rana </li></ul></ul><ul><ul><li>Marco Santambrogio </li></ul></ul><ul><li>Objectives </li></ul><ul><ul><li>Client-Server application for remote FPGA control: </li></ul></ul><ul><ul><li>Serial Mode: </li></ul></ul><ul><ul><ul><li>It downloads a bitstream, the client, that can dialogue with a second entity, the server, to request partial or complete reconfiguration </li></ul></ul></ul><ul><ul><li>Download Mode: </li></ul></ul><ul><ul><ul><li>It allows the download of a sequence of bitstreams for a fixed number of time </li></ul></ul></ul>
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