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3DD 1e 31 Luglio Apertura

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  • 1. D ynamic R econfigurability in E mbedded S ystem D esign - Prima Edizione della 3-Giorni DRESD - 31/07 - 1-2/08, 2006 Hotel Villa Gina Goglio
  • 2. Outline
    • Something about DRESD
      • DRESD philosophy
      • DRESD team
      • Where we are working
      • Some results
        • Projects and Thesis
        • Conferences
        • Partnerships
    • DRESD project: the beginning
      • Caronte
        • Flow
        • Architecture
      • DRESD and Linux: the software architecture
        • ICAP kernel module
        • The IP-Core Manager
    • DRESD project: what we are doing
      • SyCERS
      • Some theoretical aspects
      • The complete approach
        • The Acheronte flow
        • YaRA
        • How to extend YARA and the Acheronte flow
  • 3. Outline
    • Something about DRESD
      • DRESD philosophy
      • DRESD team
      • Where we are working
      • Some results
        • Projects and Thesis
        • Conferences
        • Partnerships
    • DRESD project: the beginning
      • Caronte
        • Flow
        • Architecture
      • DRESD and Linux: the software architecture
        • ICAP kernel module
        • The IP-Core Manager
    • DRESD project: what we are doing
      • SyCERS
      • Some theoretical aspects
      • The complete approach
        • The Acheronte flow
        • YaRA
        • How to extend YARA and the Acheronte flow
  • 4. DRESD Philosophy
    • Do or do not! There’s no try!
    • Master Yoda
    • I need to believe that something
    • extraordinary is possible!
    • Alicia Nash
  • 5. DRESD Team
    • People
      • 30 Undergraduate students
      • 12 Graduate students
      • 2 PhD
      • 3 Researchers
      • 4 Professors
    • Meeting
      • Regular meeting every two weeks
      • DRESD Weekend, August
  • 6. Where we are working: Reconfiguration f i x Total Embedded
  • 7. DRESD in the WORLD
    • Europe
      • Paderborn University and HNI
    • USA:
      • UIC
      • Northwestern
  • 8. Progetti di RLA 03/04 Campione di 30 Studenti
  • 9. Progetti di RLA 04/05 Campione di 75 Studenti
  • 10. Progetti di RLA 05/06 Campione di 33 Studenti
  • 11. Some results: Conferences
    • Papers: 10
    • Journal: 1
    • Conferences Organization:
      • Chair: 1
      • PC: 4
      • Reviewer: 6 + 1 TVLSI
  • 12. Some results: Partnerships
    • Industries:
      • Italian-European:
        • Siemens Mobile, Contacts: Ferrara Giovanna
        • ATMEL, Contact: Ben Altieri, Piergiovanni Bazzana, Pier Stanislao, Chiara Nencioni
        • ST – Microelectronics, Contact: Davide Pandini
        • DA Sistemi, Contact: Chiara Coppola, Andrea Zucchetti
      • American:
        • Xilinx Inc., Contact: Jeff Weintraub, Monica Maccan
        • ImpulseC, Contacts: David Buechner, David Pellerin
    • Italian Universities:
      • Collegio Sant’Anna, Contact: prof. Marco Di Natale
      • Università degli studi di Milano, Contacts: prof. Roberto Cordone
    • European Universities:
      • ALaRI, contacts: prof.ssa Mariagiovanna Sami, prof. Umberto Bondi
      • Paderborn e Heinz Nixdoerf Institute, contact: prof. Mario Porman
      • Universitaet Karlsruhe, Contact: prof. Juergen Becker
    • Noth American Universities:
      • UIC, contacts: prof. John Lillis, prof. Florin Balasa, prof. Shantanu Dutt, Lynn Thomas
      • Northwestern, contacts: prof. Seda Ogrenci Memik, Pam Mitchell, Rene Hall
      • Indiana University Purdue University Indianapolis, Contact: John Lee
  • 13. DRESD and HNI
    • Partitioning and Scheduling
    • Static Scheduling for Reconfigurable Architecture
    • Placement and Scheduling
    • Linux on Raptor2000
    • Dynamic Driver Generation for Custom IPs
    • Distributed reconfigurable scenarios
      • Cluster Based and Network Based
  • 14. DRESD and UIC
    • Memory
    • JHDL
  • 15.
    • AC2SWA - Adaptive Computing to SW acceleration:
    • AC4C - Adaptive Computing for Codesign:
    DRESD and Northwestern
  • 16. Outline
    • Something about DRESD
      • DRESD philosophy
      • DRESD team
      • Where we are working
      • Some results
        • Projects and Thesis
        • Conferences
        • Partnerships
    • DRESD project: the beginning
      • Caronte
        • Flow
        • Architecture
      • DRESD and Linux: the software architecture
        • ICAP kernel module
        • The IP-Core Manager
    • DRESD project: what we are doing
      • SyCERS
      • Some theoretical aspects
      • The complete approach
        • The Acheronte flow
        • YaRA
        • How to extend YARA and the Acheronte flow
  • 17. Caronte
    • Who
      • Marco D. Santambrogio
      • Donatella Sciuto
      • Fabrizio Ferrandi
    • Objectives
      • Propose a novel embedded partial reconfigurable architecture (RSoC)
      • Define a complete methodology to port a generic application on the proposed architecture
  • 18. DRESD: The Caronte Flow
  • 19. HW-SSP Sequencing
  • 20. DRESD: The Caronte Architecture
  • 21. DRESD and Linux
    • Who
      • Alberto Donato
      • Vincenzo Frascino
      • Paolo Martino
      • Vincezo Rana
      • Marco Santambrogio
      • Guido Serra
    • Objectives
      • Provide software support for dynamic partial reconfiguration on Systems-on-Chip running the LINUX operating system .
      • Issues:
        • Partial reconfiguration process management from the OS
        • Addition and removal of hardware reconfigurable components
        • Automatic loading and unloading of specific drivers for the IP-Cores upon components configuration/deconfiguration
        • Easier programming interface for specific drivers
  • 22. Software Architecture
    • Composed of two main elements:
      • Driver to support partial reconfiguration
      • Manager for the IP-Cores devices
    • The software architecture provides:
      • Access to ICAP component from userspace
      • Interface between IP-Cores low-level drivers and kernel
      • Access to reconfigurable devices from userspace processes
  • 23. The ICAP Kernel Module
    • Implements a device driver, adds kernel support for the Xilinx ICAP component.
      • Access from userspace via standard device node mechanism (i.e. /dev/icap)
      • Masks hardware details
      • Reconfiguration data provided in the form of partial bitstream files
  • 24. The IP-Core Manager
    • A LINUX kernel module which implements a unified infrastructure for the management of the IP-Cores.
      • IP-Cores Plug-and-Play
      • Runtime loading of specific IP-Cores drivers
      • Management of operations common to all drivers
      • Access to reconfigurable components from userspace
      • Standardize and simplify
      • writing of specific drivers
  • 25. The IP-Core Manager: Hierarchy
    • The IP-Core Manager acts as a layer between the operating system kernel and the low-level device drivers.
    • The low-level drivers contain:
      • system calls implementation
      • devices initialization and shutdown functions
    • The drivers also contain a stub :
      • provides standard kernel module interface
      • provides module initialization and shutdown functions
  • 26. Caronte: Standalone Vs Linux Table 2 - Original Caronte vs. Caronte with Linux on the XC2VP7 FPGA 4 50 2 50 2 DCM s 44 72 32 72 32 Block RAM 396 42 168 27 107 Bonded IOBs 4928 45 2262 36 1818 Occupied Slices 9856 22 2173 17 1727 4-input LUTs 9856 24 2369 18 1843 Slice Flip Flops Perc .(%) Elem. Perc .(%) Elem. Total Available Caronte Linux Orignal Caronte Resource
  • 27. Distributed scenarios
  • 28. Outline
    • Something about DRESD
      • DRESD philosophy
      • DRESD team
      • Where we are working
      • Some results
        • Projects and Thesis
        • Conferences
        • Partnerships
    • DRESD project: the beginning
      • Caronte
        • Flow
        • Architecture
      • DRESD and Linux: the software architecture
        • ICAP kernel module
        • The IP-Core Manager
    • DRESD project: what we are doing
      • SyCERS
      • Some theoretical aspects
      • The complete approach
        • The Acheronte flow
        • YaRA
        • How to extend YARA and the Acheronte flow
  • 29. SyCERS
    • Who
      • Francesco Bruschi
      • Carlo Amicucci
      • Fabrizio Ferrandi
      • Chiara Sandionigi
      • Marco Santambrogio
      • Donatella Sciuto
      • Stefano Viazzi
    • Objectives
      • Define a novel model to describe reconfigurable systems
        • Based on know HDL (no new languages)
        • To be used in the early first stage of the project; to consider the reconfiguration at the system level
      • Propose a complete framework for the simulation and the design of reconfigurable systems
        • Providing system specification that can be simulated
        • Allowing fast parameters setting, e.g. number of reconfigurable blocks, reconfigurable time
        • Taking into account the software side of the final system
  • 30. TLM e SystemC
    • Separare la definizione delle funzionalità del sistema dalla definizione dei dettagli di comunicazione
    • Attraverso la definizione di un Canale di comunicazione
      • DEF.: un canale implementa una serie di interfacce che sono esposte ai componenti funzionali connessi attraverso di esso.
      • DEF.: un’ interfaccia espone i metodi che possono essere invocati dal componente funzionale per comunicare.
    • SystemC, dalla versione 2.0, permette di utilizzare la TLM per mezzo dei costrutti:
    write() read() module A pA->write(v) module B v=pB->read() channel pA pB sc_interface sc_port
  • 31. The SyCERS methodology Specification Model Component Assembly Model Bus Functional Model
    • Define the system functionality
      • No information regarding the final implementation
    • Solution space exploration
      • Provides the functionalities implementation details
      • No information regarding the communication
    • Computed solution validation via the simulation
  • 32. A reconfigurable component using SystemC
    • It’s not possible to instantiate an sc_module during the simulation phase
    • It’s possible to modify the SC_THREAD and the SC_METHOD via:
      • function pointer
      • sc_mutex
    • Configuration
        • Combined with the reconfiguration time
    • Elaboration
        • Provided with the elaboration time
    *g() Reconfigurable Component (sc_module) Configuration (function pointer) mutex
  • 33. Reconfigurable component behaviour
  • 34. Caronte Models Control Code (SystemC) Compiler GCC Configurations BlackBox (SystemC) Configuration Control Process Scheduler and Controller Memory Model Cross Compiler GCC Control Code (C/C++) Modello Memoria BlackBoxes Model CoreConnect PowerPC ISS Open SystemC PowerPC core models
  • 35. Theoretical Aspects
    • Who
      • Gianpaolo Agosta
      • Francesco Bruschi
      • Roberto Cordone
      • Fabrizio Ferrandi
      • Chiara Fornoni
      • Matteo Giani
      • Francesco Redaelli
      • Massimo Redaelli
      • Marco Santambrogio
      • Paola Spoletini
    • Objectives
      • Partitioning
      • Scheduling
      • HLS Metrics
      • Floorplanning
  • 36. Reconfigurable Hardware: why?
  • 37. Reconfigurable Hardware: why?
  • 38. Partitioning problem
  • 39. The Acheronte Flow
    • Who
      • Elisa Malvicini
      • Alessio Montone
      • Antonio Piazzi
      • Marco Santambrogio
    • Objectives
      • Extend the Caronte flow to support different FPGAs
      • Define a complete automated version of the Flow
      • Extend the Caronte flow to support different architectural solution, e.g YARA, Raptor2000
  • 40. Acheronte: il flusso per la creazione di YaRA .:: Obiettivi .:: Caronte .:: YaRA > Parte fissa > Moduli riconf. > Infrastruttura di comunicaz. .:: Acheronte .:: Test .:: Conclusioni .:: Sviluppi futuri .::Domande
  • 41. YaRA
    • Who
      • Fabio Cancarè
      • Alessio Montone
      • Antonio Piazzi
      • Marco Santambrogio
    • Objectives
      • Extend the Caronte architecture to support the linear placement solution
      • Solve the communication constraints of the previous architecture
      • Present an architecture that can be easily portend on different board, e.g Raptor2000
  • 42. YaRA: the embedded 1D approach
  • 43. YaRA: parte fissa
  • 44. YaRA: FPGA Layers Clock Modulo Riconf. Macro HW PPC-405 BRAM e Moltiplicatori 18x18 Parte Fissa .:: Obiettivi .:: Caronte .:: YaRA > Parte fissa > Moduli riconf. > Infrastruttura di comunicaz. .:: Acheronte .:: Test .:: Conclusioni .:: Sviluppi futuri .::Domande CLB x CLB y Layer
  • 45. Caronte Vs YaRA Utilizzo tecnologie standard Intercambiabilità dei moduli Continuazione della comunicazione durante la riconfigurazione N° di moduli Riconfigurabilità Interna Riconfigurabilità Parziale e Dinamica Anche diverse decine  2 YaRA Caronte
  • 46. How to extend YaRA and Acheronte
    • The “YaRA” side:
      • D-ICAP
      • D-WBM
      • BiRF
      • IP-Core Generator Tool
      • EDK System Creator
    • The “Acheronte” side:
      • RCPCG
      • ADG
      • BAnMaT
      • RecOnDemand
  • 47. D-ICAP: DRESD - ICAP
    • Who
      • Chiara Sandionigi
      • Marco Santambrogio
      • Riccardo Somaglia
      • Paolo Tornese
    • Objectives
      • Define the DRESD – ICAP core, characterized by:
        • Support DMA communication
        • HW-IPCM integration
  • 48. D-WBM: DRESD - Wishbone BUSMacro
    • Who
      • Daniele
      • Valentina
      • Fabio Cancarè
      • Marco Santambrogio
    • Objectives
      • Create the communication infrastructure for a given instance of the YARA architecture
      • Automatic XDL description manipulation to define the correct MacroHW for the bus infrastructure
  • 49. BiRF: Bitstream Relocation Filter
    • Who
      • Simone Corbetta
      • Massimo Morandi
      • Marco Novati
      • Marco Santambrogio
    • Objectives
      • Automatic replacement of a reconfiguration bitstream
      • HW implementation of such a filter to speed-up its execution
  • 50.
    • Who
      • Matteo Murgida
      • Alessandro Panella
      • Vincenzo Rana
      • Marco Santambrogio
      • Donatella Sciuto
    • Objectives
      • Create an EDK compatible IPCore given the VHDL description of the core
      • Support the PLB, OPB and the Wishbone BUS infrastructure
      • Fully support the YARA architecture
    IP-Core Generator Tool
  • 51. EDK System Creator
    • Who
      • Roberto Palazzo
      • Marco Santambrogio
    • Objectives
      • Given a known EDK system architecture and a generic IPCore description
        • Automatic binding of the two inputs into a downloadable and executable bitstream
      • Fully support the YARA architecture
  • 52. RCPCG: Reconfigurable Core Placer Constraints Generator
    • Who
      • Cristiana Bolchini
      • Stefano
      • Gilulia
      • Marco Santambrogio
    • Objectives
      • Assign the placement constraints for a reconfigurable core to be used with the YARA architecture
      • Find the best floorplanning constraints according with different optimization function, e.g. #AssignedCLBs/#UsedCLBs
  • 53. ADG: Automatic Driver Genarator
    • Who
      • Maurizio Sala
      • Vincenzo Rana
      • Marco Santambrogio
      • Nicolas Tagliani
    • Objectives
      • Complete the IP-Core Generator tool work with the creation of the correct driver for a given IP-Core
      • Create the basic infrastructure for both the standalone and the OS version of the driver
  • 54. BAnMaT: Bitstream Analizer Manipulator Tool
    • Who
      • Simone Corbetta
      • Marco Santambrogio
    • Objectives
      • Bitstream analyzer
      • Easy API to manage the bistream file
      • Difference bitstream file checker
      • Reconfiguration bitstream debugger
  • 55. RecOnDemand
    • Who
      • Fabrizio Ferrandi
      • Alessandro Mele
      • Vincenzo Rana
      • Marco Santambrogio
    • Objectives
      • Client-Server application for remote FPGA control:
      • Serial Mode:
        • It downloads a bitstream, the client, that can dialogue with a second entity, the server, to request partial or complete reconfiguration
      • Download Mode:
        • It allows the download of a sequence of bitstreams for a fixed number of time