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3D-DRESD Polaris
3D-DRESD Polaris
3D-DRESD Polaris
3D-DRESD Polaris
3D-DRESD Polaris
3D-DRESD Polaris
3D-DRESD Polaris
3D-DRESD Polaris
3D-DRESD Polaris
3D-DRESD Polaris
3D-DRESD Polaris
3D-DRESD Polaris
3D-DRESD Polaris
3D-DRESD Polaris
3D-DRESD Polaris
3D-DRESD Polaris
3D-DRESD Polaris
3D-DRESD Polaris
3D-DRESD Polaris
3D-DRESD Polaris
3D-DRESD Polaris
3D-DRESD Polaris
3D-DRESD Polaris
3D-DRESD Polaris
3D-DRESD Polaris
3D-DRESD Polaris
3D-DRESD Polaris
3D-DRESD Polaris
3D-DRESD Polaris
3D-DRESD Polaris
3D-DRESD Polaris
3D-DRESD Polaris
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3D-DRESD Polaris


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  • 1. Polaris
  • 2.
    • A workflow to manage allocation and relocation of tasks in a reconfigurable architecture
    • Final goal: complete architecture (bitstreams) generation
  • 3. Management of 2D Reconfiguration in a Reconfigurable System Massimo Morandi [email_address]
  • 4. Outline
    • Introduction
      • Problem description
      • Project Goals and Contributions
    • Project in details
      • Phases
      • Results
    • Future Work
  • 5. Problem Description
    • New Generation of FPGAs
      • Virtex-4 and Virtex-5
      • Allow bi-dimensional reconfiguration
    • This permits to:
      • Better exploit reconfigurable area
      • Obtain modules performance optimizations
    • More complex management:
      • Handle one more degree of freedom
      • Avoid more fragmentation
      • Perform good placement choices to keep low TRR
      • Keep acceptable intra-module routing paths
  • 6. Project Goals and Contributions
    • Analyze effects of 2D reconfiguration
      • New advantages
      • New problems
    • Examine possible solutions to new problems
      • Explore literature to find promising ideas
      • Evaluate those solutions in various scenarios
    • Propose a new solution
      • Combining ideas from literature with new ones
      • Obtaining good cost-quality tradeoff
  • 7. Setting and Advantages Definition
    • Definition of the setting:
      • 2D self partial dynamical run-time reconfiguration
    • Analysis of the advantages of 2D Reconfiguration
      • In area usage and performance
  • 8. 2D Fragmentation Problem
    • Analysis of the 2D-fragmentation problem
      • Area generally more fragmented
      • Can nullify the area optimizations obtained
  • 9. Placement Decisions
    • Analysis of 2D placement choices effects:
      • Again, bad choices can lead to performance loss
  • 10. Allocation manager
    • Definition of allocation manager desired features:
      • Low TRR
      • Low management overhead
      • High routing efficiency
      • Low fragmentation
    • Definition of allocation manager structure:
      • Empty space manager
        • Complete space
        • Heuristic selection
      • Fitter
        • General (FF,BL,BF,WF…)
        • Focused (FA,RA… )
  • 11. Most relevant works
    • Maintain complete information on empty space:
      • KAMER:
        • Keep All Maximally Empty Rectangles
        • Apply a general fitting strategy
      • CUR:
        • Maintain the Countour of a Union of Rectangles
        • Apply a focused fitting strategy
    • Heuristically prune part of the information:
      • KNER:
        • Keep Non-overlapping Empty Rectangles
        • Apply a general fitting strategy
      • 2D-HASHING:
        • Keep Non-ov. Empty Rectangles in optimized data structure
        • Apply (exclusively) a general fitting strategy
  • 12. Evaluation and Proposed Approach
    • Proposed Approach
      • Heuristic (KNER-like) empty space manager, to keep low complexity for use in a self-reconfigurable system
      • Fitting strategy focused on minimizing routing paths, to maintain high performance of the reconfigurable system (chosen metric to minimize Manhattan distance)
    • High placement quality => high complexity
    • Lowest compl. => no focused fitting (bad especially for routing)
  • 13. Structure of the allocation manager
    • Task, defined by:
      • Arrival time, ASAP, (ALAP), H, W, Latency, Communicating Tasks
      • Hosted in a queue which also adds a pointer to the rectangle where it is placed
    • Reconfigurable Device, represented as:
      • Binary Tree structure, each node is a Rectangle, each leaf is an empty Rectangle.
      • Navigation trough pointers to left child, right child, next leaf and a function to find previous leaf (for bookkeeping after split or merge)
    • Rectangle, defined by:
      • X, Y, H, W
      • Initially one, (X,Y)=(0,0), H=FPGA Rows, W=FPGA Cols
  • 14. The Placement Algorithm
  • 15. Experimental Results
    • Benchmark of 100 randomly generated tasks:
      • Size (5% to 25% of FPGA), randomly interconnected
    • Execution time: 3x less than CUR, close to KNER
    • Communication cost: 3x less than KNER, close to CUR
    • Task Rejection Rate: all solutions quite close
  • 16. Future Work
    • Apply the proposed solution to self reconfiguration:
      • Adapt the algorithm to run on the internal processor
      • Create a validation reconfigurable architecture
      • Integrate the architecture with relocation
    • Tune the algorithm to improve results:
      • Experiment techniques to reduce TRR
      • Try to optimize the code to have an algorithm with lower running time
    • Evaluate other fitting strategies
  • 17. Questions?
  • 18. Relocation for 2D Reconfigurable Systems Marco Novati [email_address]
  • 19. Project Outline
    • Introduction
      • Problem description
      • Project Goals
    • Project in details
      • Phases
      • Results
    • What’s next
  • 20. Problem Description
    • Self Dynamical Runtime 2D Reconfiguration
      • Xilinx Virtex-4 and Virtex-5
    • Relocation, different solutions
      • Software
      • Hardware
    • We chose an hardware solution
      • BiRF Square
  • 21. Project Goals
    • Study of the new FPGA Families
      • Examination of Xilinx documentation on V4 and V5
    • Analysis of the new bitstream structure
      • Generation of V4 and V5 bitstream
    • Development of the new version of BiRF
      • Implementation
      • Validation
  • 22.
    • New Frame Addressing:
      • Possibility of addressing rows and columns
    Frame Addressing (1/2)
  • 23. Frame Addressing (2/2)
  • 24. New Parser
  • 25. CRC Calculation
    • Particular CRC value, used by Xilinx tools
    • Two version of BiRF Square:
      • By using the “predefined” value
      • With actual CRC calculation
    • An optimized algorithm has been used
  • 26. Synthesis results
    • On a Virtex-4 with speed grade -12
      • General purpose version: max frequency of 160 MHz
      • Specific version: max frequency of 290 Mhz
  • 27. Target Device
  • 28. Validation Architecture
  • 29. Results (1/2)
    • BiRF Square
      • Permits apply relocation in a self partially and dynamically 2D-reconfigurable system
      • The occupation ratio is relatively small
      • Frequency more than acceptable
      • Reduction of internal memory requirements
  • 30. Results (2/2)
    • Throughput of 7,3 MB/s:
      • A total configuration file size is about 1 MB
      • Considering an architecture:
        • 1/3 of the area as fixed part
        • 2/3 as reconfigurable part with 6 slots
      • With such hypothesis
        • Size of a partial bitstream will be about 110 KB
        • Relocation time of about 15 ms
  • 31. What’s Next
    • Future improvements:
      • Direct access to the memory (DMA)
        • Direct manipulation of the bitstream
        • Portability
      • Integration with ICAP
        • Elimination of the relocation overhead
        • Relocation time << reconfiguration time
    • Future work:
      • Provide a simulation framework to monitor the reconfigurable system evolution and to evaluate different choices
    • The final goal:
      • Creation of a real architecture that exploits self partial and dynamical 2D-reconfiguration,with relocation
  • 32. Questions