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  • Comparison of 1-phase cascaded & MLDCLI with PWM contol methods Sri sai institute of technology & science 1 OBJECTIVE: Multilevel inverter offers several advantages compare to the conventional bridge inverter in terms lower dv/dt stresses better fundamental output voltages and THD features. This project presents comparison of cascaded H-Bridge and multilevel dc link inverter (MLDCLI) using only a dc power sources. A MLDCLI can be constructed by the series connection half and full bridge cells each having its own dc source. A multi level voltage source inverter can be formed by connecting an MLDCL with a single bridge inverter. The MLDCLI provides a dc voltage with the shape of staircase with or without pulse width modulation (PWM) to the bridge inverter, which in turn alternates the polarity to produce an ac voltage. Compared with cascaded H-Bridge multilevel inverter, the MLDCLI can significantly reduce the switch count as the number of voltage levels increased beyond five for a given number of voltage levels, m, the required number of active switches is 2(m-1) for the existing multilevel inverter but is m+3 for the MLDCLI inverters. This project presents the performance of a seven level MLDCLI based on sine and space vector PWM control technique. Performance analysis is made based on the results of simulation study conducted on the operation of the MLDCLI using MATLAB/SIMULINK. The performance parameters chosen in the work include the waveform pattern harmonic spectrum, fundamental value and total harmonic distortion (THD) of the single phase MLDCLI.
  • Comparison of 1-phase cascaded & MLDCLI with PWM contol methods Sri sai institute of technology & science 2 CHAPTER-1 INTRODUCTION
  • Comparison of 1-phase cascaded & MLDCLI with PWM contol methods Sri sai institute of technology & science 3 1.1 Introduction: Power electronics has gone through intense technological evolution during the last three decades. It is a branch of electrical engineering that is concerned with the conversion and control of electrical power for various applications such as industrial, commercial, residential, and aerospace environments. . The utility system usually generates, transmits, and distributes power at a fixed frequency (50 or 60Hz), and fixed voltage is maintained at the consumers terminal. Some residential and industrial applications such as adjustable speed AC drives, induction heating, stand by air craft power supplies, UPS for computers needs three phase adjustable AC power source with controllable frequency and voltage. A power electronics system interfaces between the utility system and industrial loads to satisfy this need. For which we need new types of semi conductor power devices such as IGBT’s (with voltage rating as high as 3.3KV and current rating 100A) and IGCT’s (4.6 KV and 300A) with attractive switching characteristics and high power handling capacity. As a result of this evolution , today most of these industrial and residential loads are connected to the AC power line through cost effective power converters circuits which enhance the over all efficiency, performance and reliability. Among all the modern power electronics converters, the voltage source inverters (VSI) is the simplest and most widely used device with power ratings ranging from fractions of kilowatt to megawatt level. It converts fixed DC voltage to AC voltage with controllable frequency and magnitude.
  • Comparison of 1-phase cascaded & MLDCLI with PWM contol methods Sri sai institute of technology & science 4 1.2 Need for Pulse Width Modulation: A power electronic inverter is essentially a device for creating a variable AC Magnitude and Frequency output from a DC input. The frequency of the output voltage or current is readily established by simply switching for equal time periods to the positive and negative DC bus and appropriately adjusting the half cycle period. However the variable frequency ability is nearly always accompanied by a corresponding need to adjust the amplitude of fundamental component of the output waveform as the frequency changes, i.e., voltage control. One of the mostly widely utilized strategies for controlling the AC output of power electronic converters is the technique known as pulse width modulation (PWM), This varies the duty cycle of the inverter switches at a high frequency to achieve a target average low- frequency output voltage or current. Modulation theory has been a major research area in power electronic for over three decades and continues to attract considerable attention and interest. On the other hand, there have been a number of clear trends in the development of PWM concepts and strategies since the 1970’s, addressing the main objectives of reduced harmonic distortion and increased out put magnitudes for a given switching frequency and the development of modulation strategies to suit different converter topologies. While there has been a wealth of research investigating the modulation and control of lower power DC/AC converters. The actual PWM process for these converters is usually a comparison between a reference waveform and a sawtooth or a triangular carrier waveform. Since voltage source inverters employ switching devices with finite turn-on time and turn-off time characteristics, inverter switching losses are inevitable. Because the switching losses strongly affect the energy efficiency, size and reliability of an inverter, a modulation method with high performance is desirable. Therefore, the modulation method choice is significantly important. Among the variety of modulation methods, the carrier based PWM methods can operate with high switching frequency and they offer high waveform quality and implementation advantages.
  • Comparison of 1-phase cascaded & MLDCLI with PWM contol methods Sri sai institute of technology & science 5 The first important contribution in the carrier based PWM area was done by Schönung and Stemmler in 1964 with the development of the sinusoidal PWM (SPWM) method. In this method the sinusoidal reference waveform of each phase and a periodic triangular carrier wave are compared and the intersection points determine the commutation instants of the associated inverter leg switches. However, this method has a poor voltage linearity range, which is at most 78.5 % of the six-step voltage fundamental component value, hence poor voltage utilization. Therefore, the zero sequence signal injection techniques that extend the SPWM linearity range have been introduced for isolated neutral load applications which comprise the large majority of AC loads. In most three phase AC motor drive and utility interface applications the neutral point is isolated and no neutral current path exists. In such applications in the triangle intersection implementations any zero sequence signal can be injected to the reference modulation waves. K.G. King was the first researcher to utilize this concept in a voltage source inverter. He realized that a three phase varies the duty cycle of the inverter switches at a high frequency to achieve a target average low- frequency output voltage or current. Modulation theory has been a major research area in power electronic for over three decades and continues to attract considerable attention and interest. On the other hand, there have been a number of clear trends in the development of PWM concepts and strategies since the 1970’s, addressing the main objectives of reduced harmonic distortion and increased out put magnitudes for a given switching frequency and the development of modulation strategies to suit different converter topologies. While there has been a wealth of research investigating the modulation and control of lower power DC/AC converters. The actual PWM process for these converters is usually a comparison between a reference waveform and a sawtooth or a triangular carrier waveform. Since voltage source inverters employ switching devices with finite turn-on time and turn-off time characteristics, inverter switching losses are inevitable.
  • Comparison of 1-phase cascaded & MLDCLI with PWM contol methods Sri sai institute of technology & science 6 Because the switching losses strongly affect the energy efficiency, size and reliability of an inverter, a modulation method with high performance is desirable. Therefore, the modulation method choice is significantly important. Among the variety of modulation methods, the carrier based PWM methods can operate with high switching frequency and they offer high waveform quality and implementation advantages. The first important contribution in the carrier based PWM area was done by Schönung and Stemmler in 1964 with the development of the sinusoidal PWM (SPWM) method. In this method the sinusoidal reference waveform of each phase and a periodic triangular carrier wave are compared and the intersection points determine the commutation instants of the associated inverter leg switches. However, this method has a poor voltage linearity range, which is at most 78.5 % of the six-step voltage fundamental component value, hence poor voltage utilization. Therefore, the zero sequence signal injection techniques that extend the SPWM linearity range have been introduced for isolated neutral load applications which comprise the large majority of AC loads. In most three phase AC motor drive and utility interface applications the neutral point is isolated and no neutral current path exists. In such applications in the triangle intersection implementations any zero sequence signal can be injected to the reference modulation waves. K.G. King was the first researcher to utilize this concept in a voltage source inverter. He realized that a three phase. 1.3 Principle of Pulse Width Modulation (PWM): Fig. 1.1 shows circuit model of a single-phase inverter with a center-taped grounded DC bus, and Fig 1.2 illustrates principle of pulse width modulation.
  • Comparison of 1-phase cascaded & MLDCLI with PWM contol methods Sri sai institute of technology & science 7 Fig.1.1 Circuit model of a single-phase inverter Fig.1.2 Pulse width modulation As depicted in Fig. 1.2, the inverter output voltage is determined in the following: When Vcontrol > Vtri, VA0 = Vdc/2 When Vcontrol < Vtri, VA0 = −Vdc/2 Also, the inverter output voltage has the following features: PWM frequency is the same as the frequency of Vtri Amplitude is controlled by the peak value of Vcontrol Fundamental frequency is controlled by the frequency of Vcontrol
  • Comparison of 1-phase cascaded & MLDCLI with PWM contol methods Sri sai institute of technology & science 8 Modulation index (m) is defined as: 2 )( 1 dc AO tri control V Vpeakof V V m Where (VAO)1 : fundamental frequency component of VA0 1.4 Pulse width modulation techniques: The commonly used PWM techniques are : 1) single pulse width modulation 2) multiple pulse width modulation 3) sinusoidal pulse width modulation The SPWM, which is most commonly used, suffers from certain drawbacks like low fundamental output voltage. The other techniques that offer improved performances are: 1. Trapezoidal modulation 2. Stair case modulation 3. Stepped modulation 4. Delta modulation The above PWM techniques are applicable to three-phase inverters. However the following techniques are commonly used for three-phase inverters. 1) third harmonic injected PWM 2) space vector modulation (SVM) 1.5 Comparison of PWM Techniques: Any modulation scheme can be used to create the variable frequency, variable voltage ac waveforms. The sinusoidal PWM compares a high frequency triangular carrier with three sinusoidal reference signals, known as the modulating signals, to generate the gating signals for the inverter switches. This is basically a analog domain technique and is commonly used in
  • Comparison of 1-phase cascaded & MLDCLI with PWM contol methods Sri sai institute of technology & science 9 power conversion with both analog and digital implementation. In contrast to sinusoidal technique the space vector method does not consider each of the three modulating voltages as separate identity. The three voltages are simultaneously taken into account within a two-dimensional reference frame (d-q plane) and the complex reference vector is processed as a single unit. The SVM has the advantages of the lower harmonics and a higher modulation index in addition to the features of complete digital implementation by a single-chip microprocessor. Because of its flexibility of manipulation SVM has increasing applications in power converters and motor control. 1.6 Multi Level Inverters (MLI): In recent years, industry has begun to demand high power equipment, which now reaches the megawatt level. Controlled AC drives in the mega watt range are usually connected to the medium-voltage network. Today it is hard to connect a single power semi-conductor switch directly to medium voltage grids .For these reasons a new family of multilevel inverters has emerged as the solution for working with high voltage levels[1]-[3]. Multilevel inverters include an array of power semiconductors and capacitor voltage sources, the output of which generates voltages with stepped waveforms with less distortion, less switching frequency, higher efficiency, lower voltage devices and better electro-magnetic compatibility. The commutation of the switches permits the addition of the capacitor voltages, which reach high voltages at the output, while the power semiconductors must withstand only reduced voltages. Multilevel inverter structures have been developed to overcome shortcomings in solid-state switching device ratings so they can be applied to higher voltage systems. The multilevel voltage source inverters unique structure allows them to reach high voltages with low harmonics without the use of transformers. The general function of the multilevel inverter is to synthesize a desired AC voltage from several levels of DC voltages. The advent of the transform less multilevel inverters topology has brought forth various pulse width modulation (PWM) schemes as a means to control the switching of the active
  • Comparison of 1-phase cascaded & MLDCLI with PWM contol methods Sri sai institute of technology & science 10 devices in each of the multiple voltage levels in the inverter. Multilevel power conversion technology is a very rapidly growing area of power electronics with good potential for further development. The most attractive application of this technology is in the medium-to-high-voltage range, and includes motor drives, power distribution, and power conditioning applications. In general multilevel inverter can be viewed as voltage synthesizers, in which the high output voltage is synthesized from many discrete smaller voltage levels. The main advantages of this approach are summarized as follows:  They can generate output voltages with extremely low distortion and lower dv/dt.  They draw input current with very low distortion.  They can operate with a lower switching frequency.  Their efficiency is high (>98%) because of the minimum switching frequency.  They are suitable for medium to high power applications.  Multilevel waveform naturally limits the problem of large voltage transients 1.7 Applications of Multi Level inverters: 1. High Power Applications. 2. Where ever need sinusoidal supply, this type of inverter circuit can be implemented. 3. To improve the harmonic characteristics, a seven-level inverter could be modulated by a multilevel carrier technique such as five-level carrier modulation.
  • Comparison of 1-phase cascaded & MLDCLI with PWM contol methods Sri sai institute of technology & science 11 1.8 Total Harmonic Distortion (THD): The total harmonic distortion, or THD, of a signal is a measurement of the harmonic distortion present and is defined as the ratio of the sum of the powers of all harmonic components to the power of the Fundamental frequency. Lesser THD, for example, allows the components in a loudspeaker, amplifier or microphone or other equipment to make a violin sound like a violin when played back, and not a cello or simply a distorted noise. In most cases, the transfer function of a system is linear and time- invariant. When a signal passes through a non-linear device, additional content is added at the harmonics of the original frequencies. THD is a measurement of the extent of that distortion. The measurement is most commonly the ratio of the sum of the powers of all harmonic frequencies to the fundamental frequency power. For a voltage signal, for instance, the ratio of the squares of the RMS voltages is equivalent to the power ratio; In this calculation, Vn means the RMS voltage of harmonic n, where n=1 is the fundamental harmonic. One can also calculate THD using all harmonics. The THD, which is a measure of closeness in shape between a waveform and its fundamental component, is defined as 2 1 ,...3,2 21 n n n V V THD 1.9 Objectives: The main objectives of this thesis is Different topologies of multilevel inverters are studied. Different PWM techniques are studied. SPWM and Modified reference with triangular carriers PWM techniques are selected by considering their advantages. For the voltage source inverters(VSI) pulses are generated using SPWM and Modified reference with triangular carriers .
  • Comparison of 1-phase cascaded & MLDCLI with PWM contol methods Sri sai institute of technology & science 12 Influence of these PWM techniques on the performance of fundamental output voltage and total harmonic distortion (THD) is discussed, through simulation study. A real challenge in the generation of PWM waveforms is to reduce the harmonic distortion in the line currents along with the simultaneous reduction of switching losses in multilevel inverters. The main contribution of this thesis is to come out with a modulation of multilevel inverter based on SPWM, Modified reference with triangular carriers PWM techniques approach which results in better voltage waveforms and improved THD with fundamental output voltage performance. The main focus of this thesis will be on the improved THD in medium and high power applications.
  • Comparison of 1-phase cascaded & MLDCLI with PWM contol methods Sri sai institute of technology & science 13 CHAPTER-2 MULTI LEVEL INVERTERS
  • Comparison of 1-phase cascaded & MLDCLI with PWM contol methods Sri sai institute of technology & science 14 2.1 Multilevel Concept: This passage has the aim to introduce to the general principle of multilevel behavior. Figure1.1 helps to understand how multilevel converters work. The leg of a 2-level converter is represented in Figure 2.1(a) in which the semiconductor switches have been substituted with an ideal switch. The voltage output can assume only two values: 0 or E . Considering Figure 2.1(b), the voltage output of a 3-level inverter leg can assume three values: 0 , E or 2E . In Figure 2.1(c) a generalized m-level inverter leg is presented. Even in this circuit, the semiconductor switches have been substituted with an ideal switch which can provide n different voltage levels to the output. In this short explanation some simplifications have been introduced. In particular, it is considered that the DC voltage sources have the same value and are series connected. In practice there are no such limits, then the voltage levels can be different. This introduces a further possibility which can be useful in multiphase inverters, as it will be shown in the following. A three-phase inverter composed by m-level legs will be considered for the analysis. Obviously the number of phase-to-neutral voltage output levels is m. The number k of the line-to-line voltage levels is given by (2.1). K = 2m-1 (2.1) Considering a star connected load, the number p of phase voltage levels is given by (2.2). P = 2k-1 (2.2)
  • Comparison of 1-phase cascaded & MLDCLI with PWM contol methods Sri sai institute of technology & science 15 For example, considering a 5-level inverter leg, it is possible to obtain 9 lines-to- line voltage level (4 negative levels, 4 positive levels and 0) and 17 phase line voltage levels. Fig.2.1 Multilevel concept for (a) two level (b) three level and (c) m- levelive levels, 4 positive levels and 0) and 17 phase voltage levels Higher the number of levels gives better quality of output voltage which is generated by a greater number of steps with a better approximation of a sinusoidal wave. So, increasing the number of levels gives a benefit to the harmonic distortion of the generated voltage, but a more complex control system is required, when compared to the 2-level inverter. Fig.2.2 Example multilevel sinusoidal approximation using 11-levels.
  • Comparison of 1-phase cascaded & MLDCLI with PWM contol methods Sri sai institute of technology & science 16 Figure 2.2 illustrates an example multilevel waveform. Using multiple levels the multilevel inverter can yield operating characteristics such as high voltages, high power levels, and high efficiency without use of transformers. The multilevel inverter combines individual DC sources at specified times to yield a sinusoidal resemblance; by using more steps to synthesize the sinusoidal waveform, the waveform approaches the desired sinusoid and the total harmonic distortion approaches zero. 2.2 Multilevel Inverters Performance: The limit of standard three-phase converters is related to the maximum power. Which can be delivered to the load, which is related to the maximum voltage and current of a component. Furthermore, higher is the power of a switch lower is the switching frequency. An initial solution to overcome this problem was to connect several switches in series or in parallel. The series connection of two or more semiconductor devices is really difficult due to the impossibility to perfectly synchronize their commutations. In fact, if one component switches off faster than the others it will blow up because it will be subjected to the entire voltage drop designed for the series. Instead, parallel connection is slightly less complicated because of the property of MOSFETs and more recent IGBTs to increase their internal resistance with the increment of junction temperature. When a component switches on faster semiconductors block the entire dc voltage, but share the load current. Several combinational designs have also emerged some involving cascading the fundamental topologies. These designs can create higher power quality for a given number of semiconductor devices than the fundamental topologies alone due to a multiplying effect of the number of levels.
  • Comparison of 1-phase cascaded & MLDCLI with PWM contol methods Sri sai institute of technology & science 17 Fig 2.3 Multilevel inverter topologies. The most actively developed of multilevel topologies are listed in figure 2.3.This Proposed presents a new class of multilevel inverters based on an MLDCL and a bridge inverter. Compared with the existing multilevel inverters, the new MLDCL inverters can significantly reduce the switch count as well as the number of gate drivers as the number of voltage levels increases. For a given number of voltage levels m , the new inverter requires m+3 active switches, roughly half the number of switches, clamping diodes, and voltage-splitting capacitors in the diode-clamped configuration, or clamping capacitors in the flying-capacitor configuration. Simulation and experimental results are included to verify the operating principle of the proposed MLDCL inverters. MULTILEVEL TOPOLOGIES DIODE CLAMPED MULTILEVEL INVERTERS FLYING-CAPACITOR MULTILEVEL INVERTERS CASCADED MULTILEVEL INVERTERS (PROPOSED) MULTILEVEL DC LINK INVERTER
  • Comparison of 1-phase cascaded & MLDCLI with PWM contol methods Sri sai institute of technology & science 18 CHAPTER-3 Comparison of Multilevel Inverters
  • Comparison of 1-phase cascaded & MLDCLI with PWM contol methods Sri sai institute of technology & science 19 Table 1 compares the power component requirements per phase leg among the three multilevel voltage source inverter mentioned above. Table 1 show that the number of main switches and main diodes, needed by the inverters to achieve the same number of voltage levels, is the same. Clamping diodes do not need in flying-capacitor and cascaded-inverter configuration, while balancing capacitors do not need in diode-clamped and cascaded-inverter configuration. Implicitly, the multilevel converter using cascaded-inverters requires the least number of components. Converter Type Diode clamped Flying capacitor Cascaded Inverter (proposed) Multi level Dc Link inverter Main Switching devices (m-1)*2 (m-1)*2 (m-1)*2 m+3 Main diodes (m-1)*2 (m-1)*2 (m-1)*2 m+3 Clamping diodes (m-1)* (m-2) 0 0 0 Dc bus capacitors (m-1) (m-1) (m-1)/2 (m-1)/2 Balancing capacitors 0 ( m-1)* (m- 2)/2 0 0 Table.1 Comparison of Multilevel Inverters Another advantage of cascaded-inverter is circuit layout flexibility. Modularized circuit layout and packaging is possible because each level has the same structure, and there are no extra clamping diodes or voltage balancing capacitors. The number of output voltage levels can be easily adjusted by adding or removing the full-bridge cells.
  • Comparison of 1-phase cascaded & MLDCLI with PWM contol methods Sri sai institute of technology & science 20 3.1 Cascaded Multilevel Inverter The last structure introduced in this thesis is a multilevel inverter, which uses cascaded inverters with separate dc sources (SDCSs). The general function of this multilevel inverter is the same as that of the other two previous inverters. The multilevel inverter using cascaded-inverter with SDCSs synthesizes a desired voltage from several independent sources of dc voltages, which may be obtained from either batteries, fuel cells, or solar cells. This configuration recently becomes very popular in ac power supply and adjustable speed drive applications. This new inverter can avoid extra clamping diodes or voltage balancing capacitors. 3.1.1 Principle of operation of Cascaded 3LI: To produce a staircase output voltage, let us consider only one phase of the three level inverter as shown in the Fig 3.1 Fig.3.1 .1 one phase of cascaded three level H-bridge inverter
  • Comparison of 1-phase cascaded & MLDCLI with PWM contol methods Sri sai institute of technology & science 21 Fig.3.1.2 output waveform for 1-phase 3MLI The ac terminal voltages of different level inverters are connected in series. By different combinations of the four switches, Sa1, Sa2 , Sa1 1 and Sa2 1 , each inverter level can generate three different voltage outputs, +Vdc, - Vdc, and zero as shown in fig2.4(c). The ac output of each of the different level of full-bridge inverters are connected in series such that the synthesized voltage waveform is the sum of the inverter outputs. Note that the number of output phase voltage levels is defined in different way from those of two previous inverters. In this topology, the number of output phase voltage levels is defined by m = 2s+1, where s is the number of dc sources. Table 2 shows the relationship between the allowed switches configurations and the output of a 3- level cascaded inverter.
  • Comparison of 1-phase cascaded & MLDCLI with PWM contol methods Sri sai institute of technology & science 22 Table.2 Switching state for cascaded 3LI Advantages: The series structure allows a scalable, modularized circuit layout and packaging since each bridge has the same structure. Requires the least number of components considering there are no extra clamping diodes or voltage balancing capacitors. Switching redundancy for inner voltage levels is possible because the phase voltage output is the sum of each bridge’s output. Potential of electrical shock is reduced due to the separate dc sources. OUTPUT VOLTAGE Vao SWITCHING SEQUENCE Sa1 Sa2 Sa1 1 Sa2 1 0 1 1 0 0 0 0 1 1 Vdc 1 0 0 1 -Vdc 0 1 1 0
  • Comparison of 1-phase cascaded & MLDCLI with PWM contol methods Sri sai institute of technology & science 23 3.1.2 OPERATING PRINCIPLE OF PROPOSED 7 LEVEL CASCADED INVERTER The configuration and the principle of operation of the proposed inverter is given. Figure 3.2.1(a) circuit diagram for single phase7 level cascaded inverter
  • Comparison of 1-phase cascaded & MLDCLI with PWM contol methods Sri sai institute of technology & science 24 Figure.3.2.1 (b) output wave form of 7 level cascaded inverter In the case of seven level cascaded the ac output voltage at each level can be obtained in the same as in normal 2 level manner. The AC terminal voltages of different level inverters are connected in series. By different combinations of the six switchesS1, S4,S5,S8,S9,and S12 each inverter level can generate four different voltage outputs Vdc,2Vdc,3Vdc , and zero as shown in figure. The ac output of each of the different level of full-bridge inverters are connected in series such that the synthesized voltage waveform is the sum of the inverter outputs.. In this topology, the number of output phase voltage levels is defined by m = 2s+1, where s is the number of dc sources. Advantages: The series structure allows a scalable, modularized circuit layout and packaging since each bridge has the same structure. Requires the least number of components considering there are no extra clamping diodes or voltage balancing capacitors. Switching redundancy for inner voltage levels is possible because the phase voltage output is the sum of each bridge’s output. Potential of electrical shock is reduced due to the separate dc sources of the table given below represents the switching pattern developed for the proposed inverter.
  • Comparison of 1-phase cascaded & MLDCLI with PWM contol methods Sri sai institute of technology & science 25 Output voltage S1 S2 S3 S4 S5 S6 S7 S8 S9 S10 S11 S12 0vdc 1 0 1 0 1 0 1 0 1 0 1 0 vdc 1 0 0 1 0 0 1 1 0 0 1 1 2vdc 1 0 0 1 0 0 1 1 1 0 0 1 3vdc 1 0 0 1 1 0 0 1 1 0 0 1 -vdc 0 1 1 0 1 1 0 0 1 1 0 0 -2vdc 0 1 1 0 0 1 1 0 1 1 0 0 -3vdc 0 1 1 0 0 1 1 0 0 1 1 0 Table .3 Switching sequence for single phase 7 level cascaded inverter 3.3 Generalized m-level Cascaded Multi Level Inverter: A m- level Cascaded H bridge inverter consists of series connected (m-1)/2 number of cells in each phase. Each cell consists of single phase H bridge inverter with separate dc source. There are four active devices in each cell and can produce three levels 0, Vdc/2 and –Vdc/2. Higher voltage levels can be obtained by connecting these cell in cascade and the phase voltage Van is the sum of voltages of individual cells, Van = V1 + V2 + V3 + V4 +….. + VN. For a three phase system, the output of these cascaded inverters can be connected either in Y or Δ configuration.
  • Comparison of 1-phase cascaded & MLDCLI with PWM contol methods Sri sai institute of technology & science 26 Figure: 3.3.1 three phase m-level wye-configuration cascaded inverter
  • Comparison of 1-phase cascaded & MLDCLI with PWM contol methods Sri sai institute of technology & science 27 3.4 OPERATING PRINCIPLE OF PROPOSED 7 LEVEL CASCADED INVERTER Figure 3.4 (a) circuit diagram for 7 level cascaded inverter The proposed single-phase seven-level MLDCL inverter involves various steps of operation. The configuration and the principle of operation of the proposed inverter given
  • Comparison of 1-phase cascaded & MLDCLI with PWM contol methods Sri sai institute of technology & science 28 Figure: 3.4(b) output waveform for 7 levelmdcl inverter Compared with the existing multi level inverters, the new MLDCL inverters can significantly reduce the switch count as well as the no of gate drivers as the no of voltage levels increases. For a given no of voltage levels m, the new inverter requires m+3 active switches, roughfly half of the no of switches, clamping diodes, and voltage-splitting capacitors in the diode clamped configuration or clamping capacitors in the flying capacitor configuration. Simulation and experimental results are included to verify the operating principle of the proposed MLDCL inverters.
  • Comparison of 1-phase cascaded & MLDCLI with PWM contol methods Sri sai institute of technology & science 29 3.4.1Generalized Circuit for Single Phase M Level MLDCL Inverter: Figure 3.4(c) Generalized circuit for dc link inverter 3.5 COMPARISION BETWEEN CASCADED AND MULTILEVEL DC-LINK INVERTER SWITCHES:
  • Comparison of 1-phase cascaded & MLDCLI with PWM contol methods Sri sai institute of technology & science 30 Comparison of the Proposed MLDCL Inverters and the Existing Counterparts. From the previous discussions, it is demonstrated that the proposed MLDCL inverters can significantly reduce the component count. Compared with their existing counter parts for a given number of output voltage levels m. It can be seen that roughly half the number of the components can be eliminated as m increases.
  • Comparison of 1-phase cascaded & MLDCLI with PWM contol methods Sri sai institute of technology & science 31 CHAPTER -4 MODULATION STRATEGIES FOR MULTILEVEL INVERTER
  • Comparison of 1-phase cascaded & MLDCLI with PWM contol methods Sri sai institute of technology & science 32 It is generally accepted that the performance of an inverter, with any switching strategies, can be related to the harmonic contents of its output voltage. Power electronics researchers have always studied many novel control techniques to reduce harmonics in such waveforms. Up-to-date, there are many techniques, which are applied to inverter topologies. In multilevel technology, there are several well-known modulation strategies as follows: Sinusoidal or ―Sub harmonic‖ Natural Pulse Width Modulation (SPWM) Modified Reference Modulated Technique Modified Carrier with Modified Reference Modulated Technique 4.1 Sinusoidal Pulse Width Modulation (SPWM): Sinusoidal pulse width modulation is one of the primitive techniques, which are used to suppress harmonics presented in the quasi-square wave. Note that only triangular carrier is considered in this case. Fig. 4.1 illustrates a simple idea to generate a SPWM waveform. Fig.4.1 Three-phase two-level SPWM with a triangular-carrier
  • Comparison of 1-phase cascaded & MLDCLI with PWM contol methods Sri sai institute of technology & science 33 In multilevel case, PWM techniques with three different disposed triangular carriers were proposed as follows: Alternate phase disposition (APOD) – every carrier waveform is in out of phase with its neighbor carrier by 180°. Phase opposition disposition (POD) – All carrier waveforms above zero reference are in phase and are 180° out of phase with those below zero. Phase disposition (PD) - All carrier waveforms are in phase. This thesis is focused only on all the carriers are in phase (Phase disposition) 4.1.2 SPWM signal for seven-level inverters: Fig.4.1.2 SPWM with triangular multilevel carriers 4.2 Modified Reference Modulated Technique: In the SPWM scheme for two-level inverters, each reference phase voltage is compared with the triangular carrier and the individual pole voltages are generated, independent of each other. To obtain the maximum possible peak amplitude of the fundamental phase voltage, in linear modulation, a common mode voltage, Voffset1, is added to the reference phase voltages[8,1], where the magnitude of Voffset1 is given by 2 )( minmax 1 VV Voffset --------- (4.1)
  • Comparison of 1-phase cascaded & MLDCLI with PWM contol methods Sri sai institute of technology & science 34 In eq 4.1, Vmax is the maximum magnitude of the three sampled reference phase voltages, while Vmin is the minimum magnitude of the three sampled reference phase voltages, in a sampling interval. The addition of the common mode voltage, Voffset1, results in the active inverter switching vectors being centred in a sampling interval, making the SPWM technique equivalent to the modified reference PWM technique [3]. Equation 4.1 is based on the fact that, in a sampling interval, the reference phase which has lowest magnitude (termed the min-phase) crosses the triangular carrier first, and causes the first transition in the inverter switching state. While the reference phase, which has the maximum magnitude (termed the max-phase), crosses the carrier last and causes the last switching transition in the inverter switching states in a two-level modified reference PWM scheme. Thus the switching periods of the active vectors can be determined from the (max-phase and min-phase) sampled reference phase voltage amplitudes in a two-level inverter scheme. The SPWM technique, for multilevel inverters, involves comparing the reference phase voltage signals with a number of symmetrical level-shifted carrier waves for PWM generation. It has been shown that for an m-level inverter, (m-1) level-shifted carrier waves are required for comparison with the sinusoidal references [3]. Because of the level-shifted multicarriers as shown in (Fig. 4.4), the first crossing (termed the first-cross) of the reference phase voltage cannot always be the min- phase. Similarly, the last crossing (termed the third-cross) of the reference phase voltage cannot always be the max-phase. Thus the offset voltage computation, based on equation 4.1 is not sufficient to centre the middle inverter switching vectors, in a multilevel PWM scheme during a sampling period Ts . In this thesis, a simple technique to determine the offset voltage (to be added to the reference phase voltage for PWM generation for the entire modulation range) is presented, based only on the sampled amplitudes of the reference phase voltages. The idea behind the proposed scheme is to determine the sampled reference phase, from the three sampled reference phases, which crosses the triangular first (first- cross) and the reference phase which crosses the triangular carrier last (third- cross). Once the first-cross phase and third-cross phase are identified, the
  • Comparison of 1-phase cascaded & MLDCLI with PWM contol methods Sri sai institute of technology & science 35 principles of offset calculation of equation 4.1, for the two-level inverter, can easily be adapted for the multilevel modified reference PWM generation scheme. The proposed modified reference PWM technique presents a simple way to determine the time instants at which the three reference phases cross the triangular carriers. These time instants are sorted to find the offset voltage to be added to the reference phase voltages for modified reference PWM generation for multilevel inverters for the entire linear modulation range, so that the middle inverter switching vectors are centred (during a sampling interval), as in the case of the conventional two-level modified reference PWM scheme. The sine-triangle method for a seven-level inverter. phase modulation signal is compared with six (n-1 in general) triangle waveforms. The N – 1 = 6 modified carrier waveforms are arranged so that every modified carrier is in phase. The converter switches to + 3Vdc / 2 when the reference is greater than all the carrier waveforms. The converter switches to Vdc when the reference is less than the uppermost carrier waveform and greater than all the other carrier waveforms. The converter switches to Vdc / 2 when the reference is less than the two uppermost carrier waveforms and greater than all other carriers. The converter switches to 0 when the reference is less than the three uppermost carrier waveform and greater than three lowermost carriers. The converter switches to - Vdc/2 when the reference is greater than the lowermost carrier waveform and lesser than all other carriers. The converter switches to -Vdc when the reference is greater than the two uppermost carrier waveforms and less than all other carriers. The converter switches to -3Vdc / 2 when the reference is lesser than all the carrier waveforms.
  • Comparison of 1-phase cascaded & MLDCLI with PWM contol methods Sri sai institute of technology & science 36 4.2.2 Modified Reference Modulated waveform for seven-level Inverters: Fig.4.2.2 modified reference with triangular carriers for 7-level inverters 4.3 Modulation techniques for m-level multilevel inverters with triangular carriers with modified carriers: The modified reference PWM, proposed for a five-level inverter, in the last Section, can be easily extended to any m-level PWM generation. In the SPWM scheme for an m level inverter, the reference signals are compared with (m-1) level shifted carriers [3].The triangular carriers and modified carriers with the modified reference signals, for an m-level PWM scheme are shown in Figure 4.8(a) and figure 4.9(a) for m is odd, and in Fig. 4.8(b) and fig 4.9(b) for m is even respectively. The (m-1) triangular carriers and (m-1) modified carriers are compared with modified reference phase voltages as shown in Figures 4.8(a), 4.8(b), 4.9(a) and 4.9(b) respectively . A carrier index is defined to designate the carrier regions in which the reference phase voltages lie during the sampling interval under consideration. The carrier index is as shown in Fig. 4.8(a) when n is odd. The carrier index for the top carrier is 1, and it increases in steps of 1 towards the bottom carriers. The carrier index for the lowest carrier is equal to (m–1).
  • Comparison of 1-phase cascaded & MLDCLI with PWM contol methods Sri sai institute of technology & science 37 fig.a fig.b Fig 4.3 Modified reference with triangular multilevel carriers (a) m-level PWM scheme where m is odd (b) m-level PWM scheme where m is even
  • Comparison of 1-phase cascaded & MLDCLI with PWM contol methods Sri sai institute of technology & science 38 CHAPTER-5 SIMULATION DIAGRAMS
  • Comparison of 1-phase cascaded & MLDCLI with PWM contol methods Sri sai institute of technology & science 39 SINGLE PHASE 7-LEVEL CASCADED MULTILEVEL INVERTER Figure 5.1 Single phase 7-Level Cascaded Multilevel Inverter
  • Comparison of 1-phase cascaded & MLDCLI with PWM contol methods Sri sai institute of technology & science 40 SINGLE PHASE 7-LEVEL MULTILEVEL DC LINK INVERTER Figure 5.2 Single phase 7-Level Multilevel DC Link Inverter
  • Comparison of 1-phase cascaded & MLDCLI with PWM contol methods Sri sai institute of technology & science 41 CHAPTER- 6 SIMULATION RESULTS
  • Comparison of 1-phase cascaded & MLDCLI with PWM contol methods Sri sai institute of technology & science 42 SIMULATION RESULTS:  Seven Level Cascaded MLI for 1–Ф Sinusoidal Pulse Width Modulation (SPWM): Fig. 6.1line voltage of Seven level Cascaded MLI Fig. 6.2 THD of SPWM for seven Level cascaded MLI
  • Comparison of 1-phase cascaded & MLDCLI with PWM contol methods Sri sai institute of technology & science 43 Seven Level MLDCLI for 1–Ф Sinusoidal Pulse Width Modulation (SPWM): Fig.6.3 line voltage of seven level MLDCLI Fig. 6.4 THD of SPWM for seven Level MLDCI
  • Comparison of 1-phase cascaded & MLDCLI with PWM contol methods Sri sai institute of technology & science 44 Comparison of results for single phase : Input voltage = 300 Volts Switching frequency = 5000 Hertzs Modulation index = 0.86666 PWM technique Cascaded 7LI Multilevel DCL 7LI Fundamental Output Voltage(V) THD (%) Fundamental Output Voltage(V) THD (%) Sinusoidal PWM 253.4 23.13 268.4 22.01
  • Comparison of 1-phase cascaded & MLDCLI with PWM contol methods Sri sai institute of technology & science 45 CHAPTER -7 CONCLUSION
  • Comparison of 1-phase cascaded & MLDCLI with PWM contol methods Sri sai institute of technology & science 46 CONCLUSION AND FUTURE SCOPE: Conclusion: A summary of THD and fundamental output voltage for various multilevel inverter topologies with their control strategies are presented. 7-Level Cascaded inverter and 7-level D.C link inverters were simulated for SPWM and modified SVPWM with triangular carriers. And it is concluded that 7-level dc-link inverter with a modified SVPWM with triangular carriers has given good fundamental output voltage (268.4 V) with less THD (22.01%). Future Scope: The single phase proposed Multilevel Inverter can be extended to three phase proposed Multilevel Inverter and output of three phase MLI can fed as an input source to a three phase Induction Motor.
  • Comparison of 1-phase cascaded & MLDCLI with PWM contol methods Sri sai institute of technology & science 47 CHAPTER-8 REFERENCES
  • Comparison of 1-phase cascaded & MLDCLI with PWM contol methods Sri sai institute of technology & science 48 REFERENCES 1) Gui- jia su, senior member ,IEEE ―Multilevel DC-Link Inverter ‖, IEEE Trans. on Indapplications, vol.41, issue 4, pp.724-738,may/june 2005. 2) Zhong Du, i.e, Leon M.Tolbert, senior member ―Fundamental Frequency Switching Strategies of a Seven – level Hybride Cascaded H-Bridge Multilevel Inverter ‖, IEEE Transactions on, vol.24, no.1, Jan 2009. 3) J. Rodr´ıguez, J. Lai, and F. Peng, ―Multilevel inverters:Asurvey of topologies, controls and applications,‖ IEEE Trans. Ind. Electron., vol. 49, no. 4, pp. 724–738, Aug. 2002. 4) W. Yao, H. Hu, and Z. Lu, ―Comparisons of space-vector modulation and carrier-based modulation of multilevel inverter,‖ IEEE Trans. Power Electron., vol. 23, no. 1, pp. 45–51, Jan. 2008. 5) J. N. Chiasson, L. M. Tolbert, K. J.McKenzie, and Z.Du, ―A new approach to solving the harmonic elimination equations for a multilevel converter,‖in Proc. IEEE Ind. Appl. Soc. Annu. Meeting, Salt Lake City, UT, Oct. 12–16, 2003, pp. 640–645. 6) Z. Du, L. M. Tolbert, and J. N. Chiasson, ―Active harmonic elimination for multilevel converters,‖ IEEE Trans. Power Electron, vol. 21, no. 2, pp. 459–469, Mar. 2006. 7) V. Blasko, ―A novel method for selective harmonic elimination in power electronic equipment,‖ IEEE Trans. Power Electron, vol. 22, no. 1, pp. 223–228, Jan. 2007. 8) J. R. Wells, X. Geng, P. L. Chapman, P. T. Krein, and B. M. Nee, ―Modulation-based harmonic elimination,‖ IEEE Trans. Power Electron., vol. 22, no. 1, pp. 336–340, Jan. 2007. 9) S.Mariethoz, A.Rufer,‖Resolution and efficiency improvements for three-phase cascaded multilevel inverters‖, IEEE transaction, 2004.
  • Comparison of 1-phase cascaded & MLDCLI with PWM contol methods Sri sai institute of technology & science 49 10) K. Thorborg and A. Nystorm, ―Staircase PWM: an uncomplicated and efficient modulation technique for ac motor drives,‖ IEEE Transactions on Power Electronics, Vol. PE3, No.4, 1988, pp. 391-398 11) J. C. Salmon, S. Olsen, and N. Durdle, ―A three-phase PWM strategy using a stepped 12 reference waveform,‖ IEEE Transactions on Industry Applications, Vol. IA27, No. 5, 1991, pp.914-920 12) Gerardo Ceglia, Víctor Guzmán,Member ,IEEE, Carlos Sánchez, Fernando Ibáñez, Julio Walter, and María I. Giménez,Member ,IEEE , ―A New Simplified Multilevel Inverter Topology for DC–AC Conversion,‖IEEE Transactions on Power Electronics, vol. 21, no. 5, Sep.2006. 13) M. Marchesoni and M. Mazzucchelli, ―Multilevel converters for high power AC drives: a review,‖ in Proc. IEEE ISIE’93, Budapest, Hungary, 1993, pp. 38–43. 14) C. Hochgraf, R. Lasseter, D. Divan, and T. A. Lipo, ―Comparison of multilevel inverters for static var compensation,‖ in Conf. Rec. 1994 IEEE-IAS Annu. Meeting, pp. 921–928. 15) J. Zhang, ―High performance control of a 3 level IGBT inverter fed AC drive,‖ in Conf. Rec. 1995 IEEE-IAS Annu. Meeting, pp. 22–28. 16) P.W. Hammond, ―A new approach to enhance power quality for medium voltage drives,‖ in Proc. 1995 IEEE-IAS PCIC, pp. 231–235. 17) J. S. Lai and F. Z. Peng, ―Multilevel converters—a new breed of power converters,‖ in Conf. Rec. 1995 IEEE-IAS Annu. Meeting, pp. 2348– 2356.