2013-2014 VLSI Titles
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2013-2014 VLSI Titles

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2013-2014 VLSI Titles Document Transcript

  • 1. 1. 0.6mW 6.3 GHz 40nm CMOS divide-by-23 prescaler using heterodyne phase-locking technique 2. 1.2-V Supply, 100-nW, 1.09-V Bandgap and 0.7-V Supply, 52.5-nW, 0.55V Subbandgap Reference Circuits for Nanowatt CMOS LSIs 3. 10-bit 30-MSs SAR ADC Using a Switchback Switching Method 4. A 0.41 μA Standby Leakage 32 kb Embedded SRAM with Low-Voltage Resume-Standby Utilizing All Digital Current Comparator in 28 nm HKMG CMOS 5. A 6-b 4.1-GSs Flash ADC With Time-Domain Latch Interpolation in 90-nm CMOS 6. A 10-bit 25-MSs 1.25-mW Pipelined ADC With a Semidigital Gm-Based Amplifier 7. A CMOS High-Voltage Transmitter IC for Ultrasound Medical Imaging Applications 8. A Colpitts CMOS Quadrature VCO Using Direct Connection of Substrates for Coupling 9. A Design Approach of Low Power VLSI for Downsampler Using Multirate Technique
  • 2. 10.A Fast and Accurate FPGA-Based Fault Injection System 11.A Mixed Signal (Analog-Digital) Integrator Design 12.A New Leakage Reduction Method for Ultra Low Power VLSI Design for Portable Devices 13.A novel fault detection and correction technique for memory applications 14.A Reconfigurable 1 GSps to 250 MSps, 7-bit to 9-bit Highly TimeInterleaved Counter ADC with Low Power Comparator Design 15.A Self-Checking Approach for SEUMBUs- Hardened FSMs Design Based on the Replication of One-Hot Code 16.A Wide Temperature, Radiation Tolerant, CMOS-Compatible Precision Voltage Reference for Extreme Radiation Environment Instrumentation Systems 17.An 8-to-1 bit 1-MSs SAR ADC With VGA and Integrated Data Compression for Neural Recording 18.Application of Fixator-Norator Pairs in Designing Active Loads and Current Mirrors in Analog Integrated Circuits
  • 3. 19.Cross-Coupled Current Conveyor Based CMOS Transimpedance Amplifier for Broadband Data Transmission 20.Design of a Low-Voltage, Low-Power, High-Gain Operational Amplifier for Data Conversion Applications 21.Design of Low Voltage High Speed Operational Amplifier for Pipelined ADC in 90 nm Standard CMOS Process 22.High-Voltage Tolerant Digitally Aided DCMPWM Multiphase DC-DC Boost Converter With Integrated Schottky Diodes in 0.13 μm 1.2 V Digital CMOS Process 23.Implementation of Real coded Genetic Algorithms using FPGA Technology 24.Improved Accuracy Current-ModeMultiplier Circuits With Applications in Analog Signal Processing 25.Incremental Trace-Buffer Insertion for FPGA Debug 26.K-Algorithm An Improved Booth’s Recoding for Optimal Fault-Tolerant Reversible Multiplier 27.Low Power Prescaler Implementation in CMOS VLSI
  • 4. 28.Low Voltage and Low Power Divide-By-23 Counter Design Using Pass Transistor Logic Circuit Technique 29.Low-Cost Scan-Chain-Based Technique to Recover Multiple Errors in TMR Systems 30.Low-Power Correlation for IEEE 802.16 OFDM Synchronization on FPGA 31.Low-Power Level Shifter for Multi-Supply Voltage Designs 32.Performance Analysis of Power Gating designs in Low Power VLSI Circuits 33.PODIA Power Optimization through Differential Imbalanced Amplifier 34.Power-Up Sequence Control for MTCMOS Designs 35.Reconsidering High-Speed Design Criteria for Transmission-Gate-Based Master–Slave Flip-Flops 36.Robust Secure Scan Design Against Scan-Based Differential Cryptanalysis 37.Sub-mW LC Dual-Input Injection-Locked Oscillator for Autonomous WBSNs 38.Ultra-Low Power VLSI Circuit Design Demystified and Explained A Tutorial
  • 5. 39.Ultralow-Voltage Process-Variation-Tolerant Schmitt-Trigger-Based SRAM Design 40.Verification of USB 3.0 Device IP using Universal Verification Methodology 41.Zero -Order Control of Boost DC-DC Converter With Transient Enhancement Scheme
  • 6. 39.Ultralow-Voltage Process-Variation-Tolerant Schmitt-Trigger-Based SRAM Design 40.Verification of USB 3.0 Device IP using Universal Verification Methodology 41.Zero -Order Control of Boost DC-DC Converter With Transient Enhancement Scheme