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Asmc Powerpoint Presentation

  1. 1. Methods for Fast Yield Learning in A DRAM Wafer Fab using a Remote Packaging and Test Site .
  2. 2. Authors
  3. 3. Abstract In this paper, we describe the issues and solutions for overcoming the distance between a DRAM wafer fab facility and a remote packaging and test site. Fast cycle time of experimental feedback allow for accelerated yield learning and volume ramping.
  4. 4. INFINEON - Richmond
  5. 5. INFINEON - Porto
  6. 6. <ul><li>Maximum Yield requires ability to implement changes FAST </li></ul><ul><li>REQUIRES : </li></ul><ul><li>Fast feedback from electrical test results on packaged die or components. </li></ul><ul><li>- controlled experiments </li></ul><ul><li>- tool releases </li></ul><ul><li>- excursions </li></ul><ul><li>- and standard processing </li></ul>PROBLEM BACKGROUND <ul><li>DISTANCE : </li></ul><ul><ul><li>Most are located away from the FAB due to cost considerations. </li></ul></ul><ul><li>DIRECTION : </li></ul><ul><ul><li>Most are primarily cost-driven with little focus on special requirements for experimental evaluations. </li></ul></ul>
  7. 7. SPECIAL REQUESTS SWR’s: (Special Work Requests) - FE (wafer Front End) lots with non-standard processing (examples: extended BI, DC Dataloging for Characterization) or experimental designs used to evaluate a potential yield improvement, performance window or new tool qualification. New Product or Technology introduction . - FE lots of a new product or technology which in development. A Front End Process excursion - Potential quality risk which requires non-standard processing and/or containment.
  8. 8. ISSUES <ul><li>Cycle time </li></ul><ul><ul><li>Lots now included a 2 day transit time to ship wafers from the U.S. to Portugal . </li></ul></ul><ul><li>Production/Cost Impact </li></ul><ul><ul><li>Porto would now have between 5 and 10% non-standard flow lots. </li></ul></ul><ul><li>DATA Access </li></ul><ul><ul><li>Richmond Yield Engineers required real-time access to Porto WIP and Yield data. </li></ul></ul><ul><li>Quality Containment </li></ul><ul><ul><li>Porto systems would have to contain and evaluate lots at risk for lower quality. </li></ul></ul><ul><li>Quality Monitoring </li></ul><ul><ul><li>Porto would have to perform all quality monitoring tests </li></ul></ul><ul><li>Fail Samples </li></ul><ul><ul><li>Porto to provide both standard and discrepant samples to Richmond for analysis. </li></ul></ul><ul><li>Test Program Evaluation </li></ul><ul><ul><li>All new test program evaluations on volume product done in Porto. </li></ul></ul><ul><li>System Mismatch </li></ul><ul><ul><li>Porto WIP tracking system is FAB300, Richmond uses PROMIS. </li></ul></ul><ul><li>Culture </li></ul><ul><ul><li>Porto would have to change from cost driven to service orientation. </li></ul></ul>
  10. 10. PROJECT MANAGEMENT The Charter
  12. 12. SYSTEM SOLUTIONS <ul><li>Real Time ATE data transfer from Porto to Richmond. </li></ul><ul><li>Lot level attributes for Special Work Requests – non standard processing in Porto. </li></ul><ul><li>FAB300 dispatching software to receive attribute and execute SWR in Porto. </li></ul><ul><li>Communication structures: Planning Processes, Yield meetings, Engineering knowledge exchanges. </li></ul><ul><li>Priority dispatching systems in Porto. </li></ul><ul><li>Special shipping channels. </li></ul><ul><li>Wafer Level quality assessment system </li></ul>
  13. 13. LOT LEVEL ATTRIBUTES The Porto WIP system was modified to read these attributes and run the lots thru newly created test flows as listed in Table.
  14. 14. QUALITY ASSESMENT <ul><li>Continuous Test Flow process – unlimited merging </li></ul><ul><li>Lot integrity is only maintained by two methods; </li></ul><ul><li>1.) Attribute that prevents the merger of a lot </li></ul><ul><li>2.) Recording of chip, wafer and lot data at each test step. </li></ul><ul><li>If the quality of lot is known to be at risk prior to shipment to Porto, method 1) can be utilized and a special hold attribute is added to the lot. </li></ul><ul><li>- The lot is then automatically held at a Quality Control Test Gate, where a final assessment is made. </li></ul><ul><li>Using method 2), an assessment is made of the individual wafer’s yield vs. quality level limits. The affected wafer is then sorted out and downgraded at the next test insertion. WAFER LEVEL ELVALUATION </li></ul><ul><li>These processes are equal or better at quality assessment and risk containment than the previous systems in Richmond or Porto. </li></ul>
  15. 15. RESULTS (Cycle Time) <ul><ul><li>Priority lots = top of the queue for every operation. </li></ul></ul><ul><li>Special “time-matters” shipping channel established with Lufthansa airlines to guarantee shipping time to < 24 hours. </li></ul>
  16. 16. RESULTS (Volume Assesment)
  17. 17. RESULTS (Daily Shipment Report)
  18. 18. RESULTS (Summary) Quality Gate and Lot Attributes Quality Gates & Engineering Intervention Risk Containment Lot Level Parameters in FAB300 SWR Document Special Lot Flows WEB Based Report PROMIS WIP Forecast (Fig.4) Wafer Level Lot Level Quality Assessment 5% 30% Volume Impact 2X ( Fig.3 ) 2X (theoretical) Cycle Time PORTO BE RICHMOND BE FEATURE
  19. 19. CONCLUSION Transfer and development of BE learning systems from Richmond to Porto provided an estimated annual savings of $30M with no change in the learning rate and yield ramp of the Richmond FE. The system is currently planned for transfer to other Infineon BE sites in Malacca and China.