Design for Manufacturability Guidelines                         Design for Manufacturability                              ...
Design for Manufacturability GuidelinesINDEXSTANDARD PANEL SIZES ............................................................
Design for Manufacturability GuidelinesTABLESTABLE 1 – PANEL SIZE AVAILABILITY ..............................................
Design for Manufacturability GuidelinesIntroductionThis manual provides an overview of the requirements for the Design for...
Design for Manufacturability GuidelinesPanelizationSpecifications                Standard                              Adv...
Design for Manufacturability GuidelinesRaw laminate is the single principal cost constituent of a multilayer PCB. Optimizi...
Design for Manufacturability Guidelines                         Figure 2 - Layout without Edge ConnectorsGold-Electroplate...
Design for Manufacturability Guidelines             Plating Frame                                   Maximum Distance 24.0”...
Design for Manufacturability Guidelines                                                                  0.100”          U...
Design for Manufacturability GuidelinesControlled ImpedanceControl geometry to assure product conformance > 10%Control imp...
Design for Manufacturability Guidelinesreduction of the line width during the etching process. The exception to this is wi...
Design for Manufacturability Guidelines                                 Standard Material Tolerances                      ...
Design for Manufacturability GuidelinesTable 8 – UL Listing Card        13 of 65
Design for Manufacturability GuidelinesMultilayer Construction GuidelinesWhen designing multilayer constructions for PCBs ...
Design for Manufacturability GuidelinesBlind and Buried Via (BBV) BoardsGeneral descriptionLike through holes in a convent...
Design for Manufacturability GuidelinesA blind hole via does not pass through the entire board, and has access to only one...
Design for Manufacturability GuidelinesA buried via provides connection within inner layers, it has no access to the exter...
Design for Manufacturability GuidelinesBlind and Buried Via Design Constraints    •   Core thickness 0.003 minimumNote: 0....
Design for Manufacturability GuidelinesMicroviasMicrovias rulesProcess 1 - Standard Conformal Opening    •   Micro via dia...
Design for Manufacturability GuidelinesConductive Features      Specification                   Standard                  ...
Design for Manufacturability Guidelines              Annular Ring               Plated Hole                               ...
Design for Manufacturability Guidelines                                  Line Width                                       ...
Design for Manufacturability GuidelinesDesigner Reference TableInternal Signal LayersPreferred trace / space: 0.004” / 0.0...
Design for Manufacturability GuidelinesNickel/Gold Edge Connectors                                                        ...
Design for Manufacturability GuidelinesHoles and Slots Specification                        Standard                   Adv...
Design for Manufacturability GuidelinesMicro ViaMaximum panel size: 18” x 24”Routing, Bevelling and Scoring       Specific...
Design for Manufacturability Guidelines                                           Printed Circuit Board                   ...
Design for Manufacturability Guidelinesplane when the boards are bevelled. The following angles and depths may be achieved...
Design for Manufacturability GuidelinesThis process places grooves on opposite sides of a panel or between boards, for the...
Design for Manufacturability GuidelinesSoldermaskSoldermask AvailabilityA variety of soldermasks have been selected to fil...
Design for Manufacturability GuidelinesGreen is the preferred soldermask colour.Soldermask allows a 0.003” web to be place...
Design for Manufacturability Guidelines       creating a cap over the hole. Artwork modifications necessary for processing...
Design for Manufacturability GuidelinesColour: white (epoxy) preferred, Yellow (epoxy), Black and White (Liquid Photoimage...
Design for Manufacturability GuidelinesSurface Finishes                   Table 14 – Surface Finish Comparison            ...
Design for Manufacturability GuidelinesTable 15 – Surface Finish Reference Guide                35 of 65
Design for Manufacturability GuidelinesElectrical Test        Specification                       Standard                ...
Design for Manufacturability GuidelinesIsolation Resistance - the minimum resistance allowable between separate electrical...
Design for Manufacturability Guidelines                   Critical outline                Hole chart that                 ...
Design for Manufacturability GuidelinesFile Name:         README.TXTFormat:            ASCII, or MS/WordContents:         ...
Design for Manufacturability GuidelinesTable 20 – Design Capabilities             40
Design for Manufacturability GuidelinesFigure 24 – PCB Manufacturing Process                 41
Design for Manufacturability GuidelinesOuter Layer Plating Process Pattern Plating Process            Basic              L...
Design for Manufacturability GuidelinesThe allowance for etching of plated designs is as follows:                         ...
Design for Manufacturability GuidelinesGlossary of TermsAActivating: A treatment that renders nonconductive material recep...
Design for Manufacturability GuidelinesBBBT: Bare Board Test.B-Stage Material: Sheet material impregnated with a resin cur...
Design for Manufacturability GuidelinesBoard Thickness: Standard base thickness is 1/16 which is also called out as .062 o...
Design for Manufacturability GuidelinesChamfer: A broken corner to eliminate an otherwise sharp edge.Characteristic Impeda...
Design for Manufacturability GuidelinesComputer-Aided Design (CAD): A software program with algorithms for drafting and mo...
Design for Manufacturability GuidelinesCopper Invar Copper: A multilayer metal alloy of a specific proportion, laminated t...
Design for Manufacturability GuidelinesDefinition: The accuracy of reproduction of pattern edges, especially in a printed ...
Design for Manufacturability GuidelinesDrawing or Print: This usually includes a drawing of the board outline with symbols...
Design for Manufacturability GuidelinesElectroless Copper: A thin layer of copper deposited on the plastic or metallic sur...
Dapc Dfm Guide 2.0
Dapc Dfm Guide 2.0
Dapc Dfm Guide 2.0
Dapc Dfm Guide 2.0
Dapc Dfm Guide 2.0
Dapc Dfm Guide 2.0
Dapc Dfm Guide 2.0
Dapc Dfm Guide 2.0
Dapc Dfm Guide 2.0
Dapc Dfm Guide 2.0
Dapc Dfm Guide 2.0
Dapc Dfm Guide 2.0
Dapc Dfm Guide 2.0
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Dapc Dfm Guide 2.0

  1. 1. Design for Manufacturability Guidelines Design for Manufacturability Guidelines USE FOR REFERENCE ONLY UNCONTROLLED COPY PROPRIETARYPURPOSE / SCOPEThis document establishes the procedure for the creation of tooling as performed by theEngineering Department. These standards are expected to yield product in accordance with thecustomer design criteria and the most current DAPC manufacturing capabilities. These guidelinesdefine the criteria that will allow a part to be processed using a department’s normal operatingprocesses. These guidelines also define the criteria to attain the maximum producible level.Concessions to these requirements are expected to reduce the producible level impacting costand potentially yield or may require process modifications. The manufacturing tolerances, etchloss characteristics, and drill sizes defined by this standard supports typical product manufacturedat DAPCV04.21.2008 1 of 65
  2. 2. Design for Manufacturability GuidelinesINDEXSTANDARD PANEL SIZES .....................................................................................................................6CONTROLLED IMPEDANCE .................................................................................................................10CONTROLLED IMPEDANCE MODELING ................................................................................................10LAYER STACK UP ..............................................................................................................................11MULTILAYER CONSTRUCTION GUIDELINES .........................................................................................14MULTILAYER CONSTRUCTIONS ..........................................................................................................14BLIND AND BURIED VIA DESIGN CONSTRAINTS ...................................................................................18MICROVIAS .......................................................................................................................................19FILLED VIAS ......................................................................................................................................19CONDUCTIVE FEATURES ...................................................................................................................20HOLES AND SLOTS ............................................................................................................................25ROUTING ..........................................................................................................................................26BEVELLING .......................................................................................................................................27SCORING ..........................................................................................................................................28SOLDERMASK ...................................................................................................................................30LEGEND MARKING .............................................................................................................................32SURFACE FINISHES ...........................................................................................................................34ELECTRICAL TEST .............................................................................................................................36PCB DATA REQUIREMENTS ...............................................................................................................37CUSTOMER DATA MUST INCLUDE: .....................................................................................................37COMMON DATA ISSUES .....................................................................................................................39FIGURESFIGURE 1 - TYPICAL 18 X 24 PANEL .....................................................................................................5FIGURE 2 - LAYOUT WITHOUT EDGE CONNECTORS .......................................................................................7FIGURE 3 - GOLD PLATING INTERCONNECTION COMPONENTS .....................................................................8FIGURE 4 - LAYOUT - EDGE CONNECTORS ....................................................................................................8FIGURE 5 - LAY-UP WITH RECESSED EDGE CONNECTORS ............................................................................9FIGURE 6 – THROUGH HOLE VIA ..................................................................................................................15FIGURE 7 – BLIND VIA AND THROUGH HOLE VIA .........................................................................................16FIGURE 8 – BURIED VIA AND THROUGH HOLE VIA.......................................................................................17FIGURE 9 – STANDARD TEARDROP ..............................................................................................................21FIGURE 10- ANNULAR RING / TANGENCY / BREAKOUT ................................................................................21FIGURE 11- LINE WIDTH & SPACING MEASUREMENT ..................................................................................22FIGURE 12 - AVOID THERMAL ISOLATION & SLIVERS OF COPPER ..............................................................22FIGURE 13 - HOLE-TO-COPPER SPACING .....................................................................................................23FIGURE 14 - VIA-TO-GOLD EDGE CONNECTOR SPACING ..............................................................................24FIGURE 15 - ROUND THIEVING .....................................................................................................................24FIGURE 16 - BREAKAWAY TAB SPACING ......................................................................................................27FIGURE 17 – BEVEL DIAGRAM ......................................................................................................................27FIGURE 18 - EDGE MILLING DIAGRAM ..........................................................................................................28FIGURE 19 - SCORING BLADE DIAGRAM.......................................................................................................29FIGURE 20 – VIA PLUGGING .........................................................................................................................30FIGURE 21 - SOLDERMASK SMD CLEARANCES ...........................................................................................31FIGURE 22 - FABRICATION DRAWING REQUIREMENTS .........................................................................38FIGURE 23 – PCB MANUFACTURING PROCESS ..................................................................................41FIGURE 24 – OUTER LAYER PLATING PROCESSES ..............................................................................42FIGURE 25 – INNER LAYER PROCESS .................................................................................................43 2 of 65
  3. 3. Design for Manufacturability GuidelinesTABLESTABLE 1 – PANEL SIZE AVAILABILITY ....................................................................................................5TABLE 2 – USEABLE PANEL AREA ........................................................................................................6TABLE 3 - EDGE CONNECTOR RESTRICTIONS .......................................................................................7TABLE 4 – AVAILABLE MATERIAL TYPES .............................................................................................11TABLE 5 - LAMINATE (CORE) TOLERANCES .........................................................................................12TABLE 6 – PRE-PREG TOLERANCES...................................................................................................12TABLE 7 - COPPER FOIL EQUIVALENT THICKNESSES ...........................................................................12TABLE 8 – UL LISTING CARD .............................................................................................................13TABLE 9 – CONDUCTIVE FEATURES ...................................................................................................20TABLE 10 – HOLES AND SLOTS ..........................................................................................................25TABLE 11 – ROUTING, BEVELING AND SCORING .................................................................................26TABLE 12 – SOLDERMASK AVAILABILITY .............................................................................................30TABLE 13 - LEGEND MARKING SPECIFICATIONS ..................................................................................32TABLE 14 – SURFACE FINISH COMPARISON........................................................................................34TABLE 15 – SURFACE FINISH REFERENCE GUIDE ...............................................................................35TABLE 16 – ELECTRICAL TEST PARAMETERS......................................................................................36TABLE 17 – DATA REQUIREMENTS .....................................................................................................37TABLE 18 – FILE FORMATS ................................................................................................................38TABLE 19 – PREFERRED README FILE CONTENTS .............................................................................39TABLE 20 – DESIGN CAPABILITIES .....................................................................................................40TABLE 21 – ETCH LOSS.....................................................................................................................43 3 of 65
  4. 4. Design for Manufacturability GuidelinesIntroductionThis manual provides an overview of the requirements for the Design for Manufacturability (DFM)and reliability for rigid multilayer printed circuit boards.Manufacturability is the practice of designing printed circuit boards that meet not only thecapabilities of the customer’s assembly manufacturing process but also the capabilities of theboard fabrication process. Some of the benefits of DFM are: • Higher Quality • Reduced Lead Times • Lower Material Costs • Higher first pass yields • Minimized environmental impactTo achieve these benefits, this manual has been developed to enable a printed circuit boarddesigner to understand the key cost drivers relative to bare board manufacture. The cost driversare: • Raw laminate – both panel utilization and material selection • Complexity factors (component / design technology) • Total number of holes • Surface finish requirements • Soldermask requirements • Electrical test complexity • Yield • Minimized environmental impact 4 of 65
  5. 5. Design for Manufacturability GuidelinesPanelizationSpecifications Standard Advanced ComplexPanel Sizes 16x18, 12x14, 12x18, 18x24, 16x26Number of layers 2 to 28 2 to 28 or higher 2 to 28 or higherLayer-to-layer +/- 0.004”registrationFoil types available CAC, Electrodeposited copperCopper foil ≥ 6% High Temperature Elongation (HTE) - inner layers onlyelongation Table 1 – Panel Size AvailabilityPanelization is the process of placing one or more Printed Circuit Boards (PCB’s) on amanufacturing panel and incorporating features to assist manufacturing (such as tooling holes,fiducials, coupons, resin vents, panel thieving, etc.). This is one of the highest impact factors inthe cost of a PCB.The panel area that is available for circuit boards and coupons is called the useable area. Theuseable area is measured as a percentage (total area for PCB’s divided by the total panel area).PCB’s are arranged in the useable area. Any area outside the useable area is designated fortooling to optimize manufacturing. A target panel utilization of greater than 75% is consideredcost effective material utilization. The following pages will outline the provisions and requirementsnecessary make the best use of the available area in a manufacturing panel. 18 inches Useable 22.50 inch es 24.0 inche s Panel Area 16.50” x 22.50” 16.50 inches Figure 1 - Typical 18 x 24 Panel 5 of 65
  6. 6. Design for Manufacturability GuidelinesRaw laminate is the single principal cost constituent of a multilayer PCB. Optimizing panelstructure around standard base materials while achieving maximum material utilization onstandard panel sizes can have a significant positive impact on multilayer board prices anddeliveries.There are three preferred panel sizes, 16x18 inches, 18x24 inches, and 21x24 inches. Largerpanel size typically provides the most effective cost per unit area processed. Other panel sizesare also available for special applications.The most effective material utilization will be achieved with PCBs or arrays of PCBS that theirfinished outline fit as efficiently as possible within the usable area of the panel. Test couponsmust be within the usable area. The customer may negotiate to have locating holes and/orbreakaway tabs for the insertion or surface mount equipment located outside the usable area.This is usually accomplished via the tab-routing process. Material utilization may be increased byemploying the scoring process. This process places grooves on opposite sides of the panelbetween boards for snapping the boards from the panel. This method permits boards can bebutted up against each other, eliminating the real estate for rout paths thereby allowing moreboards may be placed on the panel.For single and double-sided product, a 0.500-inch border is required around the periphery of thepanel for tooling purposes. For multilayer this allowance is 0.750 inches.Standard Panel SizesUse the following table to determine the maximum, single 1-up PCB that can fit into a panel.Panel sizes are sub-divided into “standard” (most common) and “optional” (custom)classifications. Type Panel Size Useable Area Double / Single Sided Multilayer Standard 16.00” X 18.00” 15.00” X 17.00” 14.50” X 16.50” Standard 18.00” X 24.00” 17.00” X 23.00” 16.50” X 22.50” Standard 21.00” X 24.00” 20.00” X 23.00” 19.50” X 22.50” Optional 12.00” X 14.00” 11.00” X 13.00” 10.50” X 12.50” Optional 12.00” X 18.00” 11.00” X 17.00” 10.50” X 16.50” Optional 16.00” X 26.00” 15.00” X 25.00” 14.50” X 24.50” Table 2 – Useable Panel AreaThere are three general modifications to a panel, which will reduce the available useable area.These modifications include: (1) Step-and-repeat requirements (2) Provisions for electroplating edge connectors (3) Coupon requirementsStep-and-RepeatThe term ‘step-and-repeat’ describes the process of reproducing successive images onto a panel.For PCBs without gold-plated edge contacts, the standard step-and-repeat spacing betweenparts is normally 0.100”. A typical lay-up is shown in Figure 03. 6 of 65
  7. 7. Design for Manufacturability Guidelines Figure 2 - Layout without Edge ConnectorsGold-Electroplated Edge Connectors For printed circuit boards with gold-plated edge connectors (a.k.a. tips, fingers, tabs), parts are usually arranged such that the edge connectors are either facing each other or opposite each other as in Figure 04. When edge connectors face each other, the space between the partoutlines should be at minimum of 0.400”. This allows space for extensions to join the connectors for electroplating and to allow room for a shearing operation to separate the pieces (seeWhen the boundaries opposite the edge connectors are facing each other, the space between theparts can be 0.150” (minimum 0.100”) since there is no gold plating required in this area.Maximum distance between buss bar connections 24”Minimum PCB thickness 0.032”Maximum PCB thickness 0.125”Maximum edge connector recess 4.0” (minimum allowable solution level) Table 3 - Edge Connector Restrictions 7 of 65
  8. 8. Design for Manufacturability Guidelines Plating Frame Maximum Distance 24.0” Plating Frame Printed Circuit Board Extenders Plating Bar Optional Plating Frame Plating Frame Maximum Distance 24.0” Printed Circuit Board Printed Circuit Board Plating Bar Figure 3 - Gold Plating Interconnection Components Printed Circuit Board 0.400” Typical Printed Circuit Board 5.50” Panel Width Back-to-Edge Printed Circuit Board Figure 4 - Layout - Edge Connectors For printed circuit boards with recessed gold-plated edge connectors, the same rules apply as those without recessed edge connectors with one exception. The greatest inboard gold-plated feature must not exceed 4.00” (see Figure 4). When the gold-plated edge connectors arerecessed greater than 4.00” a deep-tank process is required. This process is more expensive and time consuming. 8 of 65
  9. 9. Design for Manufacturability Guidelines 0.100” Usable Area of the Perimeter Minimum 2.500” Typical Printed Circuit Board 0.100”Minimum Printed Circuit Board Figure 5 - Lay-up with Recessed Edge ConnectorsControlled Impedance CouponsPrinted circuit boards with controlled impedance technology are processed with test coupons aspart of the lay-up. When a +/- 15 ohms or +/- 20% of nominal impedance tolerance is specified,we recommend using controlled geometry to control impedance (see page 32).This will free areaon the panel for parts since the coupons will not be needed. The coupon size and location isdependant on the number of layers and panel utilization. A possible arrangement is shown inFigure 6. 1.00” Coupon Controlled Impedance Coupon Printed Circuit Board Printed Circuit Board Printed 0.100” Circuit BoardMinimum Printed Circuit Board Printed Circuit Board Coupon Figure 6 – Controlled Impedance Coupon Placement 9 of 65
  10. 10. Design for Manufacturability GuidelinesControlled ImpedanceControl geometry to assure product conformance > 10%Control impedance to assure product ± 10%Controlled Impedance ModelingControlled impedance PCB’s, require specific constructions and tighter manufacturing controls.DAPC has tailored standard impedance equations to precisely calculate PCB constructions.Controlled GeometryControlled geometry boards have specified a thickness between certain layers and require noimpedance coupons. These constructions do not give much flexibility regarding the materialsused, and typically do not have many alternative constructions. DAPC will select the appropriatepre-preg and cores that satisfy the dielectric spacing, tolerance, and overall thicknessrequirements.SerializationSerialization is a traceability process for controlled impedance jobs. DAPC adds test coupons tothe panel to measure impedance with a TDR. When the impedance has been tested, the couponand PCB have a serial number printed on them. Serialization adds additional steps to themanufacturing process.100% TestingAll impedance coupons are 100% electrically tested per panel when specified by the customer.After comparison against specified values, the measurements are electronically stored.Multiple ImpedancesSome boards require multiple impedances on the same signal layer. DAPC is able to modifyimpedance coupons to accommodate such a request. The coupon will either be wider thannormal (one trace for each impedance feature) or a secondary coupon will be added. However,testing multiple impedances on a given signal layer is not recommended. Whenever possible,designate one target impedance value per layer.Characteristic ImpedanceThe characteristic impedance of a transmission line is dependent on the relationship of theconductor width, conductor thickness, dielectric thickness between conductor and ground-powerreference planes, and the dielectric constant of the dielectric medium.It is recommended that the designer contact us to discuss impedance needs during the initialdesign phase. This will enable mutual understanding of requirements and impact of materialcharacteristics, such as specific Dk (Dielectric Constants) and manufacturing processes, onneeded impedance targets and tolerances.The actual impedance may have to be tested via a small prototype build. This is often necessarywhen tight impedance tolerances are required, or in the case of small line widths and dielectricthicknesses, which are more sensitive to variations. A tolerance swing due to etching variationswill be more significant for a 0.005-inch line than for a 0.010-inch line, for example. Line width anddielectric thickness should be documented as reference only. This will allow us to make smalladjustments to both parameters in order to match impedance targets. Note: if a line widthmodification is necessary, it will only be accomplished globally. That is, all of the lines of the samewidth will be modified on a given layer. No modification will be made without prior consent of thecustomer. For impedance calculations, it is important to consider the Etch Factor, the effective 10 of 65
  11. 11. Design for Manufacturability Guidelinesreduction of the line width during the etching process. The exception to this is with boards with anAspect Ratio ≥ 4.5:1 or with boards ≥ 0.090 inch thick and an Aspect Ratio of ≥ 3:1. No EtchFactor needs to be considered in these cases.The recommended impedance tolerance is ±10%. A lesser tolerance is often achievable,especially with fully embedded Microstrip and Stripline structures. This requirement must bediscussed with us for appropriate focus.Layer Stack Up Table 4 – Available Material Types 11 of 65
  12. 12. Design for Manufacturability Guidelines Standard Material Tolerances THICKNESS TOLERANCE CLASS 0.0030” ± 0.0007” B 0.0040” ± 0.0007” B 0.0050” ± 0.0010” B 0.0060” ± 0.0010” B 0.0075” ± 0.0015” B 0.0080” ± 0.0015” B 0.0100” ± 0.0015” B 0.0120” ± 0.0015” B 0.0140” ± 0.0020” B 0.0210” ± 0.0020” C 0.0280” ± 0.0020” C 0.0470” ± 0.0030” C 0.0590” ± 0.0030” C Table 5 - Laminate (Core) Tolerances Purchased Specifications (IPC 4101) 0.0030” – 0.0075” single ply construction laminate AVAILABLE PRE-PREG THICKNESS RANGE 106 0.0015” – 0.0021” 1080 0.0025” – 0.0035” 2113 0.0035” – 0.0045” 2116 0.0045” – 0.0055” 7628 0.0065” – 0.0071” Table 6 – Pre-Preg TolerancesCopper Foil (Base Copper Weight): Coated copper layer on the board. It can be eithercharacterized by weight or thickness of the coated copper layer. See chart below. COPPER WEIGHT * THICKNESS (ounce) (mils) **0.25 0.35 **0.375 0.525 0.5 0.7 1 1.4 2 2.8 3 4.2 **4 5.6 Table 7 - Copper Foil Equivalent Thicknesses*Purchased specifications. Tolerance per IPC-MF-150F** Non standard stock 12 of 65
  13. 13. Design for Manufacturability GuidelinesTable 8 – UL Listing Card 13 of 65
  14. 14. Design for Manufacturability GuidelinesMultilayer Construction GuidelinesWhen designing multilayer constructions for PCBs that do not have controlled impedancerequirements, or other distinct specifications, the following guidelines should be used.Design balanced constructions that are symmetrical from the lay-up’s centre outward.Whenever possible, only one core thickness should be used.The maximum B-Stage opening between C-Stages is 0.021”.Note: Each outer layer is typically a signal layer built on 0.5-ounce copper.If the B-Stage opening is greater than 0.016” use filler cores.Multilayer Constructions1. Design multilayer boards with an even number of layers.2. If specifying the dielectric thickness when for example may be required for impedance reasons,the dimensions should be selected from available core or pre-preg thickness. Dielectricthicknesses made up of pre-preg depend on the type or the combination of pre-preg is suitableand of achievable dimensions and tolerances. It is beneficial to discuss special dielectricrequirements during the design stage if possible with your PCB vendor.3. Maintaining a balance lay-up in relation to the z-axis median of the board will assure minimumbow and twist. This balance includes the following: dielectric thickness of layer, copper thicknessof layers and its distribution and the location of circuit and plane layers. A higher number of layersnormally will mean an increase number of plane layers. It is preferred that planes be balancedaround the z-axis median line of the lay-up, and ideally located internal to the board. If acceptedmultilayer design rules are adhered to, boards will meet a maximum allowable bow and twistspecification of 0.010 inch per inch (1%) or better.4. Outer layer circuitry - circuit area and distribution between the front and back of the boardshould be balanced as closely as possible. The addition of plating thieving of low pattern densityof external plane area should be considered.5. Thickness tolerance - as the overall thickness of a multilayer board increases, the thicknesstolerance should also increase. A good rule is to specify a tolerance of +/- 10% of the overallthickness. Always indicate where the thickness measurement is to be taken. Examples: glass toglass at rail guides, over gold contacts, over solder mask, etc. 14 of 65
  15. 15. Design for Manufacturability GuidelinesBlind and Buried Via (BBV) BoardsGeneral descriptionLike through holes in a conventional multilayer board, blind and/or buried vias are plated holesthat facilitate connections between copper layers. However, unlike in a conventional multilayerboard, blind and buried vias allow circuits of non-planar topography to be connected. This is asignificant strategy in order to conserve circuit board real estate because it allows only requiredlayers to be connected.We use the following terminology to define different types of via interconnection:A through hole via has access to both external layers. Figure 7 – Through Hole Via 15 of 65
  16. 16. Design for Manufacturability GuidelinesA blind hole via does not pass through the entire board, and has access to only one externallayer. Figure 8 – Blind Via and Through Hole Via 16 of 65
  17. 17. Design for Manufacturability GuidelinesA buried via provides connection within inner layers, it has no access to the external layers. Figure 9 – Buried Via and Through Hole Via 17 of 65
  18. 18. Design for Manufacturability GuidelinesBlind and Buried Via Design Constraints • Core thickness 0.003 minimumNote: 0.5-ounce copper is required for BBV layers. Individual BBV layers will receive 0.0007 inchelectrolytic copper during the through-hole plating process, bringing the total copper thickness to0.0014 inch. • Minimum drill size 0.0079 with a maximum aspect ratio of 7:1 for blind/buried via substrates.Note: all BBV holes will be plugged with epoxy during subsequent lamination cycles. • The ability to register drilled holes to inner layers is impacted after each lamination cycle. • Minimum Annular Ring: drilled before first press cycle - 0.004 inch per side • Drilled after first press cycle - 0.004 inch per side • Drilled after second press cycle - 0.006 inch per side • Drilled after third press cycle - 0.009 inch per sideRequired information on drawings: • The hole chart must list plated through holes separately from the Blind and or Buried via holes. 18 of 65
  19. 19. Design for Manufacturability GuidelinesMicroviasMicrovias rulesProcess 1 - Standard Conformal Opening • Micro via diameter maximum - 0.003 inch minimum - 0.006 inch • Maximum aspect ratio (depth/diameter) 1:1 • Minimum outer layer pad dia. via diameter + 0.008 inch • Minimum landing layer pad dia. via diameter + 0.008 inch • Panel thickness maximum - 0.100 inch minimum - 0.030 • Annual ring > 0.004 inch for all above conditionsFilled ViasConductive and Non-conductive filled vias have several applications where filled vias may bebeneficial. Filled vias can improve routing density, can aid with electrical and thermalperformance, and can improve board assembly. These are general design rules for this process.Guidelines; • Board thickness 0.020 to 0.120 inch • Drill size 0.008 inch (min /0.020 inch (max.) • Copper thickness IPC class II • Outer layer features 0.004 inch minimum trace / 0.005 inch minimum trace 19 of 65
  20. 20. Design for Manufacturability GuidelinesConductive Features Specification Standard AdvancedInner layers:Minimum line width / ½ oz - 0.0035” / 0.0035” 0.003” / 0.003”spacing: 1 oz – 0.004” / 0.004” 0.003” / 0.003” 2 oz – 0.006” / 0.006” 0.005” / 0.005” 3 oz – 0.009” / 0.009” 0.008” / 0.008” 4 oz – 0.011” / 0.011” 0.010” / 0.010”Pad diameters: Add 0.010” to drilled hole Add 0.009” to drilled Tangency: diameter hole diameter Annular ring Drilled hole + 0.010” + 2 x Drilled hole + 0.008” +requirements: min A/R 2 x min AROuter layers:Minimum line width / 0.005” / 0.005” (for ½ ounce 0.003” / 0.003”spacing: foil)Pad Diameters: Tangency: Add 0.010” to drilled hole Add 0.009” to drilled diameter hole diameter Annular ring Drilled hole + 0.009” + 2 x Drilled hole + 0.008” +requirements: min A/R 2 x min ARNPTH-to-Copper for 0.010primary drill: Table 9 – Conductive Features General To increase interconnect reliability on the signal layers, DAPC recommends that all pad-to-trace intersections be tear dropped whenever the pad diameter minus the plated hole diameter is less than 0.020”. This process is designed to provide additional metal at the critical junction of a pad and a run. When an order is drilled and mis-registration occurs, it has been theorized that a long-term reliability issue can arise if the mis-registration occurs at the junction of the pad and the trace. Adding metal at this location helps ensure that an adequate connection is made and maintained. The tear dropping process involves adding secondary pads at the junction of an existing (primary) pad and a circuit run. These secondary pads are sized 0.002 inch smaller than the primary pads, and the centre is placed 0.003 inch away from the centre of the primary pad. This tooling is conducted using IPC standards for tear dropping and has proven to be highly reliable and effective. 20 of 65
  21. 21. Design for Manufacturability Guidelines Annular Ring Plated Hole Teardrop Trace Figure 10 – Standard Teardrop Plated HoleTangency Breakout Diameter 0.001” Annular Ring Minimum Circuit Drilled Hole Pad Area Diameter Figure 11- Annular Ring / Tangency / Breakout 21 of 65
  22. 22. Design for Manufacturability Guidelines Line Width Line Space Substrate Material Figure 12- Line Width & Spacing MeasurementDesigner Reference TableInternal Power / Ground LayersProvide a layer number and description on the artwork.Clearance pads must be a minimum diameter of 0.020” larger than the nominal finished hole size.When placing thermal pads:Size the outside diameter using this formula: OD = FHS + 0.020”(Minimum: OD = ID + 0.010”)Rotation of thermals and addition of spokes is customer dependantPreferred set would be: rotate each thermal 45° to the plane and add spokes that are 90° apartSpoke width: 0.010” (preferred) or 0.006” (minimum)To prevent exposed copper at board edge of routed panel, keep copper 0.010” away from thePCB’s perimeter.Minimum barrel of hole-to-copper spacing: 0.008” (see Figure 14)To prevent exposed copper at board edge of scored panel, keep copper at 0.025” away from thePCB’s perimeter Figure 13 - Avoid Thermal Isolation & Slivers of Copper 22 of 65
  23. 23. Design for Manufacturability GuidelinesDesigner Reference TableInternal Signal LayersPreferred trace / space: 0.004” / 0.004”Minimum trace / space: 0.003” / 0.003”Inner signal layers must have a positive polarityClearly label layer number and descriptionMinimum barrel of hole-to-copper spacing: 0.008” (see Figure 14)No thieving smaller than a 0.030” feature size is allowedRelieve all copper internal to part from route paths by at least 0.010”Provide thieving inside all open and breakaway areas, if permitted by the customer Figure 14 - Hole-to-copper spacingDesigner Reference TableOuter LayersPreferred minimum trace / space: 0.004” / 0.004”.Minimum trace / space: 0.003” / 0.003”.Keep all pad edges at least 0.050” from gold features or they will be gold platedOn the solder-side, leave a 0.200” x 0.400” area for DAPC to add a date code box, ID, UL logo,and cage code.Layout of circuitry on the board has a major influence on the way the panel actually plates. Try toavoid unbalanced copper area on the outer layers. Solitary traces will over plate, while isolatedholes will over plate to yield finished hole sizes under specificationsTo maximize plating distribution, allow DAPC to add square thieving to low-density areas on theouter layers (such as breakaways or substantial unused spaces within the PCB). For boards withedge connectors, there must be at least 0.050” of soldermask between the soldermask clearanceof the nearest via hole and the top of the edge connector area. If this spacing is violated, maskwill be extended onto the edge connector until 0.050” is achieved (see Figure 15) 23 of 65
  24. 24. Design for Manufacturability GuidelinesNickel/Gold Edge Connectors 0.050” Vias Figure 15 - Via-to-gold edge connector spacing 0.030” 0.050” Round Thieving Thieving Inside BGA/SMD Arrays Removed Per Request 0.030” 0.050” Low Density Circuit Area 0.020” Printed Circuit Board Feature Figure 16 - Round Thieving 24 of 65
  25. 25. Design for Manufacturability GuidelinesHoles and Slots Specification Standard Advanced Complex Holes: Minimum drilled hole 0.011” 0.008”, 0.006”, 0.004” diameter: Maximum drilled hole 0.250” diameter: Maximum Aspect ratio: 8:1 16:1 Plated hole diameter +/- 0.003” + 0.002” / - 0.002” tolerance: Drilled hole diameter +/- 0.0015” +/- 0.001” tolerance (NPT): Hole-to-hole location +/- 0.003” (0.008” +/- 0.002” (0.0065” accuracy: DTP) DTP) Micro Via 0.005” 0.003” – 0.008” Table 10 – Holes and SlotsGeneralWhenever possible, combine hole diameters that are within 0.002” of each other.Do not add holes that are unnecessary.Clearly indicate on the fabrication drawing if any holes or slots can be optionally plated.The ‘aspect ratio’ is a ratio of the length or depth of a hole to its pre-plated diameter.Plated Through HolesStandard diameter tolerance: +/- 0.003”.Minimum diameter tolerance: + 0.003” / -0.002”.Minimum backplane hole diameter tolerance: +/- 0.002”.Minimum hole edge-to-hole edge spacing: 0.015”.The tolerance for any via ≤ 0.018” in diameter will be + 0.003” / - nominal hole size.Plated SlotsMinimum size tolerance (length & width): +/- 0.005”.Minimum position tolerance: +/- 0.005”.Non-Plated Through HolesMinimum drilled hole diameter tolerance: +/- 0.0015”.Minimum second drill diameter tolerance: +/- 0.0015”.Tooling holes should be ≤ 0.250”. The preferred size is 0.125”.Non-plated holes with a diameter greater than 0.250” will be produced during the profile routingsequence (Size tolerance = +/- 0.005” and Position tolerance = +/- 0.005”).Holes with a diameter > 0.250” will be routed.Non-plated holes and slots will be second drilled whenever the required 0.0135” minimum featureclearance cannot be maintained.The positional tolerance of secondary drilled holes to datum ± 0.005”.Non-Plated Through SlotsNon-plated slots will be routed with length, width and positional tolerances of +/- 0.005”. 25 of 65
  26. 26. Design for Manufacturability GuidelinesMicro ViaMaximum panel size: 18” x 24”Routing, Bevelling and Scoring Specification Standard Advanced Routing: Edge-to-edge tolerance: +/- 0.010” +/- 0.008” Edge-to-datum hole tolerance: +/- 0.005” +/- 0.0035” Minimum internal radius: 0.031” 0.0155” Minimum external radius: None None Max. routed hole diameter 1.250” +/- 0.010” 1.250” +/- 0.005” and tolerance: Min. routed hole diameter and 0.250” +/- 0.005” 0.250” +/- 0.003” tolerance: Preferred router bits: 0.093” 1/32”, 1/8”, 0.040”, 0.050”, 1mm Scoring: Minimum web thickness: 0.004” Available scoring angles: 30° 20°, 45°, 60° Spacing between V-sore to 25 mils 20 mils copper Web thickness tolerance: +/- 0.005” +/- 0.003” Location tolerance: +/- 0.005” Jump score capability: Yes Edge bevelling: Available angles: 20°, 30°, 35°, 45° 15° - 180° Angle tolerance: +/- 2° Available depths: 0.015” to 0.075” Depth tolerance: +/- 0.010” Table 11 – Routing, Beveling and ScoringRoutingMinimum drilled datum-to-routed edge tolerance: +/- 0.005”.Minimum routed edge-to-routed edge tolerance: +/- 0.010”.NC Routed slots:Minimum length & width tolerance: +/- 0.005”.Minimum position tolerance: +/- 0.005”.Slots must show a radius at the top and the bottom.Preferred router bits: 0.093”, 0.062”Breakaway tab attachments should be spaced apart between 1.00” and 2.50”. 26 of 65
  27. 27. Design for Manufacturability Guidelines Printed Circuit Board Slots have rounded ends Breakaway Breakaway 1.00: - 2.50” Breakaway Tab Attachment Figure 17 - Breakaway Tab SpacingMinimum tolerance of internally routed features: +/- 0.005”.Minimum individually tooled size : 0.4” x 0.4” PCB.Provide at least 3 non-plated, diagonally placed tooling holes for pinning during profile routing.Minimum distance from tooling hole edge-to-feature edge: 0.015”.Relieve all copper internal to part from route paths by ≥ 0.025”.BevellingMaximum length of a bevelled edge: 18”.Minimum bevelled edge-to-opposite edge of PCB dimension: 2.5”.Minimum / maximum PCB thickness: 0.020” / 0.125”. Width Depth Angle Angle Figure 18 – Bevel DiagramEdge bevelling may be performed on the outer edge of the board, a recessed segment of theboard, or internal to the board. Inner layer plane layers must be recessed to avoid exposing the 27 of 65
  28. 28. Design for Manufacturability Guidelinesplane when the boards are bevelled. The following angles and depths may be achieved givensufficient board thickness:20 degrees by 0.070 inch depth +/-0.01530 degrees by 0.050 inch depth +/- 0.01045 degrees by 0.040 inch depth +/- 0.005Minimum / maximum bevel depth: 0.015” / 0.075”.Bevel angles available: 20, 30, & 45 degrees +/- 5 degrees.Maximum recessed bevel: 1”.Minimum space between gold edge connector and breakaway tab: 0.250”.ScoringMinimum / maximum panel thickness: 0.020” / 0.250”.Maximum panel size for scoring: 21” x 24”Minimum web thickness tolerance: +/- 0.005”.Score angle: 30 degrees (20 degrees available)Minimum web thickness: 0.004”.Traces should be ≥ 0.050” away from the score line centre on all outer and inner layers.Score line width: 1.15 times the depth.Scoring depth is typically 33% of material thickness.Jump Score: To achieve desired remaining thickness minimum distance of 0.250” for 0.062” thickboards, from scoring start point is requiredEdge MillingBoards may require edge milling to reduce the circuit board thickness to a specified thickness andtolerance. Typically this is done to allow the board to fit into a card guide when assembled.The milled edge is usually a “step” at the edge of the board. The depth of the step is variable from0.010” removed to 0.032” remaining. The width of the step is variable from 0.020” to 0.375”.Milling requirements should be limited to simple cuts i.e. two straight edges and simple corners.The path of the mil is limited to a 90 degree turns and internal radii are controlled by cutterdiameter (minimum 0.125” and common standard sizes). Double-sided milling is stronglydiscouraged as edge thickness accuracy is reduced.The finished thickness of the milled edge can be held to +/- 0.008” for a single sided milled edge.For a double-sided milled edge, the finished thickness can be held to +/- 0.010”. The width of thestep can be held to +/- 0.010”. Figure 19 - Edge Milling DiagramScoring Section 28 of 65
  29. 29. Design for Manufacturability GuidelinesThis process places grooves on opposite sides of a panel or between boards, for the purpose ofde-panellizing by snapping the boards from the panel. Since boards can be ‘butted up” againsteach other, more boards may be placed on the panel thereby reducing the cost of the board.Design GuidelinesScore locations need to be clearly identified on the drawing, with centreline of groove-featurereferenced. • The web thickness (material remaining between opposing grooves) must be specified. Typical web thickness is 0.008” to 0.014”. Minimum web thickness is 0.006”. A different web thickness may be specified within a panel, but not within a single score cut. • The groove angle should be specified. It is typically 30° however, 20° is also available. • The depth of the groove should not be specified; because it is not controlled, (the web thickness is controlled). Also, the centering between top and bottom should be specified. • To facilitate depanelization, grooves running to the edge of the panel are recommended. • The groove width for a typical 0.062” board with a 0.013” web is about 0.020” wide at the surface of the board. Image features need to be pulled back a minimum of 0.040” from the score line centre (image edge) for this board and web thickness. • Overall board thickness suitable for scoring is 0.030” to 0.125”. Figure 20 - Scoring Blade DiagramAchievable Tolerances:Web Thickness……………………………...+/-0.002”Edge to Edge………………………………..+/-0.005”Datum to Edge………………………………+/-0.008” 29 of 65
  30. 30. Design for Manufacturability GuidelinesSoldermaskSoldermask AvailabilityA variety of soldermasks have been selected to fill the needs of our customers. The following is adescription of the soldermasks currently available. The need for closer tolerances has driven theimplementation of Liquid Photoimageable (LPI) Soldermasks. Specification Standard Advanced LPI Soldermask: Semi-Gloss Matte Average thickness over 0.0005” trace: Registration tolerance: +/- 0.003” Spacing ( for mask 0.008” 0.007” between pads): Available colours: Green Clear, Blue, Red, Black Via Plugging: PSR 4000MP SR1000 Peel able Soldermask: MacDermid 9490 Table 12 – Soldermask AvailabilitySoldermask is a protective coating that shields selected areas of a PCB from oxidation, handling,and unwanted solder during assembly.When required, allow via plugging to be applied to one side of the board. If Hot Air SolderLevelling is the finish, plugging is preferred after the HASL process. Clearances will be providedfor all vias that are tented on the customer soldermask artwork, and the clearance size will be0.003” per-side over the drilled hole size (with a minimum diameter of 0.020”). Via Plu gging S ide Via LPI Solder Mask Non Via Plu gging Side LPI Soldermask (0.020”) Outer Layer Pad Outer Layer Pad Drilled Drilled Hole Hole 0.003” Acceptable:0.003” Preferred: to O/L 0.003” Figure 21 – Via Plugging 30 of 65
  31. 31. Design for Manufacturability GuidelinesGreen is the preferred soldermask colour.Soldermask allows a 0.003” web to be placed between pads in an SMD array, provided theminimum spacing between these pads is 0.007” (by design).Green soldermask allows a 0.003” web to be placed between pads in an SMD array, provided theminimum spacing between these pads is 0.007” (by design).To assure no soldermask on any pad in an SMD array, the minimum soldermask clearance for asurface mount pad is 0.002” per side (not applicable for panel sizes over 18” x 24”). As spacepermits, a clearance of 0.0025” per side is preferred. 0.003” 0.0025” S/M Web Clearance Green Soldermask (Individual Webs) Figure 22 - Soldermask SMD ClearancesAllow 0.030” per-side soldermask clearance for score lines.To prevent soldermask from going into and/or plugging a hole, soldermask clearance should be0.010” (0.005” per side) larger than the pad size on both sides of the board.The primary coating of LPI soldermask shall not be used to tent holes.Liquid Photoimageable (LPI) SoldermaskLiquid Photoimageable soldermask is considered the soldermask of choice for most circuit boardproduct due to its high resolution, excellent electrical properties, and compatibility with surfacemount technology.Note: If pads are closer than the minimum, spacing described above, areas between should befree of soldermask, or the hold-down reliability will not be 100%.The strength of soldermask adhesion over gold plating depends on the type of soldermask, typeof gold, and the end-user processing conditions. It is recommended that the designer contact usbefore finalizing design. In certain cases, via plugging on BGA side may be required for tight pitchBGA with electrolytic gold.Tenting of Via Holes with SoldermaskVia capping with screened resistHole “capping/tenting” is available through the via cap process. On boards coated with liquidPhotoimageable mask, the vias can be screened with an epoxy or acrylic soldermask material, 31 of 65
  32. 32. Design for Manufacturability Guidelines creating a cap over the hole. Artwork modifications necessary for processing are performed as part of the initial tooling. A separate design file must be provided by the customer, which includes only those vias which are to be capped. The customer needs to provide master pad soldermask and via fills, i.e. Soldermask and via pads that are the same size as the outer layer pads. Via capping design constraints The maximum finished hole size for via capping is 0.020” diameter (preferred drill diameter 0.021 inch) Generally, the non-test vias are capped on the topside of the board. Thermal (epoxy) via caps will have a raised surface of approximately 0.0017” +/-0.004” inch above the outer layer copper pad. This is to provide the via hole being capped is not plated shut or plugged with HASL (solder). In this case, due to trapped air between the via cap and plug, the via cap may “dome” during the cure process, thus creating height 0.0035”. UV (acrylic) via cap will have a raised surface of approximately 0.0019” +/-0.0004” inch above the outer layer copper pads. Unlike Thermal (epoxy), UV (acrylic) is not influenced by plated or HASL (solder) plugged holes, therefore the via cap height will remain constant. Note: via cap height thickness measurements may include HASL (solder) and/or permanent soldermask thickness. For product that receives either immersion silver or tin, UV (acrylic) via cap material must be used and applied after the surface finish. Legend MarkingSpecification Standard Advanced ComplexLegend: Epoxy Epoxy EpoxyColours: White Yellow, Black Custom ColoursSmallest line width: 0.006” 0.005” 0.004”Location accuracy: +/- 0.010” +/- 0.005” +/-.003” Table 13 - Legend Marking Specifications To ensure all letters, numbers, and figures are legible on the finished board, character line widths should be greater than 0.006” and at least 0.030” high. Space letters at least 0.008” apart so they don’t bleed together. No legend nomenclature should overlap a copper pad or plane area. This is especially important for surface mount pads and fiducials. White is the standard legend ink colour. Use the fabrication print notes to specify special features to be screened onto the board. All legend should be kept 0.003” (min) away from soldermask clearance. Nomenclature Letter size: minimum 0.006” line width (screened nomenclature) 0.004” for Photoimageable. Recommended Letter Sizes: Line Width Height and Width 0.004” (LPI) 0.020” 0.005” (LPI) 0.025” 0.006” 0.030” 0.008” 0.035” 0.010” 0.040” Note: nomenclature placed over parallel or heavy copper traces may have poor legibility. 32 of 65
  33. 33. Design for Manufacturability GuidelinesColour: white (epoxy) preferred, Yellow (epoxy), Black and White (Liquid Photoimageable Ink(LPI) is also available).Nomenclature over solder (HASL) will have poor adherenceNomenclature placed over bare copper before HASL and immersion silver/tin will have anapparent copper “halo” after the HASL or Immersion Silver/Tin. Artwork needs to be modified if itis not acceptable to the customer. 33 of 65
  34. 34. Design for Manufacturability GuidelinesSurface Finishes Table 14 – Surface Finish Comparison 34 of 65
  35. 35. Design for Manufacturability GuidelinesTable 15 – Surface Finish Reference Guide 35 of 65
  36. 36. Design for Manufacturability GuidelinesElectrical Test Specification Standard Advanced Electrical test capabilities: Pitch: 0.020” 0.016”, 0.010” Fixture types: Flying Probe Flying Probe Test voltages available: 10 - 500 volts 10 - 500 volts Resistivity testing: Open resistance: 20 Ω 5Ω Short resistance: 10 MΩ minimum 25 MΩ Netlist capability: Yes ( Gerber netlist IPC D 356 or Mentor neutral extraction ) file reference Hi-pot testing: 500 to 1000 volts 500 to 1000 volts Controlled impedance: 10% ± 5% Table 16 – Electrical Test ParametersElectrical testing ensures electrical continuity & isolation of all nets. As the designer, keep in mindthe following parameters:Continuity TestAvailable Continuity Test Specifications:Continuity: 5 to 500Ω.Isolation: 2 to 100 MΩ.Voltage: 10 to 500VPreferred Continuity Test Specifications:Continuity: 20Ω.Isolation : 10 MΩ.Voltage : 100 V.Netlist ProgramsFor electrical testing, supply a netlist file from which the required test program will be derived.This should be in IPC-D-356 format or as a Mentor Neutral file.If a netlist isn’t supplied, one will be generated from the Gerber data.All test points should be in the netlist.Hi-Pot TestAvailable Hi-Pot Test Specifications:Voltage: 500 to 1000 V DC.Duration: 2 to 30 sec.Preferred Hi-Pot Test Specifications:Voltage: 500 V.Duration: 2 sec.Three main test parameters are of interest to customers:Test Voltage - the amount of power applied to the circuit for testing.Continuity Resistance - the maximum resistance allowable for a circuit. Any higher resistanceindicates a possible open circuit. 36
  37. 37. Design for Manufacturability GuidelinesIsolation Resistance - the minimum resistance allowable between separate electrical entities. Anylower resistance indicates a possible short. Testable settings for these parameters are systemdependant.PCB Data Requirements Customer Data Must README.TXT file , Legible fabrication file , Drill (NC) file , Include: Aperture list , All Gerber Files , CAD netlist test data Compression: ZIP, TAR-UNIX Data Format: ODB ++, RS-274-X, RS-274-D with aperture list Drill File: EXCELLON Fabrication Drawing: HPGL, DXF or PDF format Netlist: IPC-D-356 or Mentor Neutral Table 17 – Data Requirements Customer Data Must Include: A README.TXT file (See table 10) A legible fabrication print files (see Figure 33). A drill (NC) file. An aperture list file. No hard copies. One for all Gerber files. Rotation, shape, and size of all features must be clearly defined. All Gerber files CAD netlist test data. For a first time order fabrication specification must be sent. 37
  38. 38. Design for Manufacturability Guidelines Critical outline Hole chart that dimensions includes symbol, hole size, qty, plate Legible symbols or no plate, and for all hole sizes tolerance Notes 1) 2) Fabrication 3) drawing notes Dielectric Title block that dimensions and includes part #, stack-up order revision #, tolerance block, date. Figure 23 - Fabrication Drawing RequirementsNOTE: Accurate PCB data is essential to manufacture a perfect PCB. It is important that theblueprint revision, film revision, and drill tape revisions all agree, and that the part numbers oneach are identical. Also, any special instructions should be instructed in the README.TXT file. Preferred AcceptableCompression ZIP, RAR PKARC, TARData Format ODB ++ RS-274-X, RS-274-D (GERBER) plus an Aperture ListDrill File EXCELLON GERBERFabrication Drawing HPGL, DXF, AUTOCAD, PDF POSTSCRIPTNetlist IPC-D-356 MENTOR NEUTRAL FILE Table 18 – File Formats 38
  39. 39. Design for Manufacturability GuidelinesFile Name: README.TXTFormat: ASCII, or MS/WordContents: Company name Division name (and / or location) List of files in the package Board Part Number and Revision Purpose of the submittal: QUOTATION and/or PRODUCTION? Technical Contact (name and best times to call) Phone number Fax number EMAIL address (If available) Special Instructions Table 19 – Preferred Readme File ContentsCommon Data IssuesTwo types of data issues are frequently encountered: critical and non-critical. Critical data issuescan be substantial enough to stop the tooling process, while non-critical data issues simply resultin additional edits that need to be performed. The following lists present the most commonerrors. Minimization of these issues will decrease tool generation time.Critical ProblemsBad Compression (cannot unzip).Missing FAB prints of files.Formats not recognized.FAB prints are not legible.No README.TXT file.Information does not match.Missing Gerber files.Outside DAPC manufacturing capabilities.Missing Drill Files.Missing Aperture List.Missing “D” codes.Unclear aperture listRevisions do not match.Non-Critical ProblemsNetlist not supplied.No README.TXTDesign, as supplied, violates the OEM provided specifications / documentation?Design, as supplied, violates the Contract Assemblers provided specifications?Violations on rules that improve yield. 39
  40. 40. Design for Manufacturability GuidelinesTable 20 – Design Capabilities 40
  41. 41. Design for Manufacturability GuidelinesFigure 24 – PCB Manufacturing Process 41
  42. 42. Design for Manufacturability GuidelinesOuter Layer Plating Process Pattern Plating Process Basic Laminate Expose Develop Plate Copper Clad Resist Photo Image Copper & Tin Laminate Strip Etch the Strip Resist Copper the Tin Strip - Etch - Strip Panel Plate Process Basic Plate Additional Laminate Expose Photo Develop Etch & Strip Copper Clad Copper Resist Image Image Laminate Figure 25 – Outer Layer Plating Processes1. Pattern PlateDAPC fabricates all printed circuit boards with the pattern plating process. This process hasmajor advantages in that only the base copper is required to be etched. This process yields afiner, better defined line. One possible disadvantage is the variations in track height due tosurface density.2. Panel PlateThis plating fabrication method eliminates most of the copper plating distribution issues but nowthe base foil must be etched. This makes maintaining fine line definition and consistency difficultto maintain. 42
  43. 43. Design for Manufacturability GuidelinesThe allowance for etching of plated designs is as follows: Typical Minimum Reduction in Copper Weight design line line width from width nominal 0.5 ounce 0.0007” 0.004” 1.0 ounce 0.0014” 0.005” 2.0 ounce 0.0028” 0.008” Table 21 – Etch LossInner Layer Process Basic Laminate Expose Develop Etch Copper Strip Copper Clad Resist Photo Image Which Resist Laminate Polymerized the Resist Develop - Etch - Strip Figure 26 – Inner Layer Process 43
  44. 44. Design for Manufacturability GuidelinesGlossary of TermsAActivating: A treatment that renders nonconductive material receptive to Electroless deposition.Active Components: Semiconductor devices, such as transistors and diodes that can change itsbasic characteristics in a powered electrical circuit, such as amplifiers and rectifiers.Additive Process: A process for obtaining conductive patterns by the selective deposition ofconductive material on clad or unclad base material.Analog Circuit: An electrical circuit that provides a continuous quantitative output as a responsefrom its input.Annular Ring: The width of the conductor pad surrounding a drilled hole.Aperture Information: This is a text file describing the size and shape of each element on theboard. These are also known as the D-code list. These lists are not necessary if your files aresaved as Extended Gerber with embedded Apertures (RS274X)Array: A group of elements or circuits (or circuit boards) arranged in rows and columns on a basematerial.Artwork: Printed circuit design. An accurately scaled configuration used to produce the artworkmaster or production master.Artwork Master: The photographic film or glass plate that embodies the image of the PCBpattern, usually on a 1:1 scale.Aspect Ratio: The ratio of the board thickness to the smallest-hole diameter of the printed circuitboard.Assembly: A number of parts, subassemblies, or any combination thereof joined together.Assembly File: A drawing describing the locations of components on a PCB.Automated Optical Inspection (AOI): Visual inspection of the circuit board using a machinescanner to assess workmanship quality.Automated Test Equipment (ATE): Equipment that automatically tests and analyzes functionalparameters to evaluate performance of the tested electronic devices. 44
  45. 45. Design for Manufacturability GuidelinesBBBT: Bare Board Test.B-Stage Material: Sheet material impregnated with a resin cure to an intermediate stage (Bstage resin) Prepreg is the preferred term.B-Stage Resin: A thermosetting resin that is in an intermediate state of cure.Backplanes & Panels: Interconnection panels onto which printed circuits, other panels, orintegrated circuit packages can be plugged or mounted. Typical thickness is 0.125” – 0.300”.Backup Material: A layer composed of phenolic, paper composite, or aluminium foil-clad fibrecomposite used during fabrication to prevent Burrs and to protect the drill table.Ball Grid Array (BGA): A SMD package in which solder ball interconnects cover the bottomsurface of the package.Bare Board: An unpopulated PCB.Barrel: The cylinder formed by plating through a drilled hole.Base Copper: The thin copper foil portion of a copper-clad laminate for PCB’s. It can be presenton one or both sides of the board.Base Copper Weight: see Copper FoilBase Laminate: The dielectric material upon which the conductive pattern may be formed. Thebase material may be rigid or flexible.Base Material: The insulating material upon which a conductive pattern may be formed. It maybe rigid or flexible or both. It may be a dielectric or insulated metal sheet.Bed-of-nails Fixture: A test fixture consisting of a frame and a holder containing a field of spring-loaded pins that make electrical contact with a planar test object (i.e. a PCB).Bevel: An angled edge of a printed board.Bleeding: A condition in which a plated hole discharges process materials of solutions from voidsand crevices.Blind Via: A via hole from an external layer to an internal layer. It is copper plated to enable it toconduct current, but it does not penetrate the board from top to bottom.Blister: A localized swelling and separation between any of the layers of a laminated basematerial, or between base material and conductive foil. It is a form of delamination.Blow Hole: A solder joint void caused by outgassing of process solutions during thermal cycling. 45
  46. 46. Design for Manufacturability GuidelinesBoard Thickness: Standard base thickness is 1/16 which is also called out as .062 or .059.Other standard sizes are 0.031, 0.093, 0.125 and 0.256. Typical tolerance is 10% of the giventhickness. We can generally make any other thickness.Book: A specified number of stacks of Prepreg plies which are assembled for Curing in alamination press.Bond Strength: The force per unit area required to separate two adjacent layers of a board by aforce perpendicular to the board surface.Bow and Twist: The deviation from flatness of a board characterized by a roughly cylindrical orspherical curvature such that if the board is rectangular its four corners are in the same plane.Breakdown Voltage: The voltage at which an insulator or dielectric ruptures, or at whichionization and conduction take place in a gas or vapour.Bridging, Electrical: The formation of a conductive path between two insulated conductors suchas adjacent traces on a circuit board.Built-In Self Test: An electrical testing method that allows the tested devices to test itself withspecific added-on hardware.Buried Via: A via hole between internal layers that electrically conducts (by a copper platingprocess) a current from layer to layer, it does not extend to the surface of the printed board.Burr: A ridge left on the outside copper surface after drilling.CCAD: See Computer Aided Design.CAM: See Computer Aided Manufacturing.CAM Files: The files used for manufacturing PCB including Gerber file, NC Drill file andAssembly Drawings.CEM: A punchable material (paper) used in single-sided boards but not suited for plated through-holes. CEM stands for composite epoxy material.C-Stage: The condition of a resin polymer when it is solid state with high molecular weight.Capacitance: The property of a system of conductors and dielectrics that permits storage ofelectricity when potential difference exists between conductors.Centre-to-Centre Spacing: The nominal distance between the centres of adjacent features ortraces on any layer of a printed circuit board. Also known as “pitch”.Ceramic Ball Grid Array (CBGA): A ball grid array package with a ceramic substrate. 46
  47. 47. Design for Manufacturability GuidelinesChamfer: A broken corner to eliminate an otherwise sharp edge.Characteristic Impedance: A compound measurement of the resistance, inductance,conductance and capacitance of a transmission line expressed in ohms. In printing wiring itsvalue depends on the width and the thickness of the conductor, the distance from the conductorto ground plane(s), and the dielectric constant of the insulating media.Chase: The aluminium frame used in screening inks onto the board surface.Check Plots: A scaled paper or Mylar image of the database after placement and routing havebeen completed.Chip-on-Board (COB): A configuration in which a chip is directly attached to a printed circuitboard or substrate by solder or conductive adhesives.Chip: The individual circuit or component of a silicon wafer, the leadless form of anelectronic component.Circuit: The interconnection of a number of devices in one or more closed paths toperform a desired electrical or electronic function.Circuit Board (PCB/ECB): The general term for a printed or etched circuit board. Itincludes single, double, or multiple layer boards, both rigid and flexible.Circuitry Layer: A layer of a printed board containing conductors, including ground andvoltage planes.Clad or Cladding: A relatively thin layer or sheet of metal foil that is bonded to alaminate core to form the base material for printed circuit boards.Cleanroom: A room in which the concentration of airborne particles is controlled tospecified limits.Clearances: A clearance (or isolation) is a term to describe the space frompower/ground layer copper to through hole. To prevent shorting, ground and power layerclearances need to be .023”larger then the finish hole size for the inner layers. Thisallows for registration, drilling, and plating tolerances.Coating: A thin layer of material, conductive, magnetic or dielectric, deposited on a substancesurface.Coefficient of Thermal Expansion (CTE): The ratio of dimensional change of an object to theoriginal dimension when temperature changes, expressed in %/ºC or ppm/ºC.Component: An electronic device, typically a resistor, capacitor, inductor, or integrated circuit(IC), that is mounted to the circuit board and performs a specific electrical function.Component Hole: A hole used for the attachment and electrical connection of a componenttermination, such as a pin or wire to the circuit board.Component Side: The Side of a PCB on which most of components are mounted. Also calledthe “top side”. 47
  48. 48. Design for Manufacturability GuidelinesComputer-Aided Design (CAD): A software program with algorithms for drafting and modeling,providing a graphical representation of a printed board’s conductor layout and signal routes.Computer-Aided Manufacturing (CAM): The use of computers to analyze and transfer anelectronic design (CAD) to the manufacturing floor.Computer-Integrated Manufacturing (CIM): Software that takes assembly data from a CAD orCAM package and, using a pre-defined factory modeling system, outputs routing of componentsto machine programming points and assembly and inspection documentation.Conductor: A thin layer conductive area on a PCB surface or internal layer usually composed oflands (to which component leads are connected) and paths (traces).Conductor Base Width: The conductor width at the plane of the surface of the base material.Also see Conductor Width.Conductor-to-Hole Spacing: The distance between the edge of a conductor and the edge ofhole.Conductor Spacing: The distance between adjacent edges (not centreline to centreline) ofisolated conductive patterns in a conductor layer.Conductor Thickness: The thickness of the conductor including all metallic coatings.Conductor Width: The observable width of the pertinent conductor at any point chosen atrandom on the printed circuit board.Conformal Coating: An insulating protective coating that conforms to the configuration of theobject coated and is applied on the completed board assembly.Connector Area: The portion of the circuit board that is used for providing electrical connections.Contaminant: An impurity or foreign substance whose presence on printed wiring assembliescould electrolytically, chemically, or galvanically corrode the system.Continuity: An uninterrupted flow of electrical current in a circuit.Controlled Impedance: See Characteristic ImpedanceCoordinate Tolerancing: A method of tolerancing hole locations in which the tolerance isapplied directly to linear and angular dimensions, usually forming a rectangular area of allowablevariation. Also see, Positional Limitation Tolerancing and True Position Tolerance.Copper Foil (Base Copper Weight): Coated copper layer on the board. It can be eithercharacterized by weight or thickness of the coated copper layer. For instance, 0.5, 1 and 2ounces per square foot are equivalent to 0.0007, 0.0014 and 0.0028 inch thick copper layers.Copper (finished copper): This is how much copper your board will have on its surface. It isthe copper foil thickness, plus plated copper, minus surface preparation. It is given in oz/per sqfoot. 1 oz=a minimum of .0012-.0014” thickness 48
  49. 49. Design for Manufacturability GuidelinesCopper Invar Copper: A multilayer metal alloy of a specific proportion, laminated togetherwithout the use of an insulating adhesive, thereby retaining a thermal and electrical conductiveproperty.Core Thickness: The thickness of the laminate base without copper.Corrosive Flux: A flux that contains corrosive chemicals such as halides, amines, inorganic ororganic acids that can cause oxidation of copper or tin conductors.Cosmetic Defect: A defect such as a slight change in its usual colour that doesn’t affect aboard’s functionality.Cover Lay, Cover Layer, Cover Coat: Outer layer(s) of insulation material applied over theconductive pattern on the surface of a printed circuit board.Crazing: A condition existing in the base material in the form of connected white spots or“crosses” on or below the surface of the base material, reflecting the separation of fibres in theglass cloth and resin material.CTE: Coefficient of thermal expansion. The measure of the amount a material changes in anyaxis per degree of temperature change.Curing: The irreversible process of polymerizing a thermosetting epoxy in a temperature-timeprofile.Curing Time: The time needed to complete curing of resin at a certain temperature.Current Carrying Capacity: The maximum current which can be carried continuously, underspecified conditions, by a conductor without causing degradation of electrical or mechanicalproperties of the printed circuit board.Cut lines: The cut line is going to be used to program the router path and it represents the boardoutside edge.DDFSM: Dry Film Solder Mask. Coating material (dry-film resist) applied to the printed circuitboard via a lamination process to protect the board from solder or plating.Date Code: This will have the year and week of manufacture of the board. It can be etched onthe board or part of the silkscreen.Datum Reference: A defined point, line, or plane used to locate the pattern or layer formanufacturing, inspection, or for both purposes.Deburring: Process of removing burrs after drilling.Defect: Any non-conformance to specified requirements by a unit or product. 49
  50. 50. Design for Manufacturability GuidelinesDefinition: The accuracy of reproduction of pattern edges, especially in a printed circuit relativeto the original mater pattern.Delamination: A separation between any of the layers of the base of laminate or between thelaminate and the metal cladding originating from or extending to the edges of a hole or edge ofboard.Design Rule: Guidelines that determine automatic conductor routing behaviour with respect tospecified design parameters.Design Rule Checking: The use of a computer program to perform continuity verification of allconductor routing in accordance with appropriate design rules.Desmear: The removal of friction-melted resin and drilling debris from a hole wall.Develop: An imaging operation in which unpolymerized (unexposed) photoresist is dissolved orwashed away to produce a copper board with a photoresist pattern for etching or plating.Dewetting: A condition which occurs when molten solder has coated a surface and thenrecedes, leaving irregular shape mounds of solder separated by areas covered with thin solderfilm; base material is not exposed.Die: Integrated circuit chip as diced or cut from a finished wafer.Die Bonder: The placement machine bonding IC chips onto a chip-on-board substrate.Die Bonding: The attachment of an IC chip to a substrate.Dielectric: An insulating medium between conductors.Dielectric Constant: Is the ratio of permittivity of the material to that of a vacuum (referred to asa relative permittivity).Differential Impedance: Refers to the impedance of a pair of conductors when driven in adifferential mode, that is, when the conductors are driven by signals that have opposite polarityedges.Digitizing: The converting of feature locations on a flat plane to a digital representation in X-Ycoordinates.Dimensional Stability: A measure of the dimensional change of a material that is caused byfactors such as temperature changes, humidity changes, chemical treatment, and stressexposure.DIP: Dual in-line package with two rows of leads from the base in standard spacing between theleads and row.Double-Sided Assembly: PCB assembly with components on both sides of thesubstrate.Double-Sided Board: A circuit board with conductive patterns on both sides. 50
  51. 51. Design for Manufacturability GuidelinesDrawing or Print: This usually includes a drawing of the board outline with symbolsmarking individual drill sizes and corresponding board locations, dimensions, and anyother pertinent manufacturing information unique to the board (copper weight, boardthickness, stack-up specifics, etc.)Drill file (Excellon Drill File): It will have x and y coordinates with tool sizes viewable inany text editor. It is the file that governs your finished hole sizes.Drilling: The act of forming holes (vias) in a substrate by mechanical or laser means.Drills, Circuit Board: Solid carbide cutting tools with four facet points and two helical flutesdesigned specifically for the fast removal of chips in extremely abrasive materials.Dry - Film Resists: Coated photosensitive film on the copper foil of PCB using photographicmethods. They are resistant to electroplating and etching processes in the manufacturingprocess of PCB.Dry Film Solder Mask: A solder coating material applied to the PCB, through alamination process to protect the board from solder or plating.DRC: Design rule check.EEdge Bevel: A bevel operation performed on edge connectors to improve their wear and ease ofinstallation.Edge-Board Connector: A connector designed specifically for making removable and reliableinterconnection between the edge board contacts on the edge of a printed board and externalwiring.Edge Connector: A connector on the circuit-board edge in the form of gold plated pads or linesof coated holes used to connect other circuit board or electronic device.Edge Clearance: The smallest distance from any conductors or components to the edge of thePCB.Edge Dip Solderability Test: A solderability test performed by taking a specially-preparedspecimen, fluxing it with a non-activated rosin flux, and then immersing it into a pot of moltensolder at a pre-determined rate of immersion for a pre-determined dwell time, and thenwithdrawing it at a pre-determined rate.Electrical Test (1 sided / 2/sided): Testing is primarily to test for opens and shorts.Electroless deposition: The chemical coating of a conductive material onto a base materialsurface by reduction of metal ions in a chemical solution without using electrodes compared toelectroplating. 51
  52. 52. Design for Manufacturability GuidelinesElectroless Copper: A thin layer of copper deposited on the plastic or metallic surface of a PCBfrom an auto-catalytic plating solution (without the application of electrical current).Electroplating: The electrochemical deposition of reduced metal ions from an electrolyticsolution onto the cathode by applying a DC current through the electrolytic solution between twoelectrodes, cathode and anode, respectively.Entry Material: A thin layer of material composed of phenolic, aluminium foil, or paper that isplaced on top to the panel prior to drilling, to improve drill accuracy and prevent burrs and dents.Epoxy: A family of thermosetting resins. Epoxies form a chemical bond to many metal surfaces.Epoxy Smear: Epoxy resin that has been deposited on edges of copper in holes during drillingeither as uniform coating or in scattered patches. It is undesirable because it can electricallyisolate the conductive layers from the plated-through-hole interconnections.ESR: Electro-statically applied Solder Resist.Etch: Chemical removal of metal (copper) to achieve a desired circuit pattern.Etch Factor: The ratio of the depth of etch (conductor thickness) to the amount of lateral etch(undercut).Etchback: The controlled removal of all components of the base material by a chemical processacting on the sidewalls of plated-through holes to expose additional internal conductor areas.Etching: The process of removing unwanted metallic substances via chemical means.Even Mode Impedance: The impedance of a single line in a coupled-line pair when a common-mode signal drives both conductors within the pairFFiducial: Etched features or drilled hole used for optical alignment during assembly operations.Film Artwork: A positive or negative piece of film containing a circuit, soldermask, ornomenclature pattern.Fine Pitch: Fine pitch is more commonly referred to surface-mount components with a lead pitchof 25 mils or less.Finger: A gold-plated terminal of a card-edge connector. Also see Gold Finger.Files Gerber: Industry standard format for files used to generate artwork necessary forcircuit board imaging. 52

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