Analysis of Transistor Sizing
and Folding Effectiveness to
    Mitigate Soft Errors
                  Thiago Rocha de Assi...
Outline
                      Outline
Introduction
Single Event Effect



 •    Introduction
 •    Single Event Effect
 • ...
Introduction
              Introduction
              Single Event Effect
              3D NMOSFET Device
              Io...
Motivation & Objective
Outline
Introduction: Motivation & Obj.
Methodology



  • Motivation
         – Necessity of apply...
Methodology
Introduction: Motivation & Obj.
Methodology
Sources of Radiation




                                         ...
Sources of Radiation
Methodology
Sources of Radiation
SAA


       “Radiation is defined as energy in transit in the form ...
SAA
Sources of Radiation
SAA
Radiation Effects in IC




                                           7
                    ...
Radiation Effects in IC
SAA
Radiation Effects in IC
Single Event Effects




  • Transient vs. Permanent Errors
  • Perman...
Radiation Effects in IC
 SAA
 Radiation Effects in IC
 Single Event Effects


      Total Ionizing Dose                 Di...
Single Event Effect
                  Introduction
                  Single Event Effect
                  3D NMOSFET Devi...
Single Event Effect
  Radiation Effects in IC
  Single Event Effect
  3D NMOSFET Device


• Single Event Effect
   – The S...
3D NMOSFET Device
                Introduction
                Single Event Effect
                3D NMOSFET Device
     ...
3D NMOSFET Device
Single Event Effect
3D NMOSFET Device
3D NMOSFET vs. PTM L54




           Region        Width (x)    W...
3D NMOSFET Device
Single Event Effect
3D NMOSFET Device
3D NMOSFET vs. PTM L54


                                  Gate   ...
3D NMOSFET vs. PTM L54
 3D NMOSFET Device
 3D NMOSFET vs. PTM L54
 Ion Profile




Vs=Vb= 0 V
Vgs= 1.2V




              ...
3D NMOSFET vs. PTM L54
    3D NMOSFET Device
    3D NMOSFET vs. PTM L54
    Ion Profile



Vs=Vb= 0 V
Vgs= 1.2V



Thresho...
Ion Profile
              Introduction
              Single Event Effect
              3D NMOSFET Device
              Ion...
Ion Profile
 3D NMOSFET vs. PTM L54
 Ion profile
 Ion profile – Alpha Particle



• The Environment (LERAY, 2004)
   • For...
Ion Profile – Alpha Particle
 Ion Profile
 Ion Profile – Alpha Particle
 Ion Profile - Copper



• Alpha Particle (He nucl...
Ion Profile – Alpha Particle
 Ion Profile
 Ion Profile – Alpha Particle
 Ion Profile - Copper



• Alpha Particle (He nucl...
Ion Profile - Copper
 Ion Profile – Alpha Particle
 Ion Profile – Copper
 Ion Profile - Krypton



• Copper (Cu)




     ...
Ion Profile - Copper
   Ion Profile – Alpha Particle
   Ion Profile – Copper
   Ion Profile - Krypton



 • Copper (Cu)


...
Ion Profile - Krypton
Ion Profile – Alpha Particle
Ion Profile – Krypton
Ion Profile




         (ZIEGLER, SRIM 2008, 200...
Ion Profile - Krypton
 Ion Profile – Alpha Particle
 Ion Profile – Krypton
 Ion Profile



• Krypton (Kr)

 Radial Distrib...
Ion Profile
 Ion Profile – Alpha Particle
 Ion Profile
 Physical Models



• Impact details
  – Hit the transistor drain c...
Physical Models
 Ion Profile – Alpha Particle
 Physical Models
 Transistor Sizing



• Models used during simulations
  •S...
Transistor Sizing
                 Introduction
                 Single Event Effect
                 3D NMOSFET Device
  ...
Transistor Sizing Technique
Physical Models
Transistor Sizing Technique
Transistor Sizing Electric Evaluation


The idea b...
Transistor Sizing Electric Evaluation
Transistor Sizing Technique
Transistor Sizing Electric Evaluation
3D NMOSFET Device
...
Device Under Test
Transistor Sizing Electric Evaluation
Device Under Test
Results: Alpha Particle




                    ...
Device Under Test
Transistor Sizing Electric Evaluation
Device Under Test
Results: Alpha Particle


                      ...
Results: Alpha Particle
                       Device Under Test
                       Results: Alpha Particle
          ...
Results: Alpha Particle
                       Device Under Test
                       Results: Alpha Particle
          ...
Results: Alpha Particle
  Device Under Test
  Results: Alpha Particle
  Conclusion: Alpha Particle

Increasing the output ...
Conclusion: Alpha Particle
Results: Alpha Particle
Conclusion: Alpha Particle
Results: Heavy Ion (Cu & Kr)




 • Asymmetr...
Results: Heavy Ion (Cu & Kr)
                       Conclusion: Alpha Particles
                       Results: Heavy Ion ...
Results: Heavy Ion (Cu & Kr)
                  Conclusion: Alpha Particles
                  Results: Heavy Ion (Cu & Kr)
...
Results: Heavy Ion (Cu & Kr)
    Conclusion: Alpha Particles
    Results: Heavy Ion (Cu & Kr)
    Conclusion: Heavy Ion (C...
Conclusion: Heavy Ion (Cu & Kr)
Results: Heavy Ion (Cu & Kr)
Conclusion: Heavy Ion (Cu & Kr)
Related Work



 • Asymmetric...
Related Work
Conclusion: Heavy Ion (Cu & Kr)
Related Work
Conclusions

 • Shin, (SHIN, 1990) shows that the increase of th...
Conclusions
Related Work
Conclusions
Transistor Folding




 • The efficiency of transistor sizing technique
   had show t...
Transistor Folding
                 Introduction
                 Single Event Effect
                 3D NMOSFET Device
 ...
Transistor Folding
  Conclusions
  Transistor Folding
  Transistor Folding – Alpha Particle



                           ...
Transistor Folding
 Conclusions
 Transistor Folding
 Transistor Folding – Alpha Particle


           NOT: without Folding...
Transistor Folding – Alpha Particle
             Conclusions
             Transistor Folding – Alpha Particle
            ...
Transistor Folding – Alpha Particle
Conclusions
Transistor Folding – Alpha Particle
Transistor Folding – Copper


 Number ...
Transistor Folding - Copper
                       Conclusions
                       Transistor Folding – Copper
        ...
Transistor Folding - Copper
                        Conclusions
                        Transistor Folding – Copper
      ...
Transistor Folding - Krypton
                       Conclusions
                       Transistor Folding – Krypton
      ...
Transistor Folding - Krypton
                        Conclusions
                        Transistor Folding – Krypton
    ...
Transistor Folding - Conclusions
Conclusions
Transistor Folding – Conclusions
Case Study – 6T SRAM Cell




 • For alpha p...
Case Study – 6T SRAM Cell
                     Introduction
                     Single Event Effect
                     ...
Case Study – 6T SRAM Cell
Conclusions
Case Study – 6T SRAM Cell
Conclusions




                                          ...
Case Study – 6T SRAM Cell
  Conclusions
  Case Study – 6T SRAM Cell
  Conclusions



6T SRAM Cell – Write operation


 Cel...
Case Study – 6T SRAM Cell
 Conclusions
 Case Study – 6T SRAM Cell
 Conclusions



6T SRAM Cell – Write operation




     ...
Case Study – 6T SRAM Cell
 Conclusions
 Case Study – 6T SRAM Cell
 Conclusions



6T SRAM Cell – Read operation


 Cell ra...
Case Study – 6T SRAM Cell
 Conclusions
 Case Study – 6T SRAM Cell
 Conclusions



6T SRAM Cell – Read operation




      ...
Case Study – 6T SRAM Cell
Conclusions
Case Study – 6T SRAM Cell
Conclusions

Ion                    Energy          LET   ...
Conclusions
             Introduction
             Single Event Effect
             3D NMOSFET Device
             Ion Pro...
Conclusions
Case Study – 6T SRAM Cell
Conclusions
Publications




 • The efficiency of transistor sizing technique
   had...
Conclusions
Case Study – 6T SRAM Cell
Conclusions
Publications



 • Technology Scale
        –Doping profile
            ...
Conclusions
Case Study – 6T SRAM Cell
Conclusions
Publications




 • Future Works
        – Investigate others layout top...
• Published                                                             First author: 5        Second author: 4

ASSIS, T....
• Submitted
  – European Symposium on Reliability of Electron Devices,
    Failure Physics and Analysis 2009
     • Influe...
Thanks…


          65
Analysis of Transistor Sizing
and Folding Effectiveness to
    Mitigate Soft Errors
                  Thiago Rocha de Assi...
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Maste Thesis Ap Thiago Assis

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Master thesis that cover the effects of radiation in transistor sizing and folding techniques.

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Maste Thesis Ap Thiago Assis

  1. 1. Analysis of Transistor Sizing and Folding Effectiveness to Mitigate Soft Errors Thiago Rocha de Assis Advisor: Ricardo Augusto da Luz Reis Co-Advisor: Fernanda Gusmão de Lima Kastensmidt
  2. 2. Outline Outline Introduction Single Event Effect • Introduction • Single Event Effect • 3D NMOSFET Device • Ion Profile • Transistor Sizing • Transistor Folding • Case Study – 6T SRAM Cell • Conclusions 2
  3. 3. Introduction Introduction Single Event Effect 3D NMOSFET Device Ion Profile 1 Transistor Sizing Transistor Folding Case Study – 6T SRAM Cell 3 Conclusions
  4. 4. Motivation & Objective Outline Introduction: Motivation & Obj. Methodology • Motivation – Necessity of apply an accurate methodology to evaluate transient effects caused by radiation in integrated circuits – Reduce the tolerance of transistors to radiation with the scale of technology • Objective – Evaluate the effectiveness of transistor sizing and folding techniques to mitigate soft errors 4
  5. 5. Methodology Introduction: Motivation & Obj. Methodology Sources of Radiation Mesh refinements.. 5
  6. 6. Sources of Radiation Methodology Sources of Radiation SAA “Radiation is defined as energy in transit in the form of high-speed particles or electromagnetic waves (YAVORSKY, 1972).” • Sources of Radiation – Cosmic rays + Sun + Trapped Particles (Boudenot, 2006) 6
  7. 7. SAA Sources of Radiation SAA Radiation Effects in IC 7 (Boudenot, 2006)
  8. 8. Radiation Effects in IC SAA Radiation Effects in IC Single Event Effects • Transient vs. Permanent Errors • Permanent effects – Total Ionizing Dose (TID) – Displacement Damage (DD). • Transient effects – Single Event Transient (SET) – Single Event Upset (SEU) – Single Bit Upset (SBU) and Multiple Bit Upset (MBU). Many others…. Single Event Latchup (SEL), Single Event Gate Rupture (SEGR), Single Event Functional Interruption (SEFI) 8
  9. 9. Radiation Effects in IC SAA Radiation Effects in IC Single Event Effects Total Ionizing Dose Displacement Damage (ECOFFET, 2007) Long term degradation…… 9 (NASA, 1993)
  10. 10. Single Event Effect Introduction Single Event Effect 3D NMOSFET Device Ion Profile 2 Transistor Sizing Transistor Folding Case Study – 6T SRAM Cell 10 Conclusions
  11. 11. Single Event Effect Radiation Effects in IC Single Event Effect 3D NMOSFET Device • Single Event Effect – The SEE generation mechanism. 11
  12. 12. 3D NMOSFET Device Introduction Single Event Effect 3D NMOSFET Device Ion Profile 3 Transistor Sizing Transistor Folding Case Study – 6T SRAM Cell 12 Conclusions
  13. 13. 3D NMOSFET Device Single Event Effect 3D NMOSFET Device 3D NMOSFET vs. PTM L54 Region Width (x) Width(y) Width (z) Doping LDD 115 nm 30 nm 240 nm n-type. Peak: 1e19 SourceDrain 240 nm 60 nm 240 nm n-type. Peak:1e20 SSR 90 nm 5 nm 240 nm n-type. Peak:1.5e18 Gate 136 nm 300 nm 240 nm n-type. Peak:2e20 Oxide 136 nm 1.4 nm 240 nm None Substrate 0.9 1.5 0.3 um p-type. Peak:5.5e18 (MIT, Well tempered bulk CMOS,2008) 13 (DASGUPTA, Vanderbilt University. 2007)
  14. 14. 3D NMOSFET Device Single Event Effect 3D NMOSFET Device 3D NMOSFET vs. PTM L54 Gate Device modeled using Davinci tool from Synopsys. Methods: Source Substrate Drain 1. Numerical method of Newton Contact 2. Incomplete Cholesky Conjugate Gradients (ICCG). Physical Models: 1. Shockley-Read-Hall Model - SRH 2. Auger Recombination Model - AUGER 3. Carrier-Carrier Scattering Mobility Model - CCSMOB 4. Bang-Gap Narrowing Model - BGN 14
  15. 15. 3D NMOSFET vs. PTM L54 3D NMOSFET Device 3D NMOSFET vs. PTM L54 Ion Profile Vs=Vb= 0 V Vgs= 1.2V 15
  16. 16. 3D NMOSFET vs. PTM L54 3D NMOSFET Device 3D NMOSFET vs. PTM L54 Ion Profile Vs=Vb= 0 V Vgs= 1.2V Threshold Voltage •ST 90nm: Vt=0.34 V •PTM model: Vt=0.39V (ASU, 08) •TCAD Model: Vt=0.36 (ASU, Predictive Technology Model , 2008) 16 (STMicroelectronics. HCMOS9_GP Design Rules ,2002)
  17. 17. Ion Profile Introduction Single Event Effect 3D NMOSFET Device Ion Profile 4 Transistor Sizing Transistor Folding Case Study – 6T SRAM Cell 17 Conclusions
  18. 18. Ion Profile 3D NMOSFET vs. PTM L54 Ion profile Ion profile – Alpha Particle • The Environment (LERAY, 2004) • For sea level • Alpha particle • About 1 MeV/(mg/cm2) • Avionics • 10-20 MeV/(mg/cm2) • Space Applications • +20 MeV/(mg/cm2) 18 (LERAY, International Conference on Integrated Circuit Design and Technology, 2004)
  19. 19. Ion Profile – Alpha Particle Ion Profile Ion Profile – Alpha Particle Ion Profile - Copper • Alpha Particle (He nuclei) (ZIEGLER, SRIM 2008, 2008) 19
  20. 20. Ion Profile – Alpha Particle Ion Profile Ion Profile – Alpha Particle Ion Profile - Copper • Alpha Particle (He nuclei) Radial Distribution: 50nm (ZIEGLER, SRIM 2008, 2008) 20
  21. 21. Ion Profile - Copper Ion Profile – Alpha Particle Ion Profile – Copper Ion Profile - Krypton • Copper (Cu) (ZIEGLER, SRIM 2008, 2008) 21
  22. 22. Ion Profile - Copper Ion Profile – Alpha Particle Ion Profile – Copper Ion Profile - Krypton • Copper (Cu) Radial Distribution: 500nm (ZIEGLER, SRIM 2008, 2008) 22
  23. 23. Ion Profile - Krypton Ion Profile – Alpha Particle Ion Profile – Krypton Ion Profile (ZIEGLER, SRIM 2008, 2008) 23
  24. 24. Ion Profile - Krypton Ion Profile – Alpha Particle Ion Profile – Krypton Ion Profile • Krypton (Kr) Radial Distribution: 650nm 24
  25. 25. Ion Profile Ion Profile – Alpha Particle Ion Profile Physical Models • Impact details – Hit the transistor drain center – Impact angle: 90 degrees – Pass through the device 3D NMOSFET under irradiation Table 4 - Ion profile Element / LET(dE/dX) Radial (r) m Energy MeV/(mg/cm2) Alpha – 1 1.31 0.05 MeV Cu, 395 MeV 26.5 0.5 Ion track Kr, 270 MeV 40.5 0.65 (ZIEGLER, SRIM 2008, 2008) 25
  26. 26. Physical Models Ion Profile – Alpha Particle Physical Models Transistor Sizing • Models used during simulations •Shockley-Read-Hall Model - SRH •Auger Recombination Model - AUGER (LUNDSTROM, 2000) •Carrier-Carrier Scattering Mobility Model - CCSMOB •Bang-Gap Narrowing Model - BGN (SLOTBOOM, 1977) SRH AUGER (SCHOCKLEY, 1952) (LANDSBERG, 1964) 26
  27. 27. Transistor Sizing Introduction Single Event Effect 3D NMOSFET Device Ion Profile 5 Transistor Sizing Transistor Folding Case Study – 6T SRAM Cell 27 Conclusions
  28. 28. Transistor Sizing Technique Physical Models Transistor Sizing Technique Transistor Sizing Electric Evaluation The idea behind the transistor sizing technique is based on the increase of the Critical Charge of the node. The critical charge is given by the following equation.. VTRIP  (C Qcrit   2CCOUPLE )dV  n  I N , P  TPULSE TOTAL 0 CTOTAL  CGON  AN  CGOP  AP  (CGDON  CGDLN )  wn  (CGDOP  CGDLP )  w p  (C JAN  ADN  C JSWN  wN )  (C JAP  ADP  C JSWP  w p )(1) * Basically the transistor width is increased making the total capacitance of the node increase and so the critical charge. where VTRIP is the standard voltage of technology, CTOTAL is the total front-end capacitor, CCOUPLE is the coupling capacitance, CGON and CGOP are gate capacitances of N/P transistors, AN and AP are gate area of N/P transistors respectively, CGDON and CGDP are bias-independent part of the overlap capacitance, and CGDLN and CGDLP are bias-dependent overlap capacitance. Source and drain junction capacitance are CJAN and CJAP, and sidewall capacitances are CJSWN and CJSWP respectively 28 (ZHOU, IEEE CAD Design of Integrated Circuits Systems, 2006)
  29. 29. Transistor Sizing Electric Evaluation Transistor Sizing Technique Transistor Sizing Electric Evaluation 3D NMOSFET Device The technique was evaluated by (ZHOU & LAZZARI) at electric level using the double exponential equation to model the SEE.   t  t  I in (t )  I 0     e   e     The current modeled by the equation is injected in a node of the circuit and results are collected.  The problem : With the increase of the transistor width, the geometry of the device is increased and the effect of the ion particle for this new geometry is not evaluated when using this technique. A device level simulations is required! 29 (MESSENGER, NSREC, 1982)
  30. 30. Device Under Test Transistor Sizing Electric Evaluation Device Under Test Results: Alpha Particle (b) (a) (c) (d) (a) NOT gate – Input 0 (b) NAND gate – Input 01 (c) NAND gate – Input 10 (d) NOR gate – Input 00 30
  31. 31. Device Under Test Transistor Sizing Electric Evaluation Device Under Test Results: Alpha Particle Table 2 – Symmetric Sizing Table 1 – Asymmetric Sizing NMOS PMOS NMOS PMOS Sizes Wn(nm) Wp(nm) Sizes transistors transistors W0 220 390 Wn(nm) Wp(nm) W1 510 880 W0 220 880 W2 1.020 1.760 W1 510 880 W2_3 2.040 3.508 W2 1.020 880 W3 3.060 5.263 Table 3 - Output Capacitances W4 4.080 7.017 Name Capacitance Name Capacitance W5 5.100 8.772 C1 10f F C6 500f F C2 20f F C7 1p F C3 40f F C8 10p F C4 80f F C9 20p F C5 160f F 31
  32. 32. Results: Alpha Particle Device Under Test Results: Alpha Particle Conclusion: Alpha Particle 1,31 MeV/(mg/cm2) Asymmetric 2.246E-14 Collected Charge (C) 1,31 MeV/(mg/cm2) Symmetric Both sizing methodologies increase 2.0048E-14 1.6323E-14 the collected charge. 9.9227E-15 1.6323E-14 1.590E-15 W0 W1 W2 The SEE pulse peak SEE Pulse Peak (V) Asymmetric Symmetric decreases which means that the pulse is getting worst. 1.10 1.03 1.02 1.03 0.97 The symmetric sizing 0.83 simulations will be extended W0 W1 W2 due a possible recovery. 32
  33. 33. Results: Alpha Particle Device Under Test Results: Alpha Particle Conclusion: Alpha Particle 6.000E-14 Collected charge of symmetric sizing continues increasing… 5.000E-14 Collected Charge (C) 4.000E-14 3.000E-14 2.000E-14 1.000E-14 0.000E+00 W0 W1 W2 W2_3 W3 W4 W5 1.10 But the SEE pulse peak shows the recovery of the transistor, 1.08 indicating that the technique is SEE Pulse Peak (V) 1.06 working for symmetric sizing. 1.04 1.02 1.00 0.98 0.96 W0 W1 W2 W2_3 W3 W4 W5 33
  34. 34. Results: Alpha Particle Device Under Test Results: Alpha Particle Conclusion: Alpha Particle Increasing the output capacitance… SEE Pulse 34
  35. 35. Conclusion: Alpha Particle Results: Alpha Particle Conclusion: Alpha Particle Results: Heavy Ion (Cu & Kr) • Asymmetric sizing: the SEE pulse has not shown signs of recovering for the transistors that were increased. • Symmetric sizing: the SEE pulse was reduced with the increase of the transistor width. Notice that for both methodologies the transistor width was increased, but just symmetric sizing shows recovery. This indicates that the recovery of the symmetric size happens more due to the increase of the capacitance and drive current of the pull-up transistors. 35
  36. 36. Results: Heavy Ion (Cu & Kr) Conclusion: Alpha Particles Results: Heavy Ion (Cu & Kr) Conclusion: Heavy Ion (Cu & Kr) Cu: 26.5 MeV/(mg/cm2) Kr: 40.5 MeV/(mg/cm2) SEE Pulse Peak (V) Asymmetric Symmetric -0.101 Asymmetric Symmetric 0.102 -0.279 -0.18 -0.282 -0.28 -0.49 -0.50 -0.06 -0.28 -0.628 -0.610 W0 W1 W2 Collected Charge (C) Asymmetric Symmetric 6.340E-13 40,5 MeV/(mg/cm2) Asymmetric 1.259E-12 40,5 MeV/(mg/cm2) Symmetric 3.176E-13 2.953E-13 5.432E-13 2.177E-13 3.457E-13 6.317E-13 3.065E-13 5.484E-13 1.246E-13 2.073E-13 W0 W1 W2 W0 W1 W2 Heavy ion simulations presents the same behavior for Cu and Kr. The SEE pulse peak is reduced (getting worst) and the collected charge increases in both methodologies. 36
  37. 37. Results: Heavy Ion (Cu & Kr) Conclusion: Alpha Particles Results: Heavy Ion (Cu & Kr) Conclusion: Heavy Ion (Cu & Kr) Cu: 26.5 MeV/(mg/cm2) Kr: 40.5 MeV/(mg/cm2) Asymmetric Symmetric Pulse Width (s) Asymmetric 1.28E-08 Symmetric 1.134E-08 3.03E-09 5.36E-09 2.787E-09 1.86E-09 5.357E-09 1.858E-09 2.787E-09 3.03E-09 4.831E-10 5.80E-10 W0 W1 W2 W0 W1 W2 The SET pulse width also present similar behavior for both ions. The SET pulse width increases for both methodologies having the asymmetric sizing the worst results. 37
  38. 38. Results: Heavy Ion (Cu & Kr) Conclusion: Alpha Particles Results: Heavy Ion (Cu & Kr) Conclusion: Heavy Ion (Cu & Kr) 1.20 1.00 0.80 0.60 C1-Drain Voltage 0.40 Voltage (V) SEE Pulse C2-Drain Voltage 0.20 C3-Drain Voltage 0.00 C4-Drain Voltage C6-Drain Voltage -0.20 C7-Drain Voltage -0.40 C8-Drain Voltage -0.60 C9-Drain Voltage -0.80 -2.3000E-22 5.0000E-09 1.0000E-08 1.5000E-08 2.0000E-08 Time (S) Table 5 – Pull-up transistor sized Using a fixed Pulse Width Wn=220nm Increase the pull-up transistors will reduce the pulse if Wp=0.390nm 5,066e-9 38 the transient happens in the pull-down devices. Wp=0.880nm 1,095e-9
  39. 39. Conclusion: Heavy Ion (Cu & Kr) Results: Heavy Ion (Cu & Kr) Conclusion: Heavy Ion (Cu & Kr) Related Work • Asymmetric sizing: for both ions the methodology was not able to restore the pulse. • Symmetric sizing: the technique was not able to restore the pulse. Due the high amount of charge injected by heavy ions, the increase of the capacitance of the node do not help much the recovery of the transistor. Notice that for both technologies there is no sign of possible recovery. Even when simulations are extended to evaluate larger widths, the pulse continue to get worst. 39
  40. 40. Related Work Conclusion: Heavy Ion (Cu & Kr) Related Work Conclusions • Shin, (SHIN, 1990) shows that the increase of the junction area imposes an increase of the funneling of the electric field • Baumann, (BAUMANN, 2005) reports that large junctions areas are efficient in collecting radiation induced charge. (SHIN, H. IEEE TRANSACTIONS ON ELECTRON DEVICES, 1999) 40 (BAUMANN, R.C. IEEE TRANSACTIONS ON DEVICE AND MATERIALS RELIABILITY, 2005)
  41. 41. Conclusions Related Work Conclusions Transistor Folding • The efficiency of transistor sizing technique had show to be dependent of the ion that is hitting the device. – For alpha particles the technique had shown to be able to allow the recovery of the device due the small amount of charge transferred by the ion to the device. – For heavy ions the technique had not shown to be efficient due the large amount of charge generated by the ion. • The asymmetric sizing had show the worst results when compared with symmetric sizing. 41
  42. 42. Transistor Folding Introduction Single Event Effect 3D NMOSFET Device Ion Profile 6 Transistor Sizing Transistor Folding Case Study – 6T SRAM Cell 42 Conclusions
  43. 43. Transistor Folding Conclusions Transistor Folding Transistor Folding – Alpha Particle Transistor folding… (HER, 1993) 43
  44. 44. Transistor Folding Conclusions Transistor Folding Transistor Folding – Alpha Particle NOT: without Folding NOT: with Folding PMOS NMOS Sizes PMOS NMOS Sizes Wp(um) Wn(um) Folding Wp(um) Wn(um) W0 3.52 2.040 W0_S 2x1.760 2x1.020 W1 5.28 3.06 W1_S 3x1.760 3x1.020 W2 7.04 4.08 W2_S 4x1.760 4x1.020 W3 8.8 5.1 W3_S 5x1.760 5x1.020 W4 10.56 6.12 W4_S 6x1.760 6x1.020 Folding rate PMOS NMOS Sizes Wp(um) Wn(um) Wn1 1x8.8 1x5.1 Wn2 2x4.4 2x2.55 Wn3 3x2.933 3x1.7 Wn4 4x2.2 4x1.275 44
  45. 45. Transistor Folding – Alpha Particle Conclusions Transistor Folding – Alpha Particle Transistor Folding – Copper 1.250 Both techniques allows a better SEE Pulse Peak (V) 1.200 recovery.. 1.150 1.100 1.050 Folding 1.000 0.950 No Folding 0.900 W0 W1 W2 W3 W4 6.00E-14 Collected Charge (C) 5.00E-14 No Folding Using folding the collected 4.00E-14 charge is controlled during 3.00E-14 Folding the increase… 2.00E-14 1.00E-14 0.00E+00 w0 w1 w2 w3 w4 45
  46. 46. Transistor Folding – Alpha Particle Conclusions Transistor Folding – Alpha Particle Transistor Folding – Copper Number of partitions of the transistor….. 1.10 1.09 1.08 SEE Pulse Peak (V) 1.07 1.06 1.05 1.04 1.03 1.02 1.01 1.00 Wn1 Wn2 Wn3 Wn4 Recovery is seen… This is the first partition. 1 drain area is shared by 2 transistors. (SHIN, H. IEEE TRANSACTIONS ON ELECTRON DEVICES, 1999) 46 (BAUMANN, R.C. IEEE TRANSACTIONS ON DEVICE AND MATERIALS RELIABILITY, 2005)
  47. 47. Transistor Folding - Copper Conclusions Transistor Folding – Copper Transistor Folding – Krypton 0.00 SEE Pulse Peak (V) The drop of the bias is reduced -0.20 when folding devices are used.. -0.40 Folding No Folding -0.60 6E-09 -0.80 W0 W1 W2 W3 W4 5E-09 Pulse Width (s) Folding The pulse width of the SET is 4E-09 No Folding drastically reduced.. 3E-09 2E-09 1E-09 Collected Charge (C) 5.00E-11 W0 W1 W2 W3 W4 0 4.00E-11 3.00E-11 Folding allows an small increase of 2.00E-11 the collected charge.. Folding No Folding 1.00E-11 0.00E+00 W0 W1 W2 W3 W4 47
  48. 48. Transistor Folding - Copper Conclusions Transistor Folding – Copper Transistor Folding – Krypton 5.00E-11 Increasing the number of partitions Collected Charge (C) allows the reduce of the pulse 4.00E-11 3.00E-11 2.00E-11 0.00 -0.10 SEE Pulse Peak (V) 1.00E-11 -0.20 -0.30 0.00E+00 -0.40 Wn1 Wn2 Wn3 Wn4 -0.50 -0.60 -0.70 9.00E-09 -0.80 8.00E-09 7.00E-09 Wn1 Wn2 Wn3 Wn4 Pulse Width (s) 6.00E-09 5.00E-09 Both pulse width and amplitude are 4.00E-09 3.00E-09 reduced…. 2.00E-09 1.00E-09 0.00E+00 48 Wn1 Wn2 Wn3 Wn4
  49. 49. Transistor Folding - Krypton Conclusions Transistor Folding – Krypton Transistor Folding – Conclusions 0.00 -0.10 The drop of the bias is reduced SEE Pulse Peak (V) -0.20 when folding devices are used.. -0.30 Folding No Folding -0.40 -0.50 -0.60 1E-08 -0.70 -0.80 W0 W1 W2 W3 W4 8E-09 Pulse Width (s) 6E-09 The pulse width of the SET is Folding No Folding drastically reduced.. 4E-09 2E-09 6.00E-11 0 Collected Charge (C) Folding W0 W1 W2 W3 W4 5.00E-11 No Folding 4.00E-11 3.00E-11 Folding allows an small increase of the collected charge.. 2.00E-11 1.00E-11 0.00E+00 49 W0 W1 W2 W3 W4
  50. 50. Transistor Folding - Krypton Conclusions Transistor Folding – Krypton Transistor Folding – Conclusions 6E-11 Increasing the number of partitions Collected Charge (C) 5E-11 allows the reduce of the pulse 4E-11 3E-11 2E-11 0 1E-11 SEE Pulse Peak (V) -0.1 0 -0.2 Wn1 Wn2 Wn3 Wn4 -0.3 -0.4 -0.5 -0.6 1.2E-08 -0.7 Pulse Width (s) -0.8 1E-08 Wn1 Wn2 Wn3 Wn4 8E-09 Both pulse width and amplitude are 6E-09 reduced…. 4E-09 2E-09 0 50 Wn1 Wn2 Wn3 Wn4
  51. 51. Transistor Folding - Conclusions Conclusions Transistor Folding – Conclusions Case Study – 6T SRAM Cell • For alpha particles – The partition of the transistor had allow the recovery of the ionization as transistor sizing. • For heavy ions profile like Co and Kr ions the transistor folding had allow a better recovery when compared with transistor sizing. – The SET pulse width is drastically reduced when the device is folded • The higher the number of partitions the larger is the reduce over the effects of the ionization. 51
  52. 52. Case Study – 6T SRAM Cell Introduction Single Event Effect 3D NMOSFET Device Ion Profile 7 Transistor Sizing Transistor Folding Case Study – 6T SRAM Cell 52 Conclusions
  53. 53. Case Study – 6T SRAM Cell Conclusions Case Study – 6T SRAM Cell Conclusions (RABAEY, 2003). [nm] M1 M2 M3 M4 M5 M6 Mload SRAM 175 125 175 125 125 125 12.5um Standard SRAM+ 350 250 350 250 250 250 25um Sizing SRAM+ 2*175 2*125 2*175 2*125 2*125 2*125 25um Folding 53
  54. 54. Case Study – 6T SRAM Cell Conclusions Case Study – 6T SRAM Cell Conclusions 6T SRAM Cell – Write operation Cell rate for write (PR) M6*PR = M3 PR=1.4 54
  55. 55. Case Study – 6T SRAM Cell Conclusions Case Study – 6T SRAM Cell Conclusions 6T SRAM Cell – Write operation 55
  56. 56. Case Study – 6T SRAM Cell Conclusions Case Study – 6T SRAM Cell Conclusions 6T SRAM Cell – Read operation Cell rate for read (CR) M5*CR = M1 PR=1.4 The 1.4 cell rate (PR & CR) was recommended by (AGARWAL, 2006) 56
  57. 57. Case Study – 6T SRAM Cell Conclusions Case Study – 6T SRAM Cell Conclusions 6T SRAM Cell – Read operation 57
  58. 58. Case Study – 6T SRAM Cell Conclusions Case Study – 6T SRAM Cell Conclusions Ion Energy LET Radial (MeV/mg/cm2) Distribution He 1 MeV 1.31 50nm X X0 5 50nm Y Y0 10 50nm Z Z0 10 110nm Cu 395 MeV 26.5 0.5um SEU is mitigated… Kr 270 MeV 40.5 0.65um 1.2 1 0.8 0.6 Voltage (V) 0.4 STD-SET Pulse Peak (V) 0.2 0 Folding-SET Pulse Peak (V) -0.2 -0.4 Sizing-SET Pulse Peak (V) -0.6 -0.8 58 He X Y Z Cu Kr
  59. 59. Conclusions Introduction Single Event Effect 3D NMOSFET Device Ion Profile 8 Transistor Sizing Transistor Folding Case Study – 6T SRAM Cell 59 Conclusions
  60. 60. Conclusions Case Study – 6T SRAM Cell Conclusions Publications • The efficiency of transistor sizing technique had show to be dependent of the ion that is hitting the device. – For alpha particles the technique had shown to be able to allow the recovery of the device. – For heavy ions the technique had not shown to be efficient due the large amount of charge generated by the ion. • For transistor folding both heavy ions and sea level profiles had shown a reduction in their effect. 60
  61. 61. Conclusions Case Study – 6T SRAM Cell Conclusions Publications • Technology Scale –Doping profile • +doping -> Increase electric field strength – More charge collected due Drift Current • -doping -> Decrease electric field strength – Less charge collected due Drift Current – Device geometry • Drain area – Reducing the size » Allows less charge to be collected » More devices in the impact region • Multiple collected charge 61
  62. 62. Conclusions Case Study – 6T SRAM Cell Conclusions Publications • Future Works – Investigate others layout topologies like: • Enclosed Layout Transistors – Silicon on Insulator (SOI) 62
  63. 63. • Published First author: 5 Second author: 4 ASSIS, T. R. ; KASTENSMIDT, F.L.G ; WIRTH, G. ; REIS, R.A. . Measuring the Effectiveness of Symmetric and Asymmetric Transistor Sizing for Single Event Transient Mitigation in CMOS 90nm Technologies. In: 10th IEEE Latin-American TestWorkshop, 2009, Buzios. 10th IEEE Latin-American TestWorkshop, 2009. ASSIS, T. R. ; KASTENSMIDT, F.L.G ; WIRTH, G. ; REIS, R.A. . Avaliando a eficiência do redimensionamento simétrico e assimétrico de transistores para a redução de Single Event Effects em uma tecnologia 90nm CMOS. In: IBERCHIP XV Workshoop, 2009, Buenos Aires. IBERCHIP XV Workshoop, 2009. LAZZARI, C. ; ASSIS, T. R. ; KASTENSMIDT, F.L.G ; WIRTH, G. ; ANGHEL, L. ; REIS, R.A. . SET-Factor: An Analysis and Design Tool to Reduce SET Sensitivity in Integrated Circuits. In: European Test Symposium, 2008, Verbania. European Test Symposium 2008, 2008. LAZZARI, C. ; ASSIS, T. R. ; KASTENSMIDT, F.L.G ; WIRTH, G. ; ANGHEL, L. ; REIS, R.A. . Asymmetric and Symmetric Transistor Sizing to Reduce SET Sensitivity in Integrated Circuits. In: 23th South Symposium on Microelectronics, 2008, Bento Gonçalves. 23th South Symposium ASSIS, T. R. ; WIRTH, G. ; KASTENSMIDT, F.L.G ; REIS, R.A. . Modeling of a NMOS 90 nm device to Multiple Event Transient Simulation. In: 23th South Symposium on Microelectronics, 2008, Bento Gonçalves. 23th South Symposium on Microelectronics, 2008. ASSIS, T. R. ; WIRTH, G. ; KASTENSMIDT, F.L.G ; REIS, R.A. . DESIGN AND EVALUATION OF A NMOS 90 nm 3D DEVICE. In: 8th Microelectronic Students Forum 2008 - SBCCI 2008, 2008, Gramado. 8th Microelectronic Students Forum 2008, 2008. LAZZARI, C. ; ASSIS, T. R. ; KASTENSMIDT, F.L.G ; WIRTH, G. ; REIS, R.A. ; ANGHEL, L. . An Analysis and Design Technique to Reduce SET Sensitivity in Combinational Integrated Circuits. In: IFIP/IEEE VLSI-SoC2008, International Conference on Very Large Scale Integration, 2008,, 2008, Rhodes. IFIP/IEEE VLSI-SoC2008, International Conference on Very Large Scale Integration., 2008. v. 1. ASSIS, T. R. ; KASTENSMIDT, F.L.G ; WIRTH, G. ; REIS, R.A. . ANALYSIS OF SINGLE EVENT EFFECTS FOR DIFFERENT ANGLES AND IMPACT REGIONS AT A NMOS 90nm 3D DEVICE. In: Second International Workshop on Dependable Circuit Design, 2008, Playa del Carmen. Second International Workshop on Dependable Circuit Design - 2008, 2008. LAZZARI, C. ; ASSIS, T. R. ; KASTENSMIDT, F.L.G ; WIRTH, G. ; ANGHEL, L. ; REIS, R.A. . Efficient Transistor Sizing for Soft Error Protection in Combinational Logic Circuits. In: First International Workshop on Dependable Circuit Design, 2007, Buenos Aires. First International Workshop on Dependable Circuit Design, 2007. v. 1. 63
  64. 64. • Submitted – European Symposium on Reliability of Electron Devices, Failure Physics and Analysis 2009 • Influence of Carriers Spatial Distribution Generated During Ionization to Soft Errors Simulation • To Submit – Transistor folding results • Others activities – Chairman of IEEE Circuits & System Society Student Branch • 2008/2009 64
  65. 65. Thanks… 65
  66. 66. Analysis of Transistor Sizing and Folding Effectiveness to Mitigate Soft Errors Thiago Rocha de Assis Advisor: Ricardo Augusto da Luz Reis Co-Advisor: Fernanda Gusmão de Lima Kastensmidt

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