Random-access memory 1 Random-access memory Example of writable volatile random-access memory: Synchronous Dynamic RAM modules, primarily used as main memory in personal computers, workstations, and servers. Computer memory types Volatile • DRAM (e.g., DDR SDRAM) • SRAM • In development • T-RAM • Z-RAM • TTRAM • Historical • Delay line memory • Selectron tube • Williams tube Non-volatile • ROM • PROM • EPROM • EEPROM • Flash memory • Early stage • FeRAM • MRAM • PRAM • In development • CBRAM • SONOS • RRAM • Racetrack memory • NRAM • Millipede • Historical • Drum memory • Magnetic core memory • Plated wire memory • Bubble memory • Twistor memory
Random-access memory 2 Random-access memory (RAM) is a form of computer data storage. Today, it takes the form of integrated circuits that allow stored data to be accessed in any order with a worst case performance of constant time. Strictly speaking, modern types of DRAM are therefore not random access, as data is read in bursts, although the name DRAM / RAM has stuck. However, many types of SRAM, ROM, OTP, and NOR flash are still random access even in a strict sense. RAM is often associated with volatile types of memory (such as DRAM memory modules), where its stored information is lost if the power is removed. Many other types of non-volatile memory are RAM as well, including most types of ROM and a type of flash memory called NOR-Flash. The first RAM modules to come into the market were created in 1951 and were sold until the late 1960s and early 1970s. Other memory devices (magnetic tapes, disks) can access the storage data only in a predetermined order, because of mechanical design limitations. History An early type of widespread writable random-access memory was magnetic core memory, developed from 1955 to 1975, and subsequently used in most computers up until the development and adoption of the static and dynamic integrated RAM circuits in the late 1960s and early 1970s. Before this, computers used relays, delay line/delay memory, or various kinds of vacuum tube arrangements to implement "main" memory functions (i.e., hundreds or thousands of bits), some of which were random access, some not. Drum memory 1 Megabit chip - one of the last models developed could be expanded at low cost but retrieval of non-sequential memory by VEB Carl Zeiss Jena in 1989 items required knowledge of the physical layout of the drum to optimize speed. Latches built out of vacuum tube triodes, and later, out of discrete transistors, were used for smaller and faster memories such as random-access register banks and registers. Prior to the development of integrated ROM circuits, permanent (or read-only) random-access memory was often constructed using semiconductor diode matrices driven by address decoders, or specially wound core memory planes. Types of RAM The two main forms of modern RAM are static RAM (SRAM) and dynamic RAM (DRAM). In static RAM, a bit of data is stored using the state of a flip-flop. This form of RAM is more expensive to produce, but is generally faster and requires less power than DRAM and, in modern computers, is often used as cache memory for the CPU. DRAM stores a bit of data using a transistor and capacitor pair, which together comprise a memory cell. The capacitor holds a high or low Top L-R, DDR2 with heat-spreader, DDR2 without heat-spreader, Laptop DDR2, DDR, charge (1 or 0, respectively), and the transistor acts as a switch that lets Laptop DDR the control circuitry on the chip read the capacitors state of charge or change it. As this form of memory is less expensive to produce than static RAM, it is the predominant form of computer memory used in modern computers. Both static and dynamic RAM are considered volatile, as their state is lost or reset when power is removed from the system. By contrast, Read-only memory (ROM) stores data by permanently enabling or disabling selected transistors, such that the memory cannot be altered. Writeable variants of ROM (such as EEPROM and flash memory) share properties of both ROM and RAM, enabling data to persist without power and to be updated without requiring special equipment. These persistent forms of semiconductor ROM include USB flash drives, memory cards
Random-access memory 3 for cameras and portable devices, etc. As of 2007, NAND flash has begun to replace older forms of persistent storage, such as magnetic disks and tapes, while NOR flash is being used in place of ROM in netbooks and rugged computers, since it is capable of true random access, allowing direct code execution. ECC memory (which can be either SRAM or DRAM) includes special circuitry to detect and/or correct random faults (memory errors) in the stored data, using parity bits or error correction code. In general, the term RAM refers solely to solid-state memory devices (either DRAM or SRAM), and more specifically the main memory in most computers. In optical storage, the term DVD-RAM is somewhat of a misnomer since, like CD-RW, a rewriteable DVD must be erased before it can be rewritten. Memory hierarchy Many computer systems have a memory hierarchy consisting of CPU registers, on-die SRAM caches, external caches, DRAM, paging systems, and virtual memory or swap space on a hard drive. This entire pool of memory may be referred to as "RAM" by many developers, even though the various subsystems can have very different access times, violating the original concept behind the random access term in RAM. Even within a hierarchy level such as DRAM, the specific row, column, bank, rank, channel, or interleave organization of the components make the access time variable, although not to the extent that rotating storage media or a tape is variable. The overall goal of using a memory hierarchy is to obtain the higher possible average access performance while minimizing the total cost of the entire memory system (generally, the memory hierarchy follows the access time with the fast CPU registers at the top and the slow hard drive at the bottom). In many modern personal computers, the RAM comes in an easily upgraded form of modules called memory modules or DRAM modules about the size of a few sticks of chewing gum. These can quickly be replaced should they become damaged or when changing needs demand more storage capacity. As suggested above, smaller amounts of RAM (mostly SRAM) are also integrated in the CPU and other ICs on the motherboard, as well as in hard-drives, CD-ROMs, and several other parts of the computer system. Other uses of RAM In addition to serving as temporary storage and working space for the operating system and its applications, RAM is used in numerous other ways. Virtual memory Most modern operating systems employ a method of extending RAM capacity, known as "virtual memory". A portion of the computers hard drive is set aside for a paging file or a scratch partition, and the combination of physical RAM and the paging file form the systems total memory. (For example, if a computer has 2 GB of RAM and a 1 GB page file, the operating system has 3 GB total memory available to it.) When the system runs low on physical memory, it can "swap" portions of RAM to the paging file to make room for new data, as well as to read previously swapped information back into RAM. Excessive use of this mechanism results in thrashing and generally hampers overall system performance, mainly because hard drives are far slower than RAM.
Random-access memory 4 RAM disk Software can "partition" a portion of a computers RAM, allowing it to act as a much faster hard drive that is called a RAM disk. A RAM disk loses the stored data when the computer is shut down, unless memory is arranged to have a standby battery source. Shadow RAM Sometimes, the contents of a relatively slow ROM chip are copied to read/write memory to allow for shorter access times. The ROM chip is then disabled while the initialized memory locations are switched in on the same block of addresses (often write-protected). This process, sometimes called shadowing, is fairly common in both computers and embedded systems. As a common example, the BIOS in typical personal computers often has an option called “use shadow BIOS” or similar. When enabled, functions relying on data from the BIOS’s ROM will instead use DRAM locations (most can also toggle shadowing of video card ROM or other ROM sections). Depending on the system, this may not result in increased performance, and may cause incompatibilities. For example, some hardware may be inaccessible to the operating system if shadow RAM is used. On some systems the benefit may be hypothetical because the BIOS is not used after booting in favor of direct hardware access. Free memory is reduced by the size of the shadowed ROMs. Recent developments Several new types of non-volatile RAM, which will preserve data while powered down, are under development. The technologies used include carbon nanotubes and approaches utilizing the magnetic tunnel effect. Amongst the 1st generation MRAM, a 128 KiB (128 × 210 bytes) magnetic RAM (MRAM) chip was manufactured with 0.18 µm technology in the summer of 2003. In June 2004, Infineon Technologies unveiled a 16 MiB (16 × 220 bytes) prototype again based on 0.18 µm technology. There are two 2nd generation techniques currently in development: Thermal Assisted Switching (TAS) which is being developed by Crocus Technology, and Spin Torque Transfer (STT) on which Crocus, Hynix, IBM, and several other companies are working. Nantero built a functioning carbon nanotube memory prototype 10 GiB (10 × 230 bytes) array in 2004. Whether some of these technologies will be able to eventually take a significant market share from either DRAM, SRAM, or flash-memory technology, however, remains to be seen. Since 2006, "Solid-state drives" (based on flash memory) with capacities exceeding 256 gigabytes and performance far exceeding traditional disks have become available. This development has started to blur the definition between traditional random access memory and "disks", dramatically reducing the difference in performance. Some kinds of random-access memory, such as "EcoRAM", are specifically designed for server farms, where low power consumption is more important than speed. Memory wall The "memory wall" is the growing disparity of speed between CPU and memory outside the CPU chip. An important reason for this disparity is the limited communication bandwidth beyond chip boundaries. From 1986 to 2000, CPU speed improved at an annual rate of 55% while memory speed only improved at 10%. Given these trends, it was expected that memory latency would become an overwhelming bottleneck in computer performance. Currently, CPU speed improvements have slowed significantly partly due to major physical barriers and partly because current CPU designs have already hit the memory wall in some sense. Intel summarized these causes in their Platform 2015 documentation (PDF)  “First of all, as chip geometries shrink and clock frequencies rise, the transistor leakage current increases, leading to excess power consumption and heat... Secondly, the advantages of higher clock speeds are in part negated by memory latency, since memory access times have not been able to keep
Random-access memory 5 pace with increasing clock frequencies. Third, for certain applications, traditional serial architectures are becoming less efficient as processors get faster (due to the so-called Von Neumann bottleneck), further undercutting any gains that frequency increases might otherwise buy. In addition, partly due to limitations in the means of producing inductance within solid state devices, resistance-capacitance (RC) delays in signal transmission are growing as feature sizes shrink, imposing an additional bottleneck that frequency increases dont address.” The RC delays in signal transmission were also noted in Clock Rate versus IPC: The End of the Road for Conventional Microarchitectures  which projects a maximum of 12.5% average annual CPU performance improvement between 2000 and 2014. The data on Intel Processors  clearly shows a slowdown in performance improvements in recent processors. However, Intels Core 2 Duo processors (codenamed Conroe) showed a significant improvement over previous Pentium 4 processors; due to a more efficient architecture, performance increased while clock rate actually decreased. Notes and references  "Shadow Ram" (http:/ / hardwarehell. com/ articles/ shadowram. htm). . Retrieved 2007-07-24.  The Emergence of Practical MRAM http:/ / www. crocus-technology. com/ pdf/ BH%20GSA%20Article. pdf  http:/ / www. eetimes. com/ news/ latest/ showArticle. jhtml?articleID=218000269  "EcoRAM held up as less power-hungry option than DRAM for server farms" (http:/ / blogs. zdnet. com/ green/ ?p=1165) by Heather Clancy 2008  The term was coined in Hitting the Memory Wall: Implications of the Obvious (PDF) (http:/ / www. cs. virginia. edu/ papers/ Hitting_Memory_Wall-wulf94. pdf).  http:/ / epic. hpi. uni-potsdam. de/ pub/ Home/ TrendsAndConceptsII2010/ HW_Trends_borkar_2015. pdf  http:/ / www. cs. utexas. edu/ users/ cart/ trips/ publications/ isca00. pdf  http:/ / www. intel. com/ pressroom/ kits/ quickreffam. htm External links • Memory Prices (1957-2010) (http://www.jcmit.com/memoryprice.htm)
DDR3 SDRAM 6 DDR3 SDRAM In computing, DDR3 SDRAM, an abbreviation for double data rate type three synchronous dynamic random access memory, is a modern kind of dynamic random access memory (DRAM) with a high bandwidth interface. It is one of several variants of DRAM and associated interface techniques used since the early 1970s. DDR3 SDRAM is not directly compatible with any earlier type of random access memory (RAM) due to different signaling voltages, timings, and other factors. DDR3 is a DRAM interface specification. The actual DRAM arrays that store the data are similar to earlier types, with similar performance. The primary benefit of DDR3 SDRAM over its immediate predecessor, DDR2 SDRAM, is its ability to transfer data at twice the rate (eight times the speed of its internal memory arrays), enabling higher bandwidth or peak data rates. With two transfers per cycle of a quadrupled clock, a 64-bit wide DDR3 module may achieve a transfer rate of up to 64 times the memory clock speed in megabytes per second (MB/s). With data being transferred 64 bits at a time per memory module, DDR3 SDRAM gives a transfer rate of (memory clock rate) × 4 (for bus clock multiplier) × 2 (for data rate) × 64 (number of bits transferred) / 8 (number of bits/byte). Thus with a memory clock frequency of 100 MHz, DDR3 SDRAM gives a maximum transfer rate of 6400 MB/s. In addition, the DDR3 standard permits chip capacities of up to 8 gigabits. Overview DDR3 memory provides a reduction in power consumption of 30% compared to DDR2 modules due to DDR3s 1.5 V supply voltage, compared to DDR2s 1.8 V or DDRs 2.5 V. The 1.5 V supply voltage works well with the 90 nanometer fabrication technology used in the original DDR3 chips. Some manufacturers further propose using "dual-gate" transistors to reduce leakage of current. According to JEDEC the maximum recommended voltage is 1.575 volts and should be considered the absolute maximum when memory stability is the foremost consideration, such as in servers or other mission critical devices. In addition, JEDEC states that memory modules must withstand up to 1.975 volts before incurring permanent damage, although they are not required to function correctly at that level. Comparison of memory modules for desktop PCs Two low voltage DDR3 standards have been introduced by JEDEC. (DIMM). The DDR3L standard operates with a default voltage of 1.35V, using at least 15% less power than standard voltage (1.5V) DDR3. Modules with DDR3L are labeled ’’PC3L’’, and examples include DDR3L‐800, DDR3L‐1066, DDR3L‐1333, and DDR3L‐1600. The DDR3U standard operates with a default voltage of 1.25V, and modules are labelled ’’PC3U’’. The main benefit of DDR3 comes from the higher bandwidth made possible by DDR3s 8-burst-deep prefetch buffer, in contrast to DDR2s 4-burst-deep or DDRs 2-burst-deep prefetch buffer.
DDR3 SDRAM 7 DDR3 modules can transfer data at a rate of 800–2133 MT/s using both rising and falling edges of a 400–1066 MHz I/O clock. Sometimes, a vendor may misleadingly advertise the I/O clock rate by labeling the MT/s as MHz. The MT/s is normally twice that of MHz by double sampling, one on the rising clock edge, and the other, on the falling. In comparison, DDR2s current range of data transfer rates is 400–1066 MT/s using a 200–533 MHz I/O clock, and DDRs range is 200–400 MT/s based on a 100–200 MHz I/O clock. High-performance graphics was an initial driver of such bandwidth requirements, where high bandwidth data transfer between framebuffers is required. Comparison of memory modules for portable/mobile PCs (SO-DIMM). DDR3 does use the same electric signaling standard as DDR and DDR2, Stub Series Terminated Logic, albeit at different timings and voltages. Specifically DDR3 uses SSTL_15. DDR3 prototypes were announced in early 2005. Products in the form of motherboards appeared on the market in June 2007 based on Intels P35 "Bearlake" chipset with DIMMs at bandwidths up to DDR3-1600 (PC3-12800). The Intel Core i7, released in November 2008, connects directly to memory rather than via a chipset. The Core i7 supports only DDR3. AMDs first socket AM3 Phenom II X4 processors, released in February 2009, were their first to support DDR3. DDR3 DIMMs have 240 pins and are electrically incompatible with DDR2. The two are prevented from being accidentally interchanged by different key notch positions on the DIMMs. DDR3 SO-DIMMs have 204 pins. GDDR3 memory, sometimes incorrectly referred to as "DDR3" due to its similar name, is an entirely different technology, as it is designed for use in graphics cards and technologically based on DDR2 SDRAM. Latencies While the typical latencies for a JEDEC DDR2 device were 5-5-5-15, some standard latencies for JEDEC DDR3 devices include 7-7-7-20 for DDR3-1066 and 8-8-8-24 for DDR3-1333. DDR3 latencies are numerically higher because the I/O bus clock cycles by which they are measured are shorter; the actual time interval is similar to DDR2 latencies (around 10 ns). There is some improvement because DDR3 generally uses more recent manufacturing processes, but this is not directly caused by the change to DDR3. As with earlier memory generations, faster DDR3 memory became available after the release of the initial versions. DDR3-2000 memory with 9-9-9-28 latency (9 ns) was available in time to coincide with the Intel Core i7 release. CAS latency of 9 at 1000 MHz (DDR3-2000) is 9 ns, while CAS latency of 7 at 667 MHz (DDR3-1333) is 10.5 ns. (CAS / Frequency (MHz)) × 1000 = X ns Example: (7 / 667) × 1000 = 10.4948 ns
DDR3 SDRAM 8 Extensions Intel Corporation officially introduced the eXtreme Memory Profile (XMP) Specification on March 23, 2007 to enable enthusiast performance extensions to the traditional JEDEC SPD specifications for DDR3 SDRAM. Modules JEDEC standard modules Standard Memory clock Cycle I/O bus Data rate Module Peak transfer Timings CAS name (MHz) time (ns) clock (MHz) (MT/s) name rate (MB/s) (CL-tRCD-tRP) latency (ns) DDR3-800D 100 10 400 800 PC3-6400 6400 5-5-5 12 1⁄2 DDR3-800E 6-6-6 15 DDR3-1066E 133⅓ 533⅓ 1066⅔ PC3-8500 8533⅓ 6-6-6 7 1⁄2 11 1⁄4 DDR3-1066F 7-7-7 13 1⁄8 DDR3-1066G 8-8-8 15 DDR3-1333F* 166⅔ 6 666⅔ 1333⅓ PC3-10600 10666⅔ 7-7-7 10 1⁄2 DDR3-1333G 8-8-8 12 DDR3-1333H 9-9-9 13 1⁄2 DDR3-1333J* 10-10-10 15 DDR3-1600G* 200 5 800 1600 PC3-12800 12800 8-8-8 10 DDR3-1600H 9-9-9 11 1⁄4 DDR3-1600J 10-10-10 12 1⁄2 DDR3-1600K 11-11-11 13 3⁄4 DDR3-1866J* 233⅓ 933⅓ 1866⅔ PC3-14900 14933⅓ 10-10-10 4 2⁄7 10 5⁄7 DDR3-1866K 11-11-11 11 11⁄14 DDR3-1866L 12-12-12 12 6⁄7 DDR3-1866M* 13-13-13 13 13⁄14 DDR3-2133K* 266⅔ 1066⅔ 2133⅓ PC3-17000 17066⅔ 11-11-11 3 3⁄4 10 5⁄16 DDR3-2133L 12-12-12 11 1⁄4 DDR3-2133M 13-13-13 12 3⁄16 DDR3-2133N* 14-14-14 13 1⁄8 * optional CL - Clock cycles between sending a column address to the memory and the beginning of the data in response tRCD - Clock cycles between row activate and reads/writes tRP - Clock cycles between row precharge and activate Fractional frequencies are normally rounded down, but rounding up to -667 is common due to superstition about the number 666. Note: All above listed are specified by JEDEC as JESD79-3D. All RAM data rates in-between or above these listed specifications are not standardized by JEDEC—often they are simply manufacturer optimizations using higher-tolerance or overvolted chips. Of these non-standard specifications, the highest reported speed reached was equivalent to DDR3-2544 as of May 2010. DDR3-xxx denotes data transfer rate, and describes raw DDR chips, whereas PC3-xxxx denotes theoretical bandwidth (with the last two digits truncated), and is used to describe assembled DIMMs. Bandwidth is calculated by taking transfers per second and multiplying by eight. This is because DDR3 memory modules transfer data on a bus that is 64 data bits wide, and since a byte comprises 8 bits, this equates to 8 bytes of data per transfer.
DDR3 SDRAM 9 In addition to bandwidth and capacity variants, modules can 1. Optionally implement ECC, which is an extra data byte lane used for correcting minor errors and detecting major errors for better reliability. Modules with ECC are identified by an additional ECC or E in their designation. For example: "PC3-6400 ECC", or PC3-8500E. 2. Be "registered", which improves signal integrity (and hence potentially clock rates and physical slot capacity) by electrically buffering the signals with a register, at a cost of an extra clock of increased latency. Those modules are identified by an additional R in their designation, whereas non-registered (a.k.a. "unbuffered") RAM may be identified by an additional U in the designation. PC3-6400R is a registered PC3-6400 module, PC3-6400R ECC is the same module but with additional ECC. 3. Be fully buffered modules, which are designated by F or FB and do not have the same notch position as other classes. Fully buffered modules cannot be used with motherboards that are made for registered modules, and the different notch position physically prevents their insertion. Feature summary DDR3 SDRAM components • Introduction of asynchronous RESET pin • Support of system-level flight-time compensation • On-DIMM mirror-friendly DRAM pinout • Introduction of CWL (CAS write latency) per clock bin • On-die I/O calibration engine • READ and WRITE calibration DDR3 modules • Fly-by command/address/control bus with on-DIMM termination • High-precision calibration resistors • Are not backwards compatible—DDR3 modules do not fit into DDR2 sockets; forcing them can damage the DIMM and/or the motherboard Technological advantages compared to DDR2 • Higher bandwidth performance, up to 2133 MT/s standardized • Slightly improved latencies as measured in nanoseconds • Higher performance at low power (longer battery life in laptops) • Enhanced low-power features Development and market penetration In May 2005, Desi Rhoden, chairman of the JEDEC Committee responsible for creating the DDR3 standard, stated that DDR3 had been under development for "about 3 years". DDR3 was launched in 2007, however sales were not expected to overtake DDR2 until the end of 2009, or possibly early 2010, according to Intel strategist Carlos Weissenberg, speaking during the early part of their roll-out in August 2008 (the same timescale for market penetration had been stated by market intelligence company DRAMeXchange over a year earlier in April 2007. and by Desi Rhoden in 2005 ) The primary driving force behind the increased usage of DDR3 has been new Core i7 processors from Intel and Phenom II processors from AMD, both of which have internal memory controllers: the latter recommends DDR3, the former requires it. IDC stated in January 2009 that DDR3 sales will account for 29 percent of the total DRAM units sold in 2009, rising to 72% by 2011.
DDR3 SDRAM 10 Successor JEDECs planned successor to DDR3 is DDR4, whose standard is currently in development. The primary benefits of DDR4 compared to DDR3 include a higher range of clock frequencies and data transfer rates and significantly lower voltage. Some manufacturers have already demonstrated DDR4 chips for testing purposes. References  McCloskey., Alan. "Research: DDR FAQ" (http:/ / www. ocmodshop. com/ ocmodshop. aspx?a=868). . Retrieved 2007-10-18.  JEDEC JESD 79-3B (http:/ / www. jedec. org/ download/ search/ JESD79-3B. pdf) (section 6, table 21 and section 7, table 23)  Jaci Chang Design Considerations for the DDR3 Memory Sub-system. Jedex, 2004, p. 4. http:/ / www. jedex. org/ images/ pdf/ samsung%20-%20jaci_chang. pdf  Soderstrom, Thomas (2007-06-05). "Pipe Dreams: Six P35-DDR3 Motherboards Compared" (http:/ / www. tomshardware. com/ 2007/ 06/ 05/ pipe_dreams_six_p35-ddr3_motherboards_compared/ ). Toms Hardware. .  Fink, Wesley (2007-07-20). "Super Talent & TEAM: DDR3-1600 Is Here!" (http:/ / www. anandtech. com/ printarticle. aspx?i=3045). AnandTech. .  "DocMemory" (2007-02-21). "Memory Module Picture 2007" (http:/ / www. simmtester. com/ page/ news/ showpubnews. asp?title=Memory+ Module+ Picture+ 2007& num=150). .  "JEDEC" (2010-12-01). "204-Pin DDR3 SDRAM SO-DIMM Specification" (http:/ / www. jedec. org/ download/ search/ 4_20_18R20A. pdf). .  Shilov, Anton (2008-10-29). "Kingston Rolls Out Industry’s First 2GHz Memory Modules for Intel Core i7 Platforms" (http:/ / www. xbitlabs. com/ news/ memory/ display/ 20081029141143_Kingston_Rolls_Out_Industry_s_First_2GHz_Memory_Modules_for_Intel_Core_i7_Platforms. html). Xbit Laboratories. . Retrieved 2008-11-02.  "Intel Extreme memory Profile (Intel XMP) DDR3 Technology" (http:/ / www. intel. com/ assets/ pdf/ whitepaper/ 319124. pdf). . Retrieved 2009-05-29.  DDR3 SDRAM STANDARD (http:/ / www. jedec. org/ standards-documents/ docs/ jesd-79-3d)  Kingstons 2,544 MHz DDR3 On Show at Computex (http:/ / news. softpedia. com/ news/ Kingston-s-2-544-MHz-DDR3-On-Show-at-Computex-143379. shtml)  Memory technology evolution: an overview of system memory technologies (http:/ / h20000. www2. hp. com/ bc/ docs/ support/ SupportManual/ c00256987/ c00256987. pdf) (PDF), Hewlett-Packard, p. 18,  "DDR3: Frequently Asked Questions" (http:/ / www. kingston. com/ channelmarketingcenter/ hyperx/ literature/ MKF_1223_DDR3_FAQ. pdf). . Retrieved 2009-08-18.  Sobolev, Vyacheslav (2005-05-31). "JEDEC: Memory standards on the way" (http:/ / www. digitimes. com/ news/ a20050530PR201. html). digitimes.com. . Retrieved 2011-04-28. "JEDEC is already well along in the development of the DDR3 standard, and we have been working on it for about three years now.... Following historical models, you could reasonably expect the same three-year transition to a new technology that you have seen for the last several generations of standard memory"  "IDF: "DDR3 wont catch up with DDR2 during 2009"" (http:/ / www. pcpro. co. uk/ news/ 220257/ idf-ddr3-wont-catch-up-with-ddr2-during-2009. html). pcpro.co.uk. 19 August 2008. . Retrieved 2009-06-17.  Bryan, Gardiner (April 17, 2007). "DDR3 Memory Wont Be Mainstream Until 2009" (http:/ / www. extremetech. com/ article2/ 0,2845,2115031,00. asp). extremetech.com. . Retrieved 2009-06-17.  Salisbury, Andy (2009-01-20). "New 50nm Process Will Make DDR3 Faster and Cheaper This Year" (http:/ / www. maximumpc. com/ article/ news/ new_50nm_process_will_make_ddr3_faster_and_cheaper_this_year). maximumpc.com. . Retrieved 2009-06-17.  "KH Kim Receives 2011 JEDEC Technical Recognition Award" (http:/ / www. jedec. org/ news/ jedec-awards-program/ kh-kim-2011-tr-award). jedec.org. . Retrieved 2011-07-31.  Shilov, Anton (August 16, 2010). "Next-Generation DDR4 Memory to Reach 4.266GHz – Report" (http:/ / www. xbitlabs. com/ news/ memory/ display/ 20100816124343_Next_Generation_DDR4_Memory_to_Reach_4_266GHz_Report. html). Xbitlabs.com. . Retrieved 2011-01-03.  "Samsung develops DDR4 memory with up to 40 percent better energy efficiency than DDR3" (http:/ / www. engadget. com/ 2011/ 01/ 04/ samsung-develops-ddr4-memory-with-up-to-40-percent-better-energy/ ). Engadget.com. January 4, 2011. . Retrieved 2011-07-31.
DDR SDRAM 11 DDR SDRAM Double data rate synchronous dynamic random access memory (DDR SDRAM) is a class of memory integrated circuits used in computers. DDR SDRAM (sometimes referred to as DDR1 SDRAM) has been superseded by DDR2 SDRAM and DDR3 SDRAM, neither of which are either forward or backward compatible with DDR Generic DDR-266 Memory in the 184pin DIMM SDRAM, meaning that DDR2 or DDR3 memory modules will not form work in DDR equipped motherboards, and vice versa. Compared to single data rate (SDR) SDRAM, the DDR SDRAM interface makes higher transfer rates possible by more strict control of the timing of the electrical data and clock signals. Implementations often have to use schemes such as phase-locked loops and self-calibration to reach the required timing accuracy.  The interface uses double pumping (transferring data on both the rising and falling edges of the clock signal) to lower the clock frequency. One advantage of keeping the clock frequency down is that it reduces the signal integrity requirements on the circuit board connecting the Corsair DDR-400 Memory with heat spreaders memory to the controller. The name "double data rate" refers to the fact that a DDR SDRAM with a certain clock frequency achieves nearly twice the bandwidth of a single data rate (SDR) SDRAM running at the same clock frequency, due to this double pumping. With data being transferred 64 bits at a time, DDR SDRAM gives a transfer rate of (memory bus clock rate) × 2 (for dual rate) × 64 (number of bits transferred) / 8 (number of bits/byte). Thus, with a bus frequency of 100 MHz, DDR SDRAM gives a maximum transfer rate of 1600 MB/s. "Beginning in 1996 and concluding in June 2000, JEDEC developed the DDR (Double Data Rate) SDRAM specification (JESD79)." JEDEC has set standards for data rates of DDR SDRAM, divided into two parts. The first specification is for memory chips, and the second is for memory modules.
DDR SDRAM 12 Specification standardsComparison of memory modules for desktop PCs Comparison of memory modules for (DIMM). portable/mobile PCs (SO-DIMM). Standard Memory clock I/O bus clock Data rate VDDQ Module Peak transfer Timings Cycle name (MHz)  (MHz) (MT/s) (V) name rate (MB/s) (CL-tRCD-tRP) time (ns) DDR-200 100 10 100 200 2.5±0.2 PC-1600 1600 DDR-266 133⅓ 7.5 133⅓ 266⅔ PC-2100 2133⅓ DDR-333 166⅔ 6 166⅔ 333⅓ PC-2700 2666⅔ DDR-400A 200 5 200 400 2.6±0.1 PC-3200 3200 2.5-3-3 DDR-400B 3-3-3 DDR-400C 3-4-4 Note: All above listed are specified by JEDEC as JESD79F. All RAM data rates in-between or above these listed specifications are not standardized by JEDEC—often they are simply manufacturer optimizations using tighter-tolerance or overvolted chips. The package sizes in which DDR SDRAM is manufactured are also standardized by JEDEC. There is no architectural difference between DDR SDRAM designed for different clock frequencies, for example, PC-1600, designed to run at 100 MHz, and PC-2100, designed to run at 133 MHz. The number simply designates the data rate at which the chip is guaranteed to perform, hence DDR SDRAM is guaranteed to run at lower (underclocking) and can possibly run at higher (overclocking) clock rates than those for which it was made. DDR SDRAM modules for desktop computers, commonly called DIMMs, have 184 pins (as opposed to 168 pins on SDRAM, or 240 pins on DDR2 SDRAM), and can be differentiated from SDRAM DIMMs by the number of notches (DDR SDRAM has one, SDRAM has two). DDR SDRAM for notebook computers, SO-DIMMs, have 200 pins, which is the same number of pins as DDR2 SO-DIMMs. These two specifications are notched very similarly and care must be taken during insertion if unsure of a correct match. DDR SDRAM operates at a voltage of 2.5 V, compared to 3.3 V for SDRAM. This can significantly reduce power consumption. Chips and modules with DDR-400/PC-3200 standard have a nominal voltage of 2.6 V.
DDR SDRAM 13 Increasing operating voltage slightly can increase maximum speed, at the cost of higher power dissipation and heating, and at the risk of malfunctioning or damage. Many new chipsets use these memory types in multi-channel configurations. Chip characteristics DRAM density Size of the chip are measured in megabits (1 megabyte = 8 megabits. For example, 256 Mbit means 32 MB.) Nearly all motherboards only recognize 1 GB modules if they contain 64M×8 chips (low density ). If 128M×4 (high density) 1 GB modules are used, they most likely will not work. The JEDEC standard allows 128M×4 only for slower buffered/registered modules designed specifically for some servers, but some generic manufacturers do not comply. Organization The notation like 64M×4 means that the memory matrix has 64 million (the product of banks x rows x columns) 4-bit storage locations. There are ×4, ×8, and ×16 DDR chips. The ×4 chips allow the use of advanced error correction features like Chipkill, memory scrubbing and Intel SDDC in server environments, while the ×8 and ×16 chips are somewhat less expensive. x8 chips are mainly used in desktops/notebooks but are making entry into the server market. There are normally 4 banks and only one row can be active in each bank. Module characteristics Ranks To increase memory capacity and bandwidth, chips are combined on a module. For instance, the 64-bit data bus for DIMM requires eight 8-bit chips, addressed in parallel. Multiple chips with the common address lines are called a memory rank. The term was introduced to avoid confusion with chip internal rows and banks. A memory module may bear more than one rank. The term sides would also be confusing because it incorrectly suggests the physical placement of chips on the module. All ranks are connected to the same memory bus (address+data). The Chip Select signal is used to issue commands to specific rank. Adding modules to the single memory bus creates additional electrical load on its drivers. To mitigate the resulting bus signaling rate drop and overcome the memory bottleneck, new chipsets employ the multi-channel architecture. Capacity Number of DRAM Devices The number of chips is a multiple of 8 for non-ECC modules and a multiple of 9 for ECC modules. Chips can occupy one side (single sided) or both sides (dual sided) of the module. The maximum number of chips per DDR module is 36 (9×4) for ECC and 32 (8x4) for non-ECC. ECC vs non-ECC Modules that have error correcting code are labeled as ECC. Modules without error correcting code are labeled non-ECC. Timings CAS latency (CL), clock cycle time (tCK), row cycle time (tRC), refresh row cycle time (tRFC), row active time (tRAS). Buffering registered (or buffered) vs unbuffered
DDR SDRAM 14 Packaging Typically DIMM or SO-DIMM Power consumption A test with DDR and DDR2 RAM in 2005 found that average power consumption appeared to be of the order of 1-3W per 512MB stick. Increases with clock rate, and when in use rather than idling. A manufacturer has produced calculators to estimate the power used by various types of RAM . Module and chip characteristics are inherently linked. Total module capacity is a product of one chips capacity by the number of chips. ECC modules multiply it by 8/9 because they use one bit per byte for error correction. A module of any particular size can therefore be assembled either from 32 small chips (36 for ECC memory), or 16(18) or 8(9) bigger ones. DDR memory bus width per channel is 64 bits (72 for ECC memory). Total module bit width is a product of bits per chip by number of chips. It also equals number of ranks (rows) multiplied by DDR memory bus width. Consequently a module with greater amount of chips or using ×8 chips instead of ×4 will have more ranks. Example: Variations of 1 GB PC2100 Registered DDR SDRAM module with ECC Module size (GB) Number of chips Chip size (Mbit) Chip organization Number of ranks 1 36 256 64M×4 2 1 18 512 64M×8 2 1 18 512 128M×4 + This example compares different real-world server memory modules with a common size of 1 GB. One should definitely be careful buying 1 GB memory modules, because all these variations can be sold under one price position without stating whether they are ×4 or ×8, single or dual ranked. There is a common belief that number of module ranks equals number of sides. As above data shows, this is not true. One can find 2-side/1-rank or 2-side/4-rank modules. One can even think of a 1-side/2-rank memory module having 16(18) chips on single side ×8 each, but its unlikely such a module was ever produced. History Double data rate (DDR) SDRAM specification From JEDEC Board Ballot JCB-99-70, and modified by numerous other Board Ballots, formulated under the cognizance of Committee JC-42.3 on DRAM Parametrics. Standard No. 79 Revision Log: • Release 1, June 2000 • Release 2, May 2002 • Release C, March 2003 – JEDEC Standard No. 79C. "This comprehensive standard defines all required aspects of 64Mb through 1Gb DDR SDRAMs with X4/X8/X16 data interfaces, including features, functionality, ac and dc parametrics, packages and pin assignments. This scope will subsequently be expanded to formally apply to x32 devices, and higher density devices as well."
DDR SDRAM 15 High density vs low density High density memory here means non-ECC 184 pin SDRAM memory. Organization PC3200 is DDR SDRAM designed to operate at 200 MHz using DDR-400 chips with a bandwidth of 3,200 MB/s. Because PC3200 memory is double-pumped, its effective clock rate is 400 MHz. 1 GB PC3200 non-ECC modules are usually made with sixteen 512 Mbit chips, 8 down each side (512 Mbits × 16 chips) / (8 bits (per byte)) = 1,024 MB. The individual chips making up a 1 GB memory module are usually organized with 64 Mbits and a data width of 8 bits for each chip, commonly expressed as 64M×8. Memory manufactured in this way is low density RAM and will usually be compatible with any motherboard specifying PC3200 DDR-400 memory. High density RAM In the context of the 1 GB non-ECC PC3200 SDRAM module, there is very little visually to differentiate low density from high density RAM. High density DDR RAM modules will, like their low density counterparts, usually be double-sided with eight 512 Mbit chips per side. The difference is that for each chip, instead of being organized in a 64M×8 configuration, it is organized with 128 Mbits and a data width of 4 bits, or 128M×4. High density memory modules are assembled using chips from multiple manufacturers. These chips come in both the familiar 22 × 10 mm (approx.) TSOP2 and smaller squarer 12 × 9 mm (approx.) FBGA package sizes. High density chips can be identified by the numbers on each chip. High density RAM devices were designed to be used in registered memory modules for servers. JEDEC standards do not apply to high-density DDR RAM in desktop implementations. JEDECs technical documentation, however, supports 128M×4 semiconductors as such that contradicts 128×4 being classified as high density. As such, high density is a relative term, which can be used to describe memory which is not supported by a particular motherboards memory controller. Alternatives DDR Bus Internal Prefetch Transfer Voltage DIMM SO-DIMM MicroDIMM SDRAM clock rate (min burst) Rate pins pins pins Standard (MHz) (MHz) (MT/s) DDR 100–200 100–200 2n 200–400 2.5/2.6 184 200 172 DDR2 200–533 100–266 4n 400–1066 1.8 240 200 214 DDR3 400–1066 100–266 8n 800–2133 1.5 240 204 214 DDR (DDR1) has been superseded by DDR2 SDRAM, which has some modifications to allow higher clock frequency, but operates on the same principle as DDR. Competing with DDR2 are Rambus XDR DRAM. DDR2 has become the standard, as XDR is lacking support. DDR3 SDRAM is a new standard that offers even higher performance and new features. DDRs prefetch buffer depth is 2 bits, while DDR2 uses 4 bits. Although the effective clock rates of DDR2 are higher than for DDR, the overall performance was no greater in the early implementations, primarily due to the high latencies of the first DDR2 modules. DDR2 started to be effective by the end of 2004, as modules with lower latencies became available.
DDR SDRAM 16 Memory manufacturers have stated that it is impractical to mass-produce DDR1 memory with effective clock rates in excess of 400 MHz (i.e. 400MT/s and 200MHz external Clock). DDR2 picks up where DDR1 leaves off, and is available at effective clock rates of 400 MHz and higher. RDRAM is a particularly expensive alternative to DDR SDRAM, and most manufacturers have dropped its support from their chipsets. DDR1 memorys prices have substantially increased since Q2 2008 while DDR2 prices are reaching an all-time low. In January 2009, 1 GB DDR1 is 2–3 times more expensive than 1 GB DDR2. High density DDR RAM will suit about 10% of PC motherboards on the market while low density will suit almost all motherboards on the PC Desktop market. MDDR MDDR is an acronym that some enterprises use for Mobile DDR SDRAM, a type of memory used in some portable electronic devices, like mobile phones, handhelds, and digital audio players. Through techniques including reduced voltage supply and advanced refresh options, Mobile DDR can achieve greater power efficiency. References  Northwest Logic DDR Phy datasheet (http:/ / www. nwlogic. com/ docs/ ASIC_DDR_PHY. pdf)  Memory Interfaces Data Capture Using Direct Clocking Technique (Xilinx application note) (http:/ / www. xilinx. com/ support/ documentation/ application_notes/ xapp701. pdf)  "The Love/Hate Relationship with DDR SDRAM Controllers" (http:/ / www. design-reuse. com/ articles/ 13805/ the-love-hate-relationship-with-ddr-sdram-controllers. html). .  Cycle time is the inverse of the I/O bus clock frequency; e.g., 1/(100 MHz) = 10 ns per clock cycle.  DOUBLE DATA RATE (DDR) SDRAM STANDARD (http:/ / www. jedec. org/ standards-documents/ docs/ jesd-79f)  "What is the difference between PC-2100 (DDR-266), PC-2700 (DDR-333), and PC-3200 (DDR-400)?" (http:/ / www. crucial. com/ support/ memory_speeds. aspx). Micron Technology, Inc.. .  Low Density vs High Density memory modules (http:/ / reviews. ebay. com/ Myth-Low-Density-vs-High-Density-memory-modules_W0QQugidZ10000000001236178)  Mike Chin: Power Distribution within Six PCs (http:/ / www. silentpcreview. com/ article265-page4. html)  Micron: RAM power calculators (http:/ / www. micron. com/ support/ dram/ power_calc. html)  http:/ / www. jedec. org/ download/ search/ JESD79F. pdf DOUBLE DATA RATE (DDR) SDRAM SPECIFICATION (Release F)  DDR2 vs. DDR: Revenge Gained (http:/ / www. xbitlabs. com/ articles/ memory/ display/ ddr2-ddr. html) External links • Official JEDEC website (http://www.jedec.org/)
DDR4 SDRAM 17 DDR4 SDRAM In computing, DDR4 SDRAM, an abbreviation for double data rate type four synchronous dynamic random-access memory, is a type of dynamic random-access memory (DRAM) with a high bandwidth interface currently under development and expected market release in 2012. As a "next generation" successor to DDR3 SDRAM, it is one of several variants The first DDR4 memory module was manufactured by Samsung and announced in of DRAM used since the early 1970s. It is January 2011. not directly compatible with any earlier type of random access memory (RAM) due to different signaling voltages, timings, physical interface and other factors. DDR4 itself is a DRAM interface specification. Its primary benefits compared to DDR3 include a higher range of clock frequencies and data transfer rates (2133–4266 MT/s compared to DDR3s 800–2133  ) and significantly lower voltage (1.2 - 1.05 V for DDR4, compared to 1.5 – 1.2 V for DDR3). DDR4 also anticipates a change in topology – it discards dual and triple channel approaches in favor of point-to-point where each channel in the memory controller is connected to a single module.  Switched memory banks are also an anticipated option for servers. Development and market history Standards body JEDEC began working on a successor to DDR3 around 2005, about 2 years before the launch of DDR3 in 2007.  The high-level architecture of DDR4 was planned for completion in 2008 and, as of 2007, was said by JEDECs Future DRAM task group chairman to be "on time". The final specification is expected in the second half of 2011, shortly before DDR4s commercial launch. Some advance information was published in 2007, and a guest speaker from Qimonda provided further public details in a presentation at the August 2008 San Francisco Intel Developer Forum (IDF).    DDR4 was described as involving a 30 nm process at 1.2 volts, with bus frequencies of 2133 MT/s "regular" speed and 3200 MT/s "enthusiast" speed, and reaching market in 2012, before transitioning to 1 volt in 2013.  Subsequently, further details were revealed at MemCon 2010, Tokyo (a computer memory industry event), at which a presentation by a JEDEC director titled "Time to rethink DDR4"  with a slide titled "New roadmap: More realistic roadmap is 2015" led some websites to report that the introduction of DDR4 was probably or definitely  delayed until 2015. However, DDR4 test samples were announced in line with the original schedule in early 2011 at which time manufacturers began to advise that large scale commercial production and release to market was scheduled for 2012. DDR4 is expected to represent 5% of the DRAM market in 2013, and to reach mass market adoption and 50% market penetration around 2015; the latter is comparable with the approximately 5 years taken for DDR3 to achieve mass market transition over DDR2. In part, this is because changes required to other components would impact all other parts of computer systems, which would need to be updated to work with DDR4. In February 2009, Samsung validated 40 nm DRAM chips, considered a "significant step" towards DDR4 development since in 2009, DRAM chips were only beginning to migrate to a 50 nm process. In January 2011, Samsung announced the completion and release for testing of a 2 GB DDR4 DRAM module based on a process between 30 and 39 nm. It has a maximum data transfer rate of 2133 Mb/s at 1.2 V, uses pseudo open drain technology (adapted from graphics DDR memory ) and draws 40% less power than an equivalent DDR3
DDR4 SDRAM 18 module.   Three months later in April 2011, Hynix announced the production of 2 GB DDR4 modules at 2400 MT/s, also running at 1.2 V on a process between 30 and 39 nm (exact process unspecified), adding that it anticipated commencing high volume production in the second half of 2012. Semiconductor processes for DDR4 are expected to transition to sub-30 nm at some point between late 2012 and 2014.  Technical description The new chips are expected to run at 1.2 V or less,  versus the 1.5 V of DDR3 chips, and have in excess of 2 billion data transfers per second. They are expected to be introduced at clock speeds of 2133 MT/s, estimated to rise to a potential 4266 MT/s  and lowered voltage of 1.05 V  by 2013. DDR4 is likely to be initially commercialized using 32 – 36 nm processes, and according to a roadmap by PC Watch (Japan) and comments by Samsung, as 4 Gbit chips.  Increased memory density was also anticipated, possibly using TSV ("through-silicon via") or other 3D stacking processes.    The DDR4 specification will include standardized 3D stacking "from the start" according to JEDEC. X-bit Labs commented that "as a result DDR4 memory chips with very high density will become relatively inexpensive". Prefetch an 8n prefetch with bank groups, including the use of two or four selectable bank groups. DDR4 also anticipates a change in topology. It discards dual and triple channel approaches (used since the original first generation DDR ) in favor of point-to-point where each channel in the memory controller is connected to a single module.  This mirrors the trend also seen in the earlier transition from PCI to PCI Express, where parallelism was moved from the interface to the controller, and is likely to simplify timing in modern high-speed data buses. Switched memory banks are also an anticipated option for servers.  The minimum clock speed of 2133 MT/s was said to be due to progress made in DDR3 speeds which, being likely to reach 2133 Mb/s, left little commercial benefit to specifying DDR4 below this speed.  Techgage interpreted Samsungs January 2011 engineering sample as having CAS latency of 13 clock cycles, described as being comparable to the move from DDR2 to DDR3. In 2008, concerns were raised in the book Wafer Level 3-D ICs Process Technology that non-scaling analog elements such as charge pumps and voltage regulators, and additional circuitry "have allowed significant increases in bandwidth but they consume much more die area". Examples include CRC error-detection, on-die termination, burst hardware, programmable pipelines, low impedence, and increasing need for sense amps (attributed to a decline in bits per bitline due to low voltage). The authors noted that as a result, the amount of die used for the memory array itself has declined over time from 70-80% with SDRAM and DDR1, to 38% for DDR3 and potentially to less than 30% for DDR4. References  Shilov, Anton (August 16, 2010). "Next-Generation DDR4 Memory to Reach 4.266GHz – Report" (http:/ / www. xbitlabs. com/ news/ memory/ display/ 20100816124343_Next_Generation_DDR4_Memory_to_Reach_4_266GHz_Report. html). Xbitlabs.com. . Retrieved 2011-01-03.  後藤 弘茂 ("Gotou Shigehiro"). "メモリ4Gbps時代へと向かう次世代メモリDDR4 ("Towards Next-Generation 4Gbps DDR4 Memory")" (http:/ / pc. watch. impress. co. jp/ docs/ column/ kaigai/ 20100816_387444. html). 2010-08-16. PC Watch (Japan). . Retrieved 2011-04-25. ( English translation (http:/ / translate. google. com/ translate?js=y& prev=_t& hl=en& ie=UTF-8& layout=1& eotf=1& u=http:/ / pc. watch. impress. co. jp/ docs/ column/ kaigai/ 20100816_387444. html& sl=ja& tl=en))  Swinburne, Richard (2010-08-26). "DDR4: What we can Expect" (http:/ / www. bit-tech. net/ hardware/ memory/ 2010/ 08/ 26/ ddr4-what-we-can-expect/ 1). bit-tech.net. . Retrieved 2011-04-28. – Page 1 (http:/ / www. bit-tech. net/ hardware/ memory/ 2010/ 08/ 26/ ddr4-what-we-can-expect/ 2) – – Page 3 (http:/ / www. bit-tech. net/ hardware/ memory/ 2010/ 08/ 26/ ddr4-what-we-can-expect/ 3)  Sobolev, Vyacheslav (2005-05-31). "JEDEC: Memory standards on the way" (http:/ / www. digitimes. com/ news/ a20050530PR201. html). digitimes.com. . Retrieved 2011-04-28. "Initial investigations have already started on memory technology beyond DDR3. JEDEC always has about three generations of memory in various stages of the standardization process: current generation, next generation, and future."
DDR4 SDRAM 19  "DDR3: Frequently asked questions" (http:/ / www. kingston. com/ channelmarketingcenter/ hyperx/ literature/ MKF_1223-1_DDR3_FAQ. pdf). Kingston Technology. . Retrieved 2011-04-28. ""DDR3 memory launched in June 2007""  Valich, Theo (2007-05-02). "DDR3 launch set for May 9th" (http:/ / www. theinquirer. net/ inquirer/ news/ 1016272/ ddr3-launch-set-may-9th). The Inquirer. . Retrieved 2011-04-28.  Hammerschmidt, Christoph (2007-08-29). "Non-volatile memory is the secret star at JEDEC meeting" (http:/ / www. eetimes. com/ electronics-news/ 4189215/ Non-volatile-memory-is-the-secret-star-at-JEDEC-meeting?pageNumber=1). eetimes.com. . Retrieved 2011-04-28.  "Hynix produces its first DDR4 modules" (http:/ / www. behardware. com/ news/ 11425/ hynix-produces-its-first-ddr4-modules. html). behardware.com. 2011-04-05. . Retrieved 2011-04-26.  "DDR4 – the successor to DDR3 memory" (http:/ / www. h-online. com/ newsticker/ news/ item/ IDF-DDR4-the-successor-to-DDR3-memory-736983. html). The "H" (h-online.com). 2008-08-21. . Retrieved 2011-04-28. "The JEDEC standardisation committee cited similar figures around one year ago"  Graham-Smith, Darien (2008-08-19). "IDF: DDR3 wont catch up with DDR2 during 2009" (http:/ / www. pcpro. co. uk/ news/ 220257/ idf-ddr3-wont-catch-up-with-ddr2-during-2009). PC Pro. . Retrieved 2011-04-28.  Volker Risska (Volker Rißka) (2008-08-21). "IDF: DDR4 als Hauptspeicher ab 2012 ["Intel Developer Forum: DDR4 as the main memory from 2012" (http:/ / www. computerbase. de/ news/ hardware/ arbeitsspeicher/ 2008/ august/ idf-ddr4-als-hauptspeicher-ab-2012/ )"]. computerbase.de. . Retrieved 2011-04-28. ( English (http:/ / translate. google. com/ translate?hl=en& sl=de& tl=en& u=http:/ / www. computerbase. de/ news/ hardware/ arbeitsspeicher/ 2008/ august/ idf-ddr4-als-hauptspeicher-ab-2012/ ))  Novakovic, Nebojsa (2008-08-19). "Qimonda: ddr3 moving forward" (http:/ / www. theinquirer. net/ inquirer/ news/ 1012591/ qimonda-ddr3-moving-forward). The Inquirer. . Retrieved 2011-04-28.  Gervasi, Bill. "Time to rethink DDR4" (http:/ / discobolusdesigns. com/ personal/ 20100721a_gervasi_rethinking_ddr4. pdf). July 2010. Discobolus Designs. . Retrieved 2011-04-29.  "DDR4-Speicher kommt wohl später als bisher geplant ("DDR4 memory is probably later than previously planned")" (http:/ / www. heise. de/ newsticker/ meldung/ DDR4-Speicher-kommt-wohl-spaeter-als-bisher-geplant-1060545. html). heise.de. 2010-08-17. . Retrieved 2011-04-29. ( English (http:/ / translate. google. com/ translate?hl=en& sl=de& tl=en& u=http:/ / www. heise. de/ newsticker/ meldung/ DDR4-Speicher-kommt-wohl-spaeter-als-bisher-geplant-1060545. html))  Nilsson, Lars-Göran (2010-08-16). "DDR4 not expected until 2015" (http:/ / semiaccurate. com/ 2010/ 08/ 16/ ddr4-not-expected-until-2015/ ). semiaccurate.com. . Retrieved 2011-04-29.  By annihilator (2010-08-18). "DDR4 memory in Works, Will reach 4.266GHz" (http:/ / wccftech. com/ 2010/ 08/ 18/ ddr4-memory-works-reach-4266ghz/ ). wccftech.com. . Retrieved 2011-04-29.  Gruener, Wolfgang (February 4, 2009). "Samsung hints to DDR4 with first validated 40 nm DRAM" (http:/ / www. tgdaily. com/ content/ view/ 41316/ 139/ ). tgdaily.com. . Retrieved 2009-06-16.  Jansen, Ng (January 20, 2009). "DDR3 Will be Cheaper, Faster in 2009" (http:/ / www. dailytech. com/ DDR3+ Will+ be+ Cheaper+ Faster+ in+ 2009/ article13977. htm). dailytech.com. . Retrieved 2009-06-17.  "Samsung Develops Industrys First DDR4 DRAM, Using 30nm Class Technology" (http:/ / www. samsung. com/ us/ business/ semiconductor/ newsView. do?news_id=1202). Samsung. 2011-04-11. . Retrieved 26 April 2011.  Perry, Ryan (2011-01-06). "Samsung Develops the First 30nm DDR4 DRAM" (http:/ / techgage. com/ news/ samsung_develops_the_first_30nm_ddr4_dram/ ). techgage.com. . Retrieved 2011-04-29.  "Samsung Develops Industrys First DDR4 DRAM, Using 30nm Class Technology" (http:/ / www. samsung. com/ us/ business/ semiconductor/ newsView. do?news_id=1202). Samsung. 2011-01-04. . Retrieved 2011-03-13.  http:/ / www. techspot. com/ news/ 41818-samsung-develops-ddr4-memory-up-to-40-more-efficient. html  "Diagram: Anticipated DDR4 timeline" (http:/ / translate. googleusercontent. com/ translate_c?hl=en& ie=UTF-8& sl=ja& tl=en& u=http:/ / pc. watch. impress. co. jp/ img/ pcw/ docs/ 387/ 444/ html/ kaigai-09. jpg. html& prev=_t& rurl=translate. google. com& twu=1& usg=ALkJrhiDMjWRSrDnnnL4mro50bRDlxQlVw). 2010-08-146. PC Watch (Japan). . Retrieved 2011-04-25. (Linked from cited PC Watch article dated Aug 16 2010)  Looking forward to DDR4 (http:/ / www. pcpro. co. uk/ news/ 220257/ idf-ddr3-wont-catch-up-with-ddr2-during-2009. html)  DDR3 successor (http:/ / www. heise-online. co. uk/ news/ IDF-DDR4-the-successor-to-DDR3-memory--/ 111367)  "IDF: DDR4 memory targeted for 2012" (http:/ / www. hardware-infos. com/ news. php?news=2332) (in German). hardware-infos.com. . Retrieved 2009-06-16. English translation (http:/ / translate. google. com/ translate?hl=en& sl=de& u=http:/ / www. hardware-infos. com/ news. php?news=2332& ei=bi44Sv_wBouZjAfVzYyjDQ& sa=X& oi=translate& resnum=1& ct=result& prev=/ search?q=http:/ / www. hardware-infos. com/ news. php%3Fnews%3D2332& hl=en& safe=off& num=100)  "JEDEC Announces Broad Spectrum of 3D-IC Standards Development" (http:/ / www. jedec. org/ news/ pressreleases/ jedec-announces-broad-spectrum-3d-ic-standards-development). JEDEC. 2011-03-17. . Retrieved 26 April 2011.  "Main Memory: DDR3 & DDR4 SDRAM" (http:/ / www. jedec. org/ category/ technology-focus-area/ main-memory-ddr3-ddr4-sdram). jedec.org. . Retrieved 2011-09-29.  See for example • Biostar I86PE-A4 (http:/ / www. biostar. com. tw/ app/ en/ mb/ content. php?S_ID=235) (Pentium 4) "Support Dual Channel DDR 200/266/333/400 MHz"
DDR4 SDRAM 20 • Gigabyte GA-8SRX (http:/ / www. pchardware. ro/ press/ preview. php?id=64) (Pentium 4, review dated December 2001) "DDR333 or... DDR266... optimized for... dual channel DDR memory technology" • PCA-6289 specification (http:/ / www. comprel. it/ schede_prodotto/ data_sheet/ PCA-6289_ds. pdf) (Intel Xeon) "Dual channel DDR200/266 SDRAM" • AMD 2001 white paper: "White paper: AMD Eighth-Generation Processor Architecture" (http:/ / www. datasheetarchive. com/ datasheet-pdf/ 021/ DSA00367679. html). 2001-10-16. AMD. p. 4. . Retrieved 2011-04-28. "The Hammer microarchitecture [codename for Athlon 64 or Opteron] incorporates a dual-channel DDR DRAM controller... The controller will be initially designed to support PC1600, PC2100, and PC2700 DDR memory" (DDR1 memory types)"  Tan, Gutmann and Reif (2008). Wafer Level 3-D ICs Process Technology (http:/ / books. google. com/ books?id=fhen8HeoC1AC& pg=PA278& dq=ddr4+ sdram& hl=en& ei=iLa2Ta6LAY_Cswa1m9DNDQ& sa=X& oi=book_result& ct=result& resnum=13& ved=0CIcBEOgBMAw#v=onepage& q=ddr4 sdram& f=false). Springer. pp. 278 (sections 12.3.4 – 12.3.5). .
DVD 21 DVD DVD DVD-R read/write side Media type Optical disc Capacity 4.7 GB (single-sided, single-layer – common) 8.5–8.7 GB (single-sided, double-layer) 9.4 GB (double-sided, single-layer) 17.08 GB (double-sided, double-layer – rare) Read mechanism 650 nm laser, 10.5 Mbit/s (1×) Write mechanism 10.5 Mbit/s (1×) Standard    DVD Forums DVD Books and DVD+RW Alliance specifications A DVD is an optical disc storage media format, invented and developed by Philips, Sony, Toshiba, and Panasonic in 1995. DVD originally stood for Digital Versatile Disk, or Digital Video Disk. The acronym was dropped after DVD proved to have more uses than just storing video content. DVDs offer higher storage capacity than Compact Discs while having the same dimensions. Pre-recorded DVDs are mass-produced using molding machines that physically stamp data onto the DVD. Such discs are known as DVD-ROM, because data can only be read and not written nor erased. Blank recordable DVDs (DVD-R and DVD+R) can be recorded once using optical disc recording technologies and supported by optical disc drives and DVD recorders and then function as a DVD-ROM. Rewritable DVDs (DVD-RW, DVD+RW, and DVD-RAM) can be recorded and erased multiple times. DVDs are used in DVD-Video consumer digital video format and in DVD-Audio consumer digital audio format, as well as for authoring AVCHD discs. DVDs containing other types of information may be referred to as DVD data discs. History Before the advent of DVD and Blu-ray, the Video CD (abbreviated as VCD, and also known as View CD, Compact Disc digital video) became the first format for distributing digitally encoded films on standard 120 mm optical discs. (its predecessor CD Video used analog video encoding). VCD was on the market in 1993. In the same year, two new optical disc storage formats were being developed. One was the Multimedia Compact Disc (MMCD), backed by Philips and Sony, and the other was the Super Density (SD) disc, supported by Toshiba, Time Warner, Matsushita
DVD 22 Electric, Hitachi, Mitsubishi Electric, Pioneer, Thomson, and JVC. Representatives of the SD camp approached IBM, asking for advice on the file system to use for their disc as well as seeking support for their format for storing computer data. Alan E. Bell, a researcher from IBMs Almaden Research Center got that request and also learned of the MMCD development project. Wary of being caught in a repeat of the costly videotape format war between VHS and Betamax in the 1980s, he convened a group of computer industry experts, including representatives from Apple, Microsoft, Sun, Dell, and many others. This group was referred to as the Technical Working Group, or TWG. The TWG voted to boycott both formats unless the two camps agreed on a single, converged standard. Lou Gerstner, president of IBM, was recruited to apply pressure on the executives of the warring factions. Eventually, the computer companies won the day, and a single format, now called DVD, was agreed upon. The TWG also collaborated with the Optical Storage Technology Association (OSTA) on the use of their implementation of the ISO-13346 file system (known as Universal Disc Format) for use on the new DVDs. Philips and Sony decided it was in their best interest to avoid another format war over their Multimedia Compact Disc, and agreed to unify with companies backing the Super Density Disc to release a single format with technologies from both. The specification was mostly similar to Toshiba and Matsushitas Super Density Disc, except for the dual-layer option (MMCD was single-sided and optionally dual-layer, whereas SD was single-layer but optionally double-sided) and EFMPlus modulation. EFMPlus was chosen because of its great resilience to disc damage, such as scratches and fingerprints. EFMPlus, created by Kees Immink (who also designed EFM), is 6% less efficient than the modulation technique originally used by Toshiba, which resulted in a capacity of 4.7 GB, as opposed to the original 5 GB. The result was the DVD specification, finalized for the DVD movie player and DVD-ROM computer applications in December 1995. The DVD Video format was first introduced by Toshiba in Japan in November 1996, in the United States in March 1997 (test marketed), in Europe in October 1998, and in Australia in February 1999. In May 1997, the DVD Consortium was replaced by the DVD Forum, which is open to all other companies. Specifications DVD specifications created and updated by the DVD Forum are published as so-called DVD Books (e.g. DVD-ROM Book, DVD-Audio Book, DVD-Video Book, DVD-R Book, DVD-RW Book, DVD-RAM Book, DVD-AR Book, DVD-VR Book, etc.).   Some specifications for mechanical, physical and optical characteristics of DVD optical discs can be downloaded as freely available standards from the ISO website. Also, the DVD+RW Alliance publishes competing DVD specifications such as DVD+R, DVD+R DL, DVD+RW or DVD+RW DL. These DVD formats are also ISO standards.    Some of DVD specifications (e.g. for DVD-Video) are not publicly available and can be obtained only from the DVD Format/Logo Licensing Corporation for a fee of US $5000.  Every subscriber must sign a non-disclosure agreement as certain information in the DVD Book is proprietary and confidential.
DVD 23 Etymology The official DVD charter documents specify that the basis of the DVD name stems from the term "digital versatile disc" . Usage in the present day varies, with Digital Versatile Disc, Digital Video Disc, and DVD being the most common. DVD was originally used as an initialism for the unofficial term digital videodisk. A newsgroup FAQ written by Jim Taylor (a prominent figure in the industry) claims that four years later, in 1999, the DVD Forum stated that the format name was simply the three letters "DVD" and did not stand for anything. The DVD Forum website has a section called "DVD Primer" in which the answer to the question, "What does DVD mean?" reads, "The keyword is versatile. Digital Versatile Discs provide superb video, audio and data storage and access—all on one disc." Identification (MID) The DVD is made of a spiral groove read or written starting at the center. The form of the groove encodes unalterable identification data known as Media Identification Code (MID). The MID contains data such as the manufacturer and model, byte capacity, allowed data rates (also known as speed), etc. Design As a movie delivery medium DVD was adopted by movie and home entertainment distributors to replace the ubiquitous VHS tape as the primary means of distributing films to consumers in the home entertainment marketplace. DVD was chosen for its superior ability to reproduce moving pictures and sound, for its superior durability, and for its interactivity. Interactivity had proven to be a feature which consumers, especially collectors, favored when the movie studios had released their films on laser disk. When the price point for a laser disk at approximately $100 per disk moved to $20 per disk at retail, this luxury feature became available for mass consumption. Simultaneously, the movie studios decided to change their home entertainment release model from a rental Comparison of several forms of disk storage showing tracks (not-to-scale); green denotes start and red denotes end. model to a for purchase model, and large * Some CD-R(W) and DVD-R(W)/DVD+R(W) recorders operate in ZCLV, CAA numbers of dvds were sold. or CAV modes, but most work in Constant linear velocity (CLV) mode. At the same time, a demand for interactive design talent and services was created. Movies in the past had uniquely designed title sequences. Suddenly every movie being released required information architecture and interactive design components that matched the films tone and were at the quality level that Hollywood demanded for its product.
DVD 24 New DVD releases are released weekly by all major studios. DVDs are typically released on Tuesdays of every week. With the advent of Blu-ray releases, studios now rely on both Blu-ray and DVDs to supplement their revenue for a particular movie. As an interactive medium DVD as a format had two qualities at the time that were not available in any other interactive medium: 1. Enough capacity and speed to provide high quality, full motion video and sound, and 2. low cost delivery mechanism provided by consumer products retailers who quickly moved to sell their players for under $200 and eventually for under $50 at retail. In addition, the medium itself was small enough and light enough to mail using general first class postage. Almost overnight, this created a new business opportunity and model for business innovators like Netflix to re-invent the home entertainment distribution model. It also opened up the opportunity for business and product information to be inexpensively provided on full motion video through direct mail. Capacity Capacity and nomenclature  SS = single-sided, DS = double-sided, SL = single-layer, DL = dual-layer Designation Sides Layers Diameter Capacity (total) (cm) (GB) (GiB)  SS SL 1 1 8 1.46 1.36 DVD-1 DVD-2 SS DL 1 2 8 2.66 2.47 DVD-3 DS SL 2 2 8 2.92 2.72 DVD-4 DS DL 2 4 8 5.32 4.95 DVD-5 SS SL 1 1 12 4.70 4.37 DVD-9 SS DL 1 2 12 8.54 7.95 DVD-10 DS SL 2 2 12 9.40 8.75  DS SL+DL 2 3 12 13.24 12.33 DVD-14 DVD-18 DS DL 2 4 12 17.08 15.90 Capacity and nomenclature of (re)writable discs Designation Sides Layers Diameter Capacity (total) (cm) (GB) (GiB) DVD-R SS SL (1.0) 1 1 12 3.95 3.68 DVD-R SS SL (2.0) 1 1 12 4.70 4.37 DVD-RW SS SL 1 1 12 4.70 4.37 DVD+R SS SL 1 1 12 4.70 4.37 DVD+RW SS SL 1 1 12 4.70 4.37 DVD-R DS SL 2 2 12 9.40 8.75 DVD-RW DS SL 2 2 12 9.40 8.75 DVD+R DS SL 2 2 12 9.40 8.75
DVD 25 DVD+RW DS SL 2 2 12 9.40 8.75 DVD-RAM SS SL 1 1 8 1.46 1.36* DVD-RAM DS SL 2 2 8 2.65 2.47* DVD-RAM SS SL (1.0) 1 1 12 2.58 2.40 DVD-RAM SS SL (2.0) 1 1 12 4.70 4.37 DVD-RAM DS SL (1.0) 2 2 12 5.16 4.80 DVD-RAM DS SL (2.0) 2 2 12 9.40 8.75* The basic types of DVD (12 cm diameter, single-sided or homogeneous double-sided) are referred to by a rough approximation of their capacity in gigabytes. In draft versions of the specification, DVD-5 indeed held five gigabytes, but some parameters were changed later on as explained above, so the capacity decreased. Other formats, those with 8 cm diameter and hybrid variants, acquired similar numeric names with even larger deviation. The 12 cm type is a standard DVD, and the 8 cm variety is known as a MiniDVD. These are the same sizes as a standard CD and a mini-CD, respectively. The capacity by surface (MiB/cm2) varies from 6.92 MiB/cm2 in the DVD-1 to 18.0 MiB/cm2 in the DVD-18. As with hard disk drives, in the DVD realm, gigabyte and the symbol Scan of a DVD 4.5 capacity disk 9 GB are usually used in the SI sense (i.e., 10 , or 1,000,000,000 bytes). For distinction, gibibyte (with symbol GiB) is used (i.e., 10243 (230), or 1,073,741,824 bytes). Each DVD sector contains 2,418 bytes of data, 2,048 bytes of which are user data. There is a small difference in storage space between + and - (hyphen) formats: Size comparison: a 12 cm DVD+RW and a 19 cm pencil.
DVD 26 Capacity differences of writable DVD formats Type Sectors Bytes kB MB GB KiB MiB GiB DVD-R SL 2,298,496 4,707,319,808 4,707,319.808 4,707.320 4.707 4,596,992 4,489.250 4.384 DVD+R SL 2,295,104 4,700,372,992 4,700,372.992 4,700.373 4.700 4,590,208 4,482.625 4.378 DVD-R DL 4,171,712 8,543,666,176 8,543,666.176 8,543.666 8.544 8,343,424 8,147.875 7.957 DVD+R DL 4,173,824 8,547,991,552 8,547,991.552 8,547.992 8.548 8,347,648 8,152.000 7.961 Technology DVD uses 650 nm wavelength laser diode light as opposed to 780 nm for CD. This permits a smaller pit to be etched on the media surface compared to CDs (0.74 µm for DVD versus 1.6 µm for CD), allowing in part for DVDs increased storage capacity. In comparison, Blu-ray Disc, the successor to the DVD format, uses a wavelength of 405 nm, and one dual-layer disc has a 50 GB storage capacity. Writing speeds for DVD were 1×, that is, 1,385 kB/s (1,353 KiB/s), in the first drives and media models. More recent models, at 18× or 20×, DVD-RW Drive operating with the protective have 18 or 20 times that speed. Note that for CD drives, 1× means cover removed. 153.6 kB/s (150 KiB/s), about one-ninth as swift.  DVD drive speeds Drive speed Data rate  ~Write time (min) (Mbit/s) (MB/s) (MiB/s) SL DL 1× 11.08 1.39 1.32 57 103 2× 22.16 2.77 2.64 28 51 2.4× 26.59 3.32 3.17 24 43 2.6× 28.81 3.60 3.43 22 40 4× 44.32 5.54 5.28 14 26 6× 66.48 8.31 7.93 9 17 8× 88.64 11.08 10.57 7 13 10× 110.80 13.85 13.21 6 10 12× 132.96 16.62 15.85 5 9 16× 177.28 22.16 21.13 4 6 18× 199.44 24.93 23.78 3 6 20× 221.60 27.70 26.42 3 5 22× 243.76 30.47 29.06 3 5 24× 265.92 33.24 31.70 2 4
DVD 27 Internal mechanism of a drive This mechanism is shown right side up; the disc would sit on top of it. The laser and optical system scans the underside of the disc. With reference to the photo, just to the right of image center is the disc spin motor, a gray cylinder, with its gray centering hub and black resilient drive ring on top. A clamp (not in the photo, retained in the drives cover), pulled down by a magnet, clamps the disc when this mechanism rises, after the disc tray stops moving inward. This motor has an external rotor – every visible part of it spins. The gray metal chassis is shock-mounted at its four corners to reduce sensitivity to external shocks, and to reduce drive noise when running fast. The soft shock mount grommets are just below the brass-colored washers at the four corners (the left one is obscured). Running through Internal mechanism of a DVD-ROM Drive. See text for details. those grommets are screws to fasten them to the black plastic frame thats underneath. Two parallel precision guide rods that run between upper left and lower right in the photo carry the "sled", the moving optical read-write head. As shown, this "sled" is close to, or at the position where it reads or writes at the edge of the disc. A dark gray disc with two holes on opposite sides has a blue lens surrounded by silver-colored metal. This is the lens thats closest to the disc; it serves to both read and write by focusing the laser light to a very small spot. It is likely that this disc rotates half a turn to position a different set of optics (the other "hole") for CDs vs. DVDs. Under the disc is an ingenious actuator comprising permanent magnets and coils that move the lens up and down to maintain focus on the data layer. As well, the actuator moves the lens slightly toward and away from the spin-motor spindle to keep the spot on track. Both focus and tracking are relatively quite fast and very precise. The same actuator rotates the lens mount half a turn as described. To select tracks (or files) as well as advancing the "sled" during continuous read or write operations, a stepping motor rotates a coarse-pitch leadscrew to move the "sled" throughout its total travel range. The motor, itself, is the gray cylinder just to the left of the most-distant shock mount; its shaft is parallel to the support rods. The leadscrew, itself, is the rod with evenly-spaced darker details; these are the helical groove that engages a pin on the "sled". The irregular orange material is flexible etched copper foil supported by thin sheet plastic; these are "flexible printed circuits" that connect everything to the electronics (which is not shown).
DVD 28 DVD recordable and rewritable HP initially developed recordable DVD media from the need to store data for backup and transport. DVD recordables are now also used for consumer audio and video recording. Three formats were developed: DVD-R/RW, DVD+R/RW (plus), and DVD-RAM. DVD-R is available in two formats, General (650 nm) and Authoring (635 nm), where Authoring discs may be recorded with encrypted content but General discs may not. Although most DVD writers can nowadays write the DVD+R/RW and DVD-R/RW formats (usually denoted by "DVD±RW" and/or the existence of both the DVD Forum logo and the DVD+RW Alliance logo), the "plus" and the "dash" formats use different writing Sony DVD Read & Rewritable specifications. Most DVD readers and players will play both kinds of discs, although older models can have trouble with the "plus" variants. Some first generation DVD players would cause damage to DVD±R/RW/DL when attempting to read them. Dual-layer recording Dual-layer recording (sometimes also known as double-layer recording) allows DVD-R and DVD+R discs to store significantly more data—up to 8.54 gigabytes per disc, compared with 4.7 gigabytes for single-layer discs. Along with this, DVD-DLs have slower write speeds as compared to ordinary DVDs and when played on a DVD player a slight transition can sometimes be seen between the layers. DVD-R DL was developed for the DVD Forum by Pioneer Corporation; DVD+R DL was developed for the DVD+RW Alliance by Philips and Mitsubishi Kagaku Media (MKM). A dual-layer disc differs from its usual DVD counterpart by employing a second physical layer within the disc itself. The drive with dual-layer capability accesses the second layer by shining the laser through the first semitransparent layer. In some DVD players, the layer change can exhibit a noticeable pause, up to several seconds. This caused some viewers to worry that their dual-layer discs were damaged or defective, with the end result that studios began listing a standard message explaining the dual-layer pausing effect on all dual-layer disc packaging. DVD recordable discs supporting this technology are backward-compatible with some existing DVD players and DVD-ROM drives. Many current DVD recorders support dual-layer technology, and the price is now comparable to that of single-layer drives, although the blank media remain more expensive. The recording speeds reached by dual-layer media are still well below those of single-layer media. There are two modes for dual-layer orientation. With Parallel Track Path (PTP), used on DVD-ROM, both layers start at the inside diameter (ID) and end at the outside diameter (OD) with the lead-out. With Opposite Track Path (OTP), used on many Digital Video Discs, the lower layer starts at the ID and the upper layer starts at the OD, where the other layer ends; they share one lead-in and one lead-out. DVD-Video DVD-Video is a standard for storing and distributing video/audio content on DVD media. The format went on sale in Japan on November 1, 1996, in the United States on March 1, 1997, in Europe on October 1, 1998 and in Australia on February 1, 1999. DVD-Video became the dominant form of home video distribution in Japan when it first went on sale in 1996, but did not become the dominant form of home video distribution in the United States until June 15, 2003, when weekly DVD-Video in the United States rentals began outnumbering weekly VHS cassette rentals, reflecting the rapid adoption rate of the technology in the U.S. marketplace.  Currently, DVD-Video is