8085 MICROPROCESSOR

38,497 views
37,894 views

Published on

8085 MICROPROCESSOR

Published in: Education
4 Comments
27 Likes
Statistics
Notes
No Downloads
Views
Total views
38,497
On SlideShare
0
From Embeds
0
Number of Embeds
5
Actions
Shares
0
Downloads
2,574
Comments
4
Likes
27
Embeds 0
No embeds

No notes for slide

8085 MICROPROCESSOR

  1. 1. UNIT - IThe 8085 Microprocessor Prepared By,Mr.R-THANDAIAH PRABU M.E., Lecturer - ECE thandaiah@gmail.com
  2. 2. RE TU 5 CH 08 R AR IT EC 8 O SS TI ON CE & RA P RO GU RO FIMIC C ON PI N
  3. 3. The 8085 and Its Busses• The 8085 is an 8-bit general purpose microprocessor that can address 216 =64K Byte of memory.• It has 40 pins and uses +5V for power. It can run at a maximum frequency of 3 MHz. – The pins on the chip can be grouped into 6 groups: • Address Bus. • Data Bus. • Control and Status Signals. • Power supply and frequency. • Externally Initiated Signals. • Serial I/O ports. SJCET
  4. 4. Intel 8085 Pin Configuration SJCET
  5. 5. Functional Blocks• Registers • Increment/ Decrement• ALU Address Latch• Instruction Decoder • Interrupt Control• Address Buffer • Serial I/O Control• Address/Data Buffer • Timing and control circuitry SJCET
  6. 6. Registers • General purpose Registers • Temporary Registers • Special Purpose Register • 16 Bit Registers SJCET
  7. 7. The Flags register – There is also the flags register whose bits are affected by the arithmetic & logic operations. • S-sign flag – The sign flag is set if bit D7 of the accumulator is set after an arithmetic or logic operation. CY – 0- + Ve 1- -Ve • Z-zero flag P – Set if the result of the ALU operation is 0. Otherwise is reset. This flag is affected by operations on the accumulator as well as other AC registers. (DCR B). • AC-Auxiliary Carry Z – This flag is set when a carry is generated from bit D3 and passed to D4 . This flag is used only internally for BCD operations.S • P-Parity flag – After an ALU operation if the result has an even no of 1’s the p- flag is set. Otherwise it is cleared. So, the flag can be used to indicate even parity. • CY-carry flag – CY = carry is set when result generates a carry. Also a borrow flag. SJCET
  8. 8. PROGRAM COUNTER (PC) AND STACK POINTER (SP)• These are two 16-bit registers used to hold memory addresses.• PC: – The function of the PC is to point to the memory address from which the next byte is to be fetched. – When a byte (machine code) is being fetched, the program counter is incremented by one to point to the next memory location.• SP: – It points to a memory location in R/W memory, called the stack. – The beginning of the stack is defined by loading a 16-bit address in the stack pointer. – The PC will automatically update when calling to /returning from Subroutines.
  9. 9. The ALU• In addition to the arithmetic & logic circuits, the ALU includes the accumulator, which is part of every arithmetic & logic operation.• Also, the ALU includes a temporary register used for holding data temporarily during the execution of the operation. This temporary register is not accessible by the programmer. SJCET
  10. 10. The Address and Data Busses• The address bus has 8 signal lines A8 – A15 which are unidirectional.• The other 8 address bits are multiplexed (time shared) with the 8 data bits. – So, the bits AD0 – AD7 are bi-directional and serve as A0 – A7 and D0 – D7 at the same time. • During the execution of the instruction, these lines carry the address bits during the early part, then during the late parts of the execution, they carry the 8 data bits. – In order to separate the address from the data, we can use a latch to save the value before the function of the bits changes. SJCET
  11. 11. INCREMENT/ DECREMENT ADDRESS LATCH Interrupt Control: Fetch, Decode & execute RST 5.5, RST 6.5, RST 7.5, TRAP, & INTR Serial I/O Control SOD & SID Timing and Control Circuitry Its control fetching, decoding, execution SJCET
  12. 12. Frequency Control Signals• There are 3 important pins in the frequency control group. – X0 and X1 are the inputs from the crystal or clock generating circuit. • The frequency is internally divided by 2. – So, to run the microprocessor at 3 MHz, a clock running at 6 MHz should be connected to the X0 and X1 pins. – CLK (OUT): An output clock pin to drive the clock of the rest of the system.• We will discuss the rest of the control signals as we get to them. SJCET
  13. 13. The Control and Status Signals • There are 4 main control and status signals. These are: • ALE: Address Latch Enable. This signal is a pulse that become 1 when the AD0 – AD7 lines have an address on them. It becomes 0 after that. This signal can be used to enable a latch to save the address bits from the AD lines. • RD: Read. Active low indicates that the data must be read from the selected memory location or I/O port via data bus. • WR: Write. Active low indicates that the data must be written into the selected memory location or I/O port via data bus.. • IO/M: This signal specifies whether the operation is a memory operation (IO/M=0) or an I/O operation (IO/M=1). • S1 and S0 : Status signals to specify the kind of operation being performed .Usually un-used in small systems. SJCET
  14. 14. GE UA N G A M L A LY GR B O M R S SE PA SJCET
  15. 15. ADDRESSING MODES• IMMEDIATE MVI A,05(H) LXI H,0050(H)• DIRECT LDA 0208(H)• REGISTER MOV B,C ADD B• REGISTER INDIRECT LDAX B• INHERENT HLT STC(SET CARRY FLAG) SJCET
  16. 16. NOTATIONS MEANING M Memory location pointed by HL reg pair r 8- bit register rp 16-bit register rs Source register rd Destination register addr 16-bit address SJCET
  17. 17. Data Transfer Group• MVI r, data (8- Bit)• MVI M, data (8- Bit)• MOV rd, rs• MOV M, rs• MOV rd, M• LXI rp, data (16 bit)• STA addr• LDA addr• SHLD addr• LHLD addr• STAX addr• LDAX rp• XCHG SJCET
  18. 18. • MOV Rd,Rs MOV B,C• MVI R,8bit MVI A,05H• LXI Rp,16bit LXI B,2050• MOV R,M MOV D,M• MOV M,R MOV M,E• LDA 16 bit LDA 8005H• STA 16 bit STA 8006H• LDAx Rp LDAx B• STAX Rp STAX D SJCET
  19. 19. ARITHEMATIC GROUP• ADD r • SUB r • INR r• ADD M • SUB M • INR M• ADI data (8) • SUI data • INX rp• ADC r • SBB r • DCR r• ADC M • SBB M • DCR M• ACI data (8) • SBI data • DCX rp• DAD rp • DAA SJCET
  20. 20. • ADD R ADD B• ADI 8bit ADI 59H• SUB R SUB C• SUI 8bit SUI 37H• INR R INR D• DCR R DCR B• INR M INR M• DCR M DCRB M• INX Rp INX B• DCX Rp SJCET
  21. 21. LOGIC GROUP• ANA r • ORI data• ANA M • CMP r• ANI data • CMP M• XRA r • CPI data• XRA M • STC• XRI data • CMC• ORA r • CMA• ORA M SJCET
  22. 22. • ANA R/M ANA D• ANI 8bit• ORA R/M ORA C• ORI 8bit• XRA R/M XRA D• XRI 8bit• RLC• RAL• RRC• RAR• CMP R/M SJCET
  23. 23. BRANCH GROUP• JUMP INSTRUCTION• CALL and RETURN INSTRUCTION• RESTART INSTRUCTION SJCET
  24. 24. • JMP 16bit Address• JZ 16bit Address• JNZ 16bit Address• JC 16bit Address• JNC 16bit Address• HLT Stop processing and wait• NOP Don’t perform anything - delay SJCET
  25. 25. STACK OPERATION I/O & CONTROL GROUP• PUSH• POP• RESTART RST n SJCET
  26. 26. INSTRUCTION FORMATS 1 BYTE INSTRUCTION 2 BYTE INSTRUCTION 3 BYTE INSTRUCTION JMP 6200H ---MOV A,B --- 78H MVI B, 02 --- 06H 02 C3H 00 62 SJCET
  27. 27. INSTRUCTION SET SJCET
  28. 28. INSTUCTION SET MODIFICATION CONTROL MOVEMENT INSTUCTIONS INSTRUCTIONS INSTUCTIONS GROUP-0 GROUP – 1 GROUP – 2 GROUP – 3B I/O & DATA DATA ARITHEMATI GROUP -3A MACHINE TRANSFER TRANSFER C & LOGIC BRANCH CONTROLMVI,INR,DCR,LDA, JNZ,JNC,JC, HLT,ENABLE AND,ADD, STA,RAR,CMC, JZ etc., ,DISABLE, CMA,STC,DAA, MOV OR,XOR etc., PROGRAM INTRDAD,LDAX,SHLD, CONTROL PROCESS INX,RIM ETC., CONTROL SJCET
  29. 29. BYTE ORGANIZATION GROUP - 00 0 R R R I0 I0 I0 GROUP - 10 1 R R R S S S GROUP - 21 0 A1 A1 A1 S S S GROUP - 3 1 1 Cb Cb Cb B0 B0 B0 SJCET
  30. 30. CODE FOR RECEIVING AND SENDING REGISTERS/PAIRSRESSISTERS AADDRESS CODE RESSISTERS ADDRESS CODE B 000 B–C 00 C 001 D 010 D–E 01 E 011 H 100 H–L 10 L 101 M 110 SP 11 A 111 SJCET
  31. 31. INFORMATION OPERATIONS (I0 I0 I0) ADDRESS OPERATIONI0 I0 I00 0 0 NOT USED0 0 1 IMMETIATE OPERATION REGISTER PAIR0 1 0 LOAD / STORE0 1 1 INCREMENT/ DECREMENT REGISTER PAIR1 0 0 INCREMENT SINGLE REGISTER1 0 1 DECREMENT SINGLE REGISTER1 1 0 IMMETIATE OPERATION ON SINGLE REGISTER1 1 1 REGISTER SHIFTING SJCET
  32. 32. ARITHEMATIC AND LOGICAL OPERATIONS (A1 A1 A1) ADDRESS OPERATIONA1 A1 A10 0 0 ADD0 0 1 ADD WITH CARRY (ADC)0 1 0 SUBTRACT (SUB)0 1 1 SUBTRACT WITH BORROW (SBB)1 0 0 LOGICAL AND1 0 1 EXCLUSIVE OR (X-OR)1 1 0 LOGICAL OR (OR)1 1 1 COMPARE SJCET
  33. 33. CONDITIONS OF BRANCH ( Cb Cb Cb) ADDRESS OPERATIONCb Cb Cb0 0 0 IF NOT ZERO (JNZ)0 0 1 IF ZERO (JZ)0 1 0 IF NO CARRY(JNC)0 1 1 IF CARRY (JC)1 0 0 IF ODD PARITY (JPO)1 0 1 IF EVEN PARITY (JPE)1 1 0 WAS IT POSITIVE (JP)1 1 1 WAS IT NEGATIVE (JM) SJCET
  34. 34. BRANCH OPERATIONS (B0 B0 B0) ADDRESS OPERATIONB0 B0 B00 0 0 CONDITIONAL RETURN0 0 1 SIMPLE RETURN0 1 0 CONDITIONAL JUMP0 1 1 UNCONDITIONAL JUMP1 0 0 CONDITIONAL CALL1 0 1 SIMPLE CALL1 1 0 SPECIAL A/L OPERATIONS1 1 1 SPECIAL UNCONDITIONAL JUMPS SJCET
  35. 35. MVI B, BYTE0 0 R R R I0 I0 I0 0 0 0 0 0 1 1 0 MOV B,C0 1 R R R S S S0 1 0 0 0 0 0 1 ADD B 1 0 A1 A1 A1 S S S 1 0 0 0 0 0 0 0 SJCET
  36. 36. Static RAM Dynamic RAMStatic RAM contains less memory cells Dynamic RAM contains more memoryper unit area cells as compare to static RAM per unit areaIt has less access time, hence faster Its access time is greater than staticmemories RAMsStatic RAM consists of number of flip- Dynamic RAM stores the data as aflops. Each flip-flop stores one bit charge on the capacitor. It consists of MOSFET and the capacitor for each cellRefreshing circuitry is not required Refreshing circuitry is required to maintain the charge on the capacitor after every few millisecondsCost is more Cost is less SJCET
  37. 37. MACHINE CYCLES AND THEIR TIMING OF 8085: Timing Diagram is a graphical representation. It represents the execution time taken by each instruction in a graphical format. The execution time is represented in T-states. Instruction Cycle: The time required to execute an instruction is called instruction cycle. Machine Cycle: The time required to access the memory or input/output devices is called machine cycle. T-State: The machine cycle and instruction cycle takes multiple clock periods. A portion of an operation carried out in one system clock period is called as T-state.
  38. 38. • Clock SignalThe 8085 divides the clock frequency provided at x1 and x2 inputs by 2 which is called operating frequency. Rise time and fall time T-State 1 Clock cycle SJCET
  39. 39. • Single SignalSingle signal status is represented by a line. It may have status either logic 0 or logic 1 or tri-state Logic 1 Tri stateLogic 0 SJCET
  40. 40. • Group of signalsGroup of signals is also called a bus.Eg: Address bus, data bus Valid state State changes State changes Tri state Tri state SJCET
  41. 41. SJCET
  42. 42. Instruction cycle Instruction cycle Machine cycle1 Machine cycle1 Machine cycle 2 Machine cycle 2 Machine cycle 5 Machine cycle 5T – State 1 T – State 2 T – State 3T – State 1 T – State 2 T – State 3 T – State 6 T – State 6 SJCET
  43. 43. The 8085 microprocessor has 5 basic machine cycles. They are 1.Opcode fetch cycle (4T) 2.Memory write cycle (3 T) 3.I/O read cycle (3 T) 4.Memory read cycle (3 T) 5.I/O write cycle (3 T)
  44. 44. • Each instruction of the 8085 processor consists of one to five machine cycles, i.e., when the 8085 processor executes an instruction, it will execute some of the machine cycles in a specific order.• The processor takes a definite time to execute the machine cycles. The time taken by the processor to execute a machine cycle is expressed in T-states.• One T-state is equal to the time period of the internal clock signal of the processor.• The T-state starts at the falling edge of a clock.• In this time, the first, 3 T-states are used for fetching the opcode from memory and the remaining T-states are used for internal operations by the processor.
  45. 45. Opcode Fetch Machine Cycle• The first step of executing any instruction is the Opcode fetch cycle. – In this cycle, the microprocessor brings in the instruction’s Opcode from memory. • To differentiate this machine cycle from the very similar “memory read” cycle, the control & status signals are set as follows: – IO/M=0, s0 and s1 are both 1. – This machine cycle has four T-states. • The 8085 uses the first 3 T-states to fetch the opcode. • T4 is used to decode and execute it. – It is also possible for an instruction to have 6 T-states in an opcode fetch machine cycle. SJCET
  46. 46. Timing Diagram for Opcode Fetch Machine Cycle SJCET
  47. 47. Memory Read Machine Cycle of 8085:• The memory read machine cycle is executed by the processor to read a data byte from memory.• The processor takes 3T states to execute this cycle.• The instructions which have more than one byte word size will use the machine cycle after the opcode fetch machine cycle. SJCET
  48. 48. Memory Read Machine Cycle• The memory read machine cycle is exactly the same as the opcode fetch except: – It only has 3 T-states – The s0 signal is set to 0 instead. SJCET
  49. 49. The Memory Read Machine Cycle – To understand the memory read machine cycle, let’s study the execution of the following instruction: • MVI A, 32 – In memory, this instruction looks like: • The first byte 3EH represents the opcode for loading a byte into the accumulator (MVI A), the second byte is the data to be loaded. – The 8085 needs to read these two bytes from memory before it can execute the instruction. Therefore, it will need at least two machine cycles. – The first machine cycle is the opcode fetch discussed earlier. – The second machine cycle is the Memory Read Cycle. 2000H 3E 2001H 32 SJCET
  50. 50. Timing Diagram for Memory Read Machine Cycle SJCET
  51. 51. Memory Write Machine Cycle of 8085:• The memory write machine cycle is executed by the processor to write a data byte in a memory location.• The processor takes, 3T states to execute this machine cycle. SJCET
  52. 52. The Memory Write Operation• In a memory write operation: – The 8085 places the address (2065H) on the address bus – Identifies the operation as a memory write (IO/M=0, s1=0, s0=1). – Places the contents of the accumulator on the data bus and asserts the signal WR. – During the last T-state, the contents of the data bus are saved into the memory location. SJCET
  53. 53. Timing Diagram for Memory Write Machine Cycle SJCET
  54. 54. SJCET
  55. 55. INTERFACING I/O AND PERIPHERAL DEVICES:1. For data transfer from input device to processor the following operations are performed.• The input device will load the data to the port.• When the port receives a data, it sends message to the processor to read the data.• The processor will read the data from the port.• After a data have been read by the processor the input device will load the next data into the port. SJCET
  56. 56. 2. For data transfer from processor to output device the followingoperations are performed.•The processor will load the data to the port.•The port will send a message to the output device to read the data.•The output device will read the data from the port.•After the data have been read by the output device the processor can loadthe next data to the port.•The various INTEL 110 port devices are 8212, 8155/8156, 8255, 8355and 8755.•8212•The 8212 is a 24 pin IC.•It consists of eight number of D-type latches.•It has 8-input lines DI1 to DI8 and 8-output lines DO1 to DO8•The 8212 can be used as an input or output device•It has two selecting device DS1 (low) and DS2. SJCET
  57. 57. SJCET
  58. 58. SJCET
  59. 59. Dimensions of Memory • Memory is usually measured by two numbers: its length and its width (Length X Width). » The length is the total number of locations. » The width is the number of bits in each location.– The length (total number of locations) is a function of the number of address lines. # of memory locations = 2( # of address lines) • So, a memory chip with 10 address lines would have 210 = 1024 locations (1K) • Looking at it from the other side, a memory chip with 4K locations would need Log2 4096=12 address lines
  60. 60. The 8085 and Memory• The 8085 has 16 address lines. That means it can address 216 = 64K memory locations. – Then it will need 1 memory chip with 64 k locations, or 2 chips with 32 K in each, or 4 with 16 K each or 16 of the 4 K chips, etc.• how would we use these address lines to control the multiple chips?
  61. 61. SJCET
  62. 62. To communicate with other devices two interfacingdevices are usedMemory InterfacingI/o InterfacingMEMORY INTERFACING• Require:Select a chipIdentify the registerEnable the appropriate buffer SJCET
  63. 63. Memory interfacing techniques • Techniques Absolute Decoding / Full Decoding Linear Decoding / Partial Decoding SJCET
  64. 64. Absolute Decoding / Full Decoding SJCET
  65. 65. I/O Intefacing• I/O devices can be interfaced to an 8085I/O Mapped I/OMemory Mapped I/O SJCET
  66. 66. I/O Mapped I/O• IN addr8the content of port is moved to A- Register• OUT addr8The content of A register is moved to port SJCET
  67. 67. Memory Mapped I/O• Mov r,m LDA addr• LHLD addr ADD M• XRA M MOV m,r• STA addr SJCET
  68. 68. Comparison of memory mapped I/O and Peripheral I/O Characteristics Memory Mapped I/O Mapped Device address 16 bit 8 bit Control signals for I/O MEMW MEMR IOR IOW Instruction available STA, LDA, LDAX, IN & OUT STAX etc., Data Transfer between any register Between I/O and and I/O accumulator Maximum no of I/O 64k Independent Execution speed 13T for STA &LDA 10T Hardware More hardware require Less hardware SJCET

×