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Design and Implementation of VLSI Systems                (EN1600)                lecture02
Impact of doping on silicon resistivity                                                  silicon                          ...
What happens if we sandwich p & n types?                                            A           Al                        ...
PN-junction regions of operation                             A forward biasIn reverse bias, the width   decreases the pote...
nMOS and pMOS transistors Each transistor consists of a stack of a conducting gate, an insulating layer of silicon dioxide...
nMOS transistor                                            Source    Gate   Drain                                         ...
nMOS pass ‘0’ more strongly than ‘1’                   Source   Gate   Drain                                             P...
pMOS transistor                                                Source   Gate   Drain                                  Poly...
pMOS pass ‘1’ more strongly than ‘0’                          Source   Gate   Drain            Polysilicon               S...
An nMOS and pMOS make up an inverter           pMOS + nMOS = CMOS
More CMOS gates                                        B                                  A                               ...
3-input NANDs  What are the advantages of CMOS circuit style?
Series-Parallel Combinations
What are the transistor schematics of theNOR gate?
AOI
Transmission gate
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Vlsi Lecture02

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Transcript of "Vlsi Lecture02"

  1. 1. Design and Implementation of VLSI Systems (EN1600) lecture02
  2. 2. Impact of doping on silicon resistivity silicon 4.995×1022 atoms in cm3 Resistivity 3.2 × 105 Ωcm dope with dope with phosphorous boron → or arsenic → p-type n-type1 atom in billion ⇒ 88.6 Ωcm 1 atom in billion ⇒ 266.14 Ωcm1 atom in million ⇒ 0.114 Ωcm 1 atom in million ⇒ 0.344 Ωcm1 atom in thousand ⇒ 0.00174 Ωcm 1 atom in thousand ⇒ 0.00233 Ωcm ⇒ Electrons are more mobile/faster than holes
  3. 3. What happens if we sandwich p & n types? A Al p n B One-dimensional representation  In equilibrium, the drift and diffusion components of current are balanced; therefore the net current flowing across the junction is zero.
  4. 4. PN-junction regions of operation A forward biasIn reverse bias, the width decreases the potentialof the depletion region drop across theincreases. The diode acts junction. As a result,as voltage-controlled the magnitude of the electric field decreasescapacitor. and the width of the depletion region narrows.
  5. 5. nMOS and pMOS transistors Each transistor consists of a stack of a conducting gate, an insulating layer of silicon dioxide and a semiconductor substrate (body or bulk) nMOS transistor pMOS transistor Source Gate Drain Source Gate Drain Polysilicon Polysilicon SiO2 SiO2 polysilicon gate W n+ n+ p+ p+ tox p bulk Si L SiO2 gate oxide n bulk Si n+ n+ (good insulator, εox = 3.9) p-type bodyBody is typically grounded Body is typically at supply voltage
  6. 6. nMOS transistor Source Gate Drain Polysilicon SiO2 n+ n+ p bulk Sig=0: When the gate is at a low voltage (VGS < VTN):  p-type body is at low voltage  source and drain-junctions diodes are OFF  transistor is OFF, no current flowsg=1: When the gate is at a high voltage (VGS ≥ VTN):  negative charge attracted to body  inverts a channel under gate to n-type  transistor ON, current flows, transistor can be viewed as a resistor
  7. 7. nMOS pass ‘0’ more strongly than ‘1’ Source Gate Drain Polysilicon SiO2 n+ n+ p bulk Si• Why does ‘1’ pass degraded?
  8. 8. pMOS transistor Source Gate Drain Polysilicon SiO2 p+ p+ n bulk Si g=0: When the gate is at a low voltage (VGS < VTP):  positive charge attracted to body  inverts a channel under gate to p-type  transistor ON, current flows g=1: When the gate is at a high voltage (VGS ≥ VTP):  negative charge attracted to body  source and drain junctions are OFF  transistor OFF, no current flows
  9. 9. pMOS pass ‘1’ more strongly than ‘0’ Source Gate Drain Polysilicon SiO2 p+ p+ n bulk Si • Why does ‘0’ pass degraded?
  10. 10. An nMOS and pMOS make up an inverter pMOS + nMOS = CMOS
  11. 11. More CMOS gates B A B F = AB 0What is this gate function? What’s wrong about this design?
  12. 12. 3-input NANDs What are the advantages of CMOS circuit style?
  13. 13. Series-Parallel Combinations
  14. 14. What are the transistor schematics of theNOR gate?
  15. 15. AOI
  16. 16. Transmission gate

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