Lecture21

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Lecture21

  1. 1. Design and Implementation of VLSI Systems (EN1600) Lecture 21: Dynamic Combinational Circuit DesignS. Reda EN160 SP’07
  2. 2. Dynamic logic • Dynamic gates uses a clocked pMOS pullup • Two modes: precharge and evaluate 2 2/3 φ 1 A Y Y Y 1 A 4/3 A 1 Static Pseudo-nMOS Dynamic • Dynamic circuit operation is divided into two modes: precharge and evaluate φ Precharge Evaluate Precharge YS. Reda EN160 SP’07
  3. 3. What if the input is ON during precharge? • What if pulldown network is ON during precharge? – Contention arises because both pMOS and nMOS will be ON • Use series evaluation transistor to prevent fight. precharge transistor φ φ φ Y Y Y A inputs inputs f f foot footed unfootedS. Reda EN160 SP’07
  4. 4. Logic effort for dynamic circuits Very fast with very low logical effortS. Reda EN160 SP’07
  5. 5. Dynamic circuits have a problem: Monotonicity requirement violates monotonicity during evaluation A precharge transistor φ Y φ Precharge Evaluate Precharge A Y foot Output should rise but does not • Dynamic gates require monotonically rising inputs during evaluation – 0→0 – 0→1 – 1→1 – But not 1 → 0S. Reda EN160 SP’07
  6. 6. Implications of Monotonicity • But dynamic gates produce monotonically falling outputs during evaluation • Illegal for one dynamic gate to drive another!S. Reda EN160 SP’07
  7. 7. Domino Logic • Follow dynamic stage with inverting static gate – Dynamic / static pair is called domino gate – Produces monotonic outputs φ Precharge Evaluate Precharge domino AND W W X Y Z X A Y B C φ Z dynamic static φ φ NAND inverter φ φ A W X A X H Y = B H Z B Z C CS. Reda EN160 SP’07
  8. 8. Domino optimizations • Each domino gate triggers next one, like a string of dominos toppling over • Gates evaluate sequentially but precharge in parallel • Thus evaluation is more critical than precharge • HI-skewed static stages can perform logic φ S0 S1 S2 S3 D0 D1 D2 D3 Y H φ S4 S5 S6 S7 D4 D5 D6 D7 8-input multiplexer built from two 4-input dynamic multiplexersS. Reda EN160 SP’07
  9. 9. Dual-Rail Domino • Domino only performs noninverting functions: – AND, OR but not NAND, NOR, or XOR • Dual-rail domino solves this problem – Takes true and complementary inputs – Produces true and complementary outputs sig_h sig_l Meaning 0 0 Precharged 0 1 ‘0’ 1 0 ‘1’ 1 1 invalidS. Reda EN160 SP’07
  10. 10. Leakage problems • Dynamic node floats high during evaluation – Transistors are leaky (IOFF ≠ 0) – Dynamic value will leak away over time – Formerly miliseconds, now nanoseconds! • Use keeper to hold dynamic node – Must be weak enough not to fight evaluation weak keeper φ 1 k X H Y A 2 2S. Reda EN160 SP’07
  11. 11. Charge sharing • Dynamic gates suffer from charge sharing φ φ Y A x CY A Cx Y B=0 Charge sharing noise x • Solution: add secondary precharge transistors • Typically need to precharge every other node • Big load capacitance CY helps as well secondary φ precharge Y transistor A x BS. Reda EN160 SP’07
  12. 12. Domino Summary • Domino logic is attractive for high-speed circuits – 1.5 – 2x faster than static CMOS – But many challenges: Monotonicity, leakage, charge sharing, noise, and high dynamic power • Widely used in high-performance microprocessors Circuit Families  Static CMOS  Ratioed Circuits  Cascode Voltage Switch Logic  Pass-transistor Circuits  Dynamic CircuitsS. Reda EN160 SP’07

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