Pcb carolina scg_2010

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  • 1. Models and Metrics: Get Your Signal Integrity Simulations Right Tim Coyle President Signal Consulting Group LLC PCB Carolina 2010 Signal Consulting Group LL Copyright 2010
  • 2. Consulting Software Education www.siconsultant.com www.sharksim.com www.xrosstalkmag.com 2
  • 3. Outline  Why Signal Integrity Matters  How Simulations Provides Solutions  Why You Need Simulation Metrics  Good Simulations Have Good Models 3
  • 4. Why Do We Need to Simulate?  Faster edge rates makes interconnect look like transmission lines  Increased frequencies starts to put digital design into RF world  Ex. insertion loss  Simulations give you a window into what’s going on in a system  Used at the right times it can save you from costly board spins and failing products 4
  • 5. Is This Waveform Good? VCC VIH VIL 5 Waveform at Receiver
  • 6. Need Metrics To Analyze Waveform 1. Overshoot: Too much voltage could damage component 2. Ringback: Signal must be kept out of threshold region (timing errors) 3. Settling Time: Too long and interferes with next transition (ISI) 4. Non-Monotonic Edge: Can cause timing errors (especially if clock) 1 3 VCC 2 Noise margin VIH 4 Noise margin VIL 2 1 3 Waveform at Receiver 6
  • 7. Metrics Include Timing and Noise  Setup Time: Data has to be valid for a minimum amount of time before clock edge  Hold Time: Data has to be valid for a minimum amount of time after clock edge Clock Data Setup Hold 7
  • 8. Need Quality Models for Simulation Single LC Ladder Multiple LC Ladder Segments RLGC Values Per Unit Length Lumped Distributed Distributed (via algorithims) 8
  • 9. Simulation Solves Two Problems  Performance  Cost 9
  • 10. Case Study: Clock Termination  Vendor guideline states to use 33 Ohm series termination on clock line But what if simulation shows you don’t need it? 10
  • 11. Case Study Results: Clock Termination  Vendor guideline stated to use 33 Ohm series termination on clock line for a clean signal  Simulations showed for YOUR design it wasn’t needed  1 Resistor = $0.05 USD  10 Resistors per PCB = $0.50 USD  1 Million PCBs = $500,00.00 USD SAVED Simulations Help You Reduce Costs 11
  • 12. Case Study: PCB Stackup  Use Sunstone Circuits PCBexpress Quickturn stack-up  Choose standard 6 Layer PCB Build (62 mil thickness)  Should you route critical signal microstrip or stripline? signal ground signal signal power 12 signal
  • 13. Case Study: Microstrip Zo vs. H 13
  • 14. Case Study: Microstrip Results  10 mil trace width gives 50 Ohms  Er variation +/- 0.1 small enough to ignore  H variation +/- 0.7mils is biggest factor on Zo  Do we want H to be large or small?  Answer: Crosstalk 14
  • 15. NEXT Crosstalk  NEXT=Near End Crosstalk=Backward Crosstalk  Vb = Backward crosstalk voltage  NEXT is induced voltage on the victim and travels in opposite direction of aggressor  Vb waveform will reflect off of victim TX and affect victim RX OR full Vb onto victim RX if bi-directional bus Aggressor Signal Aggressor TX RX Vb TX RX Victim 15 Reflected Signal
  • 16. NEXT Characteristics Vb Trise 2Td Time  If coupling length is longer than saturation length then noise Vb reaches max constant value  Defined as ratio of near-end noise voltage on quiet line to switching voltage on aggressor line  NEXT=Vb/Vswing  Same as ratio of backward crosstalk coefficient Kb=Vb/Vswing 16  NEXT lasts for time of 2TD and turn on time is Trise
  • 17. Case Study: Microstrip Crosstalk  Use same PCB stackup  Set trace spacing to be 10mils  Vary dielectric height H from 5.7 to 7.1 H=5.7 H=7.1 17
  • 18. Case Study: Microstrip Summary  Often times with PCB fabrication for your design you will only have one or two impedance levers to work with  Our case it was dielectric height  Once impedance target has been established (ex. 50 Ohm +/- 10 %) need to consider other affects  Crosstalk often overlooked in PCB stackup design  Trade-off between trace width defining Zo and height defining crosstalk  Could go to larger W so smaller crosstalk but target Zo decreases  The distance of signal to reference plane is important on 18 crosstalk magnitude
  • 19. Case Study: Stripline Crosstalk  Use same PCB stackup as microstrip  Stripline will have same general trends as microstrip so dielectric height variation will have biggest impact on Zo  Set trace spacing to be 10mils  Vary dielectric height H H=34 H=41 19
  • 20. Case Study Results: PCB Stackup  Wanted to determine if critical signal should be routed on microstrip or stripline layer  Based upon available noise margin (METRICS) decided stripline crosstalk too large so chose microstrip Simulations Help You Increase Performance 20
  • 21. Keys To Accurate Simulation  Metrics  Models 21
  • 22. Metric: Noise Margin Budget 22
  • 23. Metric: Noise Margin Budget 23
  • 24. Metric: Timing Margin Budget 24
  • 25. Timing Equations : Common Clock  Define equation in terms of margin  Only have 1 full clock cycle to subtract all delays from for setup time  Tsetup_margin = Tcycle - Tco - Tflight - Tsetup - Tskew - Tjitter  Thold_margin = Tco + Tflight - Thold - Tskew 25
  • 26. Models: PCB Traces 26
  • 27. Example TLine Model Component  Example from SharkSim PCB simulation tool 27
  • 28. Impedance: Analytical vs Field Solver  Analytical equations make assumptions by fitting expressions over tabulated data for given parameter range  Field Solvers use algorithms to solve for Maxwell’s equations directly  Analytical equations can be very accurate (< 1%) to Field Solver under certain conditions  When you use analytical equations need to understand where they work and don’t work  Always use Field Solver for critical design areas and final sign-off 28
  • 29. MicroStrip:Trace Width Comparison Microstrip Impedance Comparison 120 100 80 Impedance Zo 60 Calculated Field Solver 40 20 0 0 2 4 6 8 10 12 14 Trace Width W 29
  • 30. Models: IBIS Model 30
  • 31. IO Buffer Model Matrix Model Type When To Use … Why To Use … SPICE Need to model advanced SPICE is still the golden standard and if circuit features that other you can think it you can model it BUT it formats can’t model reveals IP and can have long simulation run times IBIS Want fast and easy simulations IBIS doesn’t reveal any IP and has faster simulation run times than SPICE BUT it can’t model some advanced circuits MacroModel Want ease of use of IBIS but MacroModeling allows you to use existing (IBIS flexibility of SPICE OR build IBIS models or create your own External your own behavioral models behavioral models to model complex Extensions) circuit features like equalization BUT is tool dependent IBIS-AMI Need to model >5Gbps SerDes Extension to IBIS specification that allows for programming own dynamic link library (dll) to model complex SerDes 31 features
  • 32. IBIS Model Quality Checking Compliant IBIS Keywords and Syntax Graph and View Data Run IBIS Parser Advanced quality checking
  • 33. Block Diagram Of An IBIS Model  I/V and V/T curves (lookup tables) represent IO buffer (CMOS driver and clamps)  IO capacitance modeled as lumped cap  Package modeled as lumped RLC RLC package VCC pin C_comp power C_comp input pullup pullup clamp power 3-state clamp RLC package IO control pin pulldown C_comp ground C_comp pulldown clamp ground clamp RLC package GND pin 33
  • 34. Load Line Analysis Calculate Vol Using Pulldown I/V Curve Example Vdd=3.3V R_load=50 Ohms Vdd Vdd I I=Vdd/R_load V pulldown on Vcc Vdd=3.3V R_load Vol Vdd V T Vol Vol from V/T data (AC) should match Ground Vol intersection on I/V curve (DC) IBIS parser uses load line analysis to verify that DC endpoints from I/V curve match AC endpoints from V/T curve 34
  • 35. Summary  Simulations give you two solutions  Reduce Cost  Increase Performance  Simulation results only useful if you have metrics to analyze them by  Noise Margin  Timing Margin  Simulations need quality models 35