2.
CHAPTER 1
DIGITAL ELECTRONICS
1.1 Introduction
One of the first things we have to know is that electronics can be broadly classified into two
groups, viz. analog electronics and digital electronics. Analog electronics deals with things that
are continuous in nature and digital electronics deals with things that are discrete in nature. But
they are very much interlinked. For example, if we consider a bucket of water, then it is analog
in terms of the content i.e., water, but it is discrete in terms of the container, i.e., bucket. Now
though in nature most things are analog, still we very often require digital concepts. It is because
it has some specific advantages over analog, which we will discuss in due course of time.
Many of us are accustomed with the working of electronic amplifiers. Generally they are
used to amplify electronic signals. Now these signals usually have a continuous value and hence
can take up any value within a given range, and are known as analog signals. The electronic
circuits which are used to process such signals are called analog circuits and the circuits based
on such operation are called analog systems.
On the other side, in a computer, the input is given with the help of the switches. Then
this is converted into electronic signals, which have two distinct discrete levels or values. One of
them is called HIGH level whereas the other is called LOW level. The signal must always be in
either of the two levels. As long as the signal is within a prespecified range of HIGH and LOW,
the actual value of the signal is not that important. Such signals are called digital signals and the
circuit within the device is called a digital circuit. The system based on such a concept is an
example of a digital system.
Since Claude Shannon systemized and adapted the theoretical work of George Boole in 1938,
digital techniques saw a tremendous growth. Together with developments in semiconductor
technology, and with the progress in digital technology, a revolution in digital electronics
happened when the microprocessor was introduced in 1971 by Intel Corporation of America. At
present, digital technology has progressed much from the era of vacuum tube circuits to
integrated circuits. Digital circuits find applications in computers, telephony, radar navigation,
data processing, and many other applications. The general properties of number systems,
methods of their interconversions, and arithmetic operations are discussed in this chapter.
1.2 Number System
There are several number systems which we normally use, such as decimal, binary, octal,
hexadecimal, etc. Amongst them we are most familiar with the decimal number system. These
3.
systems are classified according to the values of the base of the number system. The number
system having the value of the base as 10 is called a decimal number system, whereas that with a
base of 2 is called a binary number system. Likewise, the number systems having base 8 and 16
are called octal and hexadecimal number systems respectively.
With a decimal system we have 10 different digits, which are 0, 1, 2, 3, 4, 5, 6, 7, 8, and
9. But a binary system has only 2 different digits—0 and 1. Hence, a binary number cannot have
any digit other than 0 or 1. So to deal with a binary number system is quite easier than a decimal
system. Now, in a digital world, we can think in binary nature, e.g., a light can be either off or
on. There is no state in between these two. So we generally use the binary system when we deal
with the digital world. Here comes the utility of a binary system. We can express everything in
the world with the help of only two digits i.e., 0 and 1. For example, if we want to express 2510 in
binary we may write 110012. The right most digit in a number system is called the ‗Least
Significant Bit‘ (LSB) or ‗Least Significant Digit‘ (LSD). And the left most digit in a number
system is called the ‗Most Significant Bit‘ (MSB) or ‗Most Significant Digit‘ (MSD). Now
normally when we deal with different number systems we specify the base as the subscript to
make it clear which number system is being used.
In an octal number system there are 8 digits—0, 1, 2, 3, 4, 5, 6, and 7. Hence, any octal
number cannot have any digit greater than 7. Similarly, a hexadecimal number system has 16
digits—0 to 9— and the rest of the six digits are specified by letter symbols as A, B, C, D, E, and
F. Here A, B, C, D, E, and F represent decimal 10, 11, 12, 13, 14, and 15 respectively. Octal and
hexadecimal codes are useful to write assembly level language.
In general, we can express any number in any base or radix ―X.‖ Any number with base
X, having n digits to the left and m digits to the right of the decimal point can be expressed as:
anXn1 + an1Xn2 + an2Xn3 + …. + a2X1 + a1X0 + b1X1 + b2X2 + …. + bmXm
where an is the digit in the nth position. The coefficient an is termed as the MSD or Most
Significant Digit and bm is termed as the LSD or the Least Significant Digit.
1.2.1 Conversion between Number System
It is often required to convert a number in a particular number system to any other number
system, e.g., it may be required to convert a decimal number to binary or octal or hexadecimal.
The reverse is also true, i.e., a binary number may be converted into decimal and so on. The
methods of interconversions are now discussed.
4.
1.2.1.1 DecimaltoBinary Conversion
Now to convert a number in decimal to a number in binary we have to divide the decimal
number by 2 repeatedly, until the quotient of zero is obtained. This method of repeated division
by 2 is called the ‗doubledabble‘ method. The remainders are noted down for each
of the division steps. Then the column of the remainder is read in reverse order i.e., from bottom
to top order. We try to show the method with an example shown in Example 1.1.
Example 1.1. Convert 2610 into a binary number.
Solution.
Division
Quotient
Generated remainder
26/2
13
0
13/2
6
1
6/2
3
0
3/2
1
1
1/2
0
1
Hence the converted binary number is 110102.
1.2.1.2 DecimaltoOctal Conversion
Similarly, to convert a number in decimal to a number in octal we have to divide the decimal
number by 8 repeatedly, until the quotient of zero is obtained. This method of repeated division
by 8 is called ‗octaldabble.‘ The remainders are noted down for each of the division steps. Then
the column of the remainder is read from bottom to top order, just as in the case of the doubledabble method. We try to illustrate the method with an example shown in Example 1.2.
Example 1.2. Convert 42610 into an octal number.
Solution.
Division
Quotient
426/8
53
53/8
6
6/8
0
Hence the converted octal number is 6528.
Generated remainder
2
5
6
5.
1.2.1.3 DecimaltoHexadecimal Conversion
The same steps are repeated to convert a number in decimal to a number in hexadecimal. Only
here we have to divide the decimal number by 16 repeatedly, until the quotient of zero is
obtained. This method of repeated division by 16 is called ‗hexdabble.‘ The remainders are
noted down for each of the division steps. Then the column of the remainder is read from bottom
to top order as in the two previous cases. We try to discuss the method with an example shown in
Example 1.3.
Example 1.3. Convert 34810 into a hexadecimal number.
Solution.
Division
Quotient
Generated remainder
348/16
21
12
21/16
1
5
1/16
0
1
Hence the converted hexadecimal number is 15C16.
1.2.1.4 BinarytoDecimal Conversion
Now we discuss the reverse method, i.e., the method of conversion of binary, octal, or
hexadecimal numbers to decimal numbers. Now we have to keep in mind that each of the binary,
octal, or hexadecimal number system is a positional number system, i.e., each of the digits in the
number systems discussed above has a positional weight as in the case of the decimal system.
We illustrate the process with the help of examples.
Example 1.4. Convert 101102 into a decimal number.
Solution. The binary number given is
10110
Positional weights
43210
The positional weights for each of the digits are written in italics below each digit. Hence
the decimal equivalent number is given as:
1*24 + 0*23 + 1*22 + 1*21 + 0*20
= 16 + 0 + 4 + 2 + 0
= 2210
Hence we find that here, for the sake of conversion, we have to multiply each bit with its
positional weights depending on the base of the number system.
6.
1.2.1.5 OctaltoDecimal Conversion
Example 1.5. Convert 34628 into a decimal number.
Solution. The octal number given is
3462
Positional weights
3210
The positional weights for each of the digits are written in italics below each digit. Hence the
decimal equivalent number is given as:
= 3*83 + 4*82 + 6*81 + 2*80
= 1536 + 256 + 48 + 2
= 184210
1.2.1.6 HexadecimaltoDecimal Conversion
Example 1.6. Convert 42AD16 into a decimal number.
Solution. The hexadecimal number given is
42AD
Positional weights
3210
The positional weights for each of the digits are written in italics below each digit. Hence the
decimal equivalent number is given as:
= 4*163 + 2*162 + 10*161 + 13*160
= 16384 + 512 + 160 + 13
= 1706910
1.2.1.7 Fractional Conversion
So far we have dealt with the conversion of integer numbers only. Now if the number contains
the fractional part we have to deal in a different way when converting the number from a
different number system (i.e., binary, octal, or hexadecimal) to a decimal number system or vice
versa. We illustrate this with examples.
Example 1.7. Convert 1010.0112 into a decimal number.
Solution. The binary number given is
1 0 1 0. 0 1 1
Positional weights
3 2 1 0 123
The positional weights for each of the digits are written in italics below each digit. Hence the
decimal equivalent number is given as:
= 1*23 + 0*22 + 1*21 + 0*20 + 0*21 + 1*22 + 1*23
= 8 + 0 + 2 + 0 + 0 + .25 + .125
= 10.37510
7.
Example 1.8. Convert 362.358 into a decimal number.
Solution. The octal number given is
3 6 2. 3 5
Positional weights
2 1 0 12
The positional weights for each of the digits are written in italics below each digit. Hence the
decimal equivalent number is given as:
= 3*82 + 6*81 + 2*80 + 3*81 + 5*82
= 192 + 48 + 2 + .37 + .078125
= 242.45212510
Example 1.9. Convert 42A.1216 into a decimal number.
Solution. The hexadecimal number given is
4 2 A. 1 2
Positional weights
2 1 0 12
The positional weights for each of the digits are written in italics below each digit. Hence the
decimal equivalent number is given as:
= 4*162 + 2*161 + 10*160 + 1*161 + 2*162
= 1024 + 32 + 10 + .0625 + .00393625
= 1066.06640621510
Example 1.10. Convert 25.62510 into a binary number.
Solution.
Division
25/2
12/2
6/2
3/2
1/2
Therefore,
Quotient
12
6
3
1
0
Generated remainder
1
0
0
1
1
(25)10 = (11001)2
Fractional Part
.625 * 2 = 1.250
.250 * 2 = .500
.500 * 2 = 1.000
1
0
1
i.e., (0.625)10 = (0.101)2
Therefore, (25.625)10 = (11001.101)2
Example 1.11. Convert 34.52510 into an octal number.
8.
Solution.
Therefore,
Division
Quotient
34/8
4
4/8
0
(34)10 = (42)8
Generated remainder
2
4
Fractional Part
.525 * 8 = 4.200
.200 * 8 = 1.600
.600 * 8 = 4.800
i.e., (0.525)10 = (0.414)8
4
1
4
Therefore, (34.525)10 = (42.411)8
Example 1.12. Convert 92.8510 into a hexadecimal number.
Solution.
Division
92/16
5/16
Therefore, (92)10 = (5C)16
Quotient
5
0
Generated remainder
12
5
Fractional Part
.85 * 16 = 13.60
.60 * 16 = 9.60
13
9
i.e., (0.85)10 = (0.D9)16
Therefore, (92.85)10 = (5C.D9)16
1.2.1.8 Conversion from a Binary to Octal Number and Vice Versa
We know that the maximum digit in an octal number system is 7, which can be represented as
1112 in a binary system. Hence, starting from the LSB, we group three digits at a time and
replace them by the decimal equivalent of those groups and we get the final octal number.
Example 1.13. Convert 1011010102 into an equivalent octal number.
Solution. The binary number given is
Starting with LSB and grouping 3 bits
Octal equivalent
Hence the octal equivalent number is (552)8.
101101010
101 101 010
5 5 2
9.
Example 1.14. Convert 10111102 into an equivalent octal number.
Solution. The binary number given is
Starting with LSB and grouping 3 bits
Octal equivalent
1011110
001 011 110
1
3 6
Hence the octal equivalent number is (176)8.
Since at the time of grouping the three digits in Example 1.14 starting from the LSB, we find that
the third group cannot be completed, since only one 1 is left out in the third group, so we
complete the group by adding two 0s in the MSB side. This is called left padding of the number
with 0. Now if the number has a fractional part then there will be two different classes of
groups—one for the integer part starting from the left of the decimal point and proceeding
toward the left and the second one starting from the right of the decimal point and proceeding
toward the right. If, for the second class, any 1 is left out, we complete the group by adding two
0s on the right side. This is called rightpadding.
Example 1.15. Convert 1101.01112 into an equivalent octal number.
Solution. The binary number given is
Grouping 3 bits
Octal equivalent:
1101.0111
001 101. 011 100
1
5
3 4
Hence the octal number is (15.34)8.
Now if the octal number is given and you're asked to convert it into its binary equivalent,
then each octal digit is converted into a 3bitequivalent binary number and—combining all
those digits we get the final binary equivalent.
Example 1.16. Convert 2358 into an equivalent binary number.
Solution. The octal number given is
3bit binary equivalent
235
010 011 101
Hence the binary number is (010011101)2.
Example 1.17. Convert 47.3218 into an equivalent binary number.
Solution. The octal number given is
47321
3bit binary equivalent
100 111 011 010 001
Hence the binary number is (100111.011010001)2.
10.
1.2.1.9 Conversion from a Binary to Hexadecimal Number and Vice Versa
We know that the maximum digit in a hexadecimal system is 15, which can be represented by
11112 in a binary system. Hence, starting from the LSB, we group four digits at a time and
replace them with the hexadecimal equivalent of those groups and we get the final hexadecimal
number.
Example 1.18. Convert 110101102 into an equivalent hexadecimal number.
Solution. The binary number given is
11010110
Starting with LSB and grouping 4 bits
1101 0110
Hexadecimal equivalent
D 6
Hence the hexadecimal equivalent number is (D6)16.
Example 1.19. Convert 1100111102 into an equivalent hexadecimal number.
Solution. The binary number given is
110011110
Starting with LSB and grouping 4 bits 0001 1001 1110
Hexadecimal equivalent
1
9
E
Hence the hexadecimal equivalent number is (19E)16.
Since at the time of grouping of four digits starting from the LSB, in Example 1.19 we
find that the third group cannot be completed, since only one 1 is left out, so we complete the
group by adding three 0s to the MSB side. Now if the number has a fractional part, as in the case
of octal numbers, then there will be two different classes of groups—one for the integer part
starting from the left of the decimal point and proceeding toward the left and the second one
starting from the right of the decimal point and proceeding toward the right. If, for the second
class, any uncompleted group is left out, we complete the group by adding 0s on the right side.
Example 1.20. Convert 111011.0112 into an equivalent hexadecimal number.
Solution. The binary number given is
111011.011
Grouping 4 bits
0011 1011. 0110
Hexadecimal equivalent
3
B
6
Hence the hexadecimal equivalent number is (3B.6)16.
Now if the hexadecimal number is given and you're asked to convert it into its binary
equivalent, then each hexadecimal digit is converted into a 4bitequivalent binary number and
by combining all those digits we get the final binary equivalent.
11.
Example 1.21. Convert 29C16 into an equivalent binary number.
Solution. The hexadecimal number given is
29C
4bit binary equivalent
0010 1001 1100
Hence the equivalent binary number is (001010011100)2.
Example 1.22. Convert 9E.AF216 into an equivalent binary number.
Solution. The hexadecimal number given is
9 E.A F 2
4bit binary equivalent
1001 1110 1010 1111 0010
Hence the equivalent binary number is (10011110.101011110010)2.
1.2.1.10 Conversion from an Octal to Hexadecimal Number and Vice Versa
Conversion from octal to hexadecimal and vice versa is sometimes required. To convert an octal
number into a hexadecimal number the following steps are to be followed:
i. First convert the octal number to its binary equivalent (as already discussed above).
ii. Then form groups of 4 bits, starting from the LSB.
iii. Then write the equivalent hexadecimal number for each group of 4 bits.
Similarly, for converting a hexadecimal number into an octal number the following steps are to
be followed:
i. First convert the hexadecimal number to its binary equivalent.
ii. Then form groups of 3 bits, starting from the LSB.
iii. Then write the equivalent octal number for each group of 3 bits.
Example 1.23. Convert the following hexadecimal numbers into equivalent octal numbers.
(a) A72E (b) 4.BF85
Solution.
(a) Given hexadecimal number is
A72E
Binary equivalent is
1010 0111 0010 1110
= 1010011100101110
Forming groups of 3 bits from the LSB 001 010 011 100 101 110
Octal equivalent 1 2 3 4 5 6
Hence the octal equivalent of (A72E)16 is (123456)8.
(b) Given hexadecimal number is
4BF85
Binary equivalent is
0100 1011 1111 1000 0101
= 0100.1011111110000101
12.
Forming groups of 3 bits 100. 101 111 111 000 010 100
Octal equivalent 4 5 7 7 0 2 4
Hence the octal equivalent of (4.BF85)16 is (4.577024)8.
Example 1.24. Convert (247)8 into an equivalent hexadecimal number.
Solution. Given octal number is
Binary equivalent is
247
010 100 111
= 010100111
Forming groups of 4 bits from the LSB 1010 0111
Hexadecimal equivalent A 7
Hence the hexadecimal equivalent of (247)8 is (A7)16.
Example 1.25. Convert (36.532)8 into an equivalent hexadecimal number.
Solution. Given octal number is
36532
Binary equivalent is
011 110 101 011 010
= 011110.101011010
Forming groups of 4 bits 0001 1110. 1010 1101
Hexadecimal equivalent 1 E. A D
Hence the hexadecimal equivalent of (36.532)8 is (1E.AD)16.
1.2.2 Complements
Complements are used in digital computers for simplifying the subtraction operation and for
logical manipulations. There are two types of complements for each number system of baser:
the r‘s complement and the (r – 1)‘s complement. When we deal with a binary system the value
of r is 2 and hence the complements are 2‘s and 1‘s complements. Similarly for a decimal system
the value of r is 10 and we get 10‘s and 9‘s complements. With the same logic if the number
system is octal we get 8‘s and 7‘s complement, while it is 16‘s and 15‘s complements for
hexadecimal system.
1.2.2.1 The r’s Complement
If a positive number N is given in base r with an integer part of n digits, the r‘s complement of N
is given as rn–N for N != 0 and 0 for N = 0. The following examples will clarify the definition.
The 10‘s complement of (23450)10 is
105 – 23450 = 76550.
The number of digits in the number is
n = 5.
The 10‘s complement of (0.3245)10 is
100 – 0.3245 = 0.6755.
13.
Since the number of digits in the integer part of the number is n = 0, we have 100 = 1.
The 10‘s complement of (23.324)10 is
102 – 23.324 = 76.676.
The number of digits in the integer part of the number is n = 2.
Now if we consider a binary system, then r = 2.
The 2‘s complement of (10110)2 is (25)10–(10110)2 = (100000 – 10110)2 = 01010.
The 2‘s complement of (0.1011)2 is (20)10–(0.1011)2 = (1 – 0.1011)2 = 0.0101.
Now if we consider an octal system, then r = 8.
The 8‘s complement of (2450)8 is
(84)10 – (2450)8.
= (409610 – 24508)
= (409610 – 132010)
= 277610.
= 53308.
Now if we consider a hexadecimal system, then r = 16.
The 16‘s complement of (4A30)16 is
(164)10 – (4A30)16
= (6553610 – 4A3016)
= (6553610 – 1899210)
= 4654410
= B5D016.
From the above examples, it is clear that to find the 10‘s complement of a decimal number all of
the bits until the first significant 0 is left unchanged and the first nonzero leastsignificant digit is
subtracted from 10 and the rest of the higher significant digits are subtracted from 9. With a
similar reasoning, the 2‘s complement of a binary number can be obtained by leaving all of the
least significant zeros and the first nonzero digit unchanged, and then replacing 1‘s with 0‘s and
0‘s with 1‘s. Similarly the 8‘s complement of an octal number can be obtained by keeping all the
bits until the first significant 0 is unchanged, and the first non zero least significant digit is
subtracted from 8 and the rest of the higher significant digits are subtracted from 7. Similarly, the
16‘s complement of a hexadecimal number can be obtained by keeping all the bits until the first
significant 0 is unchanged, and the first nonzero leastsignificant digit is subtracted from 16 and
the rest of the higher significant digits are subtracted from 15. Since r‘s complement is a general
term, r can take any value e.g., r = 11. Then we will have 11‘s complement for r‘s complement
case and 10‘s complement for (r – 1)‘s complement case.
1.2.2.2 The (r–1)’s Complement
If a positive number N is given in base r with an integer part of n digits and a fraction part of m
digits, then the (r – 1)‘s complement of N is given as (rn – r–m– N) for N �0 and 0 for N = 0. The
following examples will clarify the definition.
The 9‘s complement of (23450)10 is
105 – 100 – 23450 = 76549.
14.
Since there is no fraction part, 10–m = 100 = 1.
The 9‘s complement of (0.3245)10 is
100 – 10–4 – 0.3245 = 0.6754.
Since there is no integer part, 10n = 100 = 1.
The 9‘s complement of (23.324)10 is
102 – 10–3 – 23.324 = 76.675.
Now if we consider a binary system, then r = 2, i.e., (r – 1) = 1.
The 1‘s complement of (10110)2 is
(25–1)10 – (10110)2 = 01001.
The 1‘s complement of (0.1011)2 is
(1–2–4)10 – (0.1011)2 = 0.0100.
Now if we consider an octal system, then r = 8, i.e., (r – 1) = 7.
The 7‘s complement of (2350)8 is
84 – 80 – 23508
= 409510 – 125610
= 283910
= 54278.
The 15‘s complement of (A3E4)16 is
164 – 160 – A3E416
= 6553510 – 4195610
= 2357910
= 5C1B16.
From the above examples, it is clear that to find the 9‘s complement of a decimal number each of
the digits can be separately subtracted from 9. The 1‘s complement of a binary number can be
obtained by changing 1s into 0s and 0s into 1s. Similarly, to find the 7‘s complement of a
decimal number each of the digits can be separately subtracted from 7. Again, to find the 15‘s
complement of a decimal number each of the digits can be separately subtracted from 15.
Example 1.26. Find out the 11‘s and 10‘s complement of the number (576)11.
Solution.
The number in base is 11. So to find 11‘s complement we have to follow the r‘s complement rule
and in order to get 10‘s complement the (r – 1)‘s complement rule is to be followed.
11‘s complement:
rn – N = 113 – 57611
= (1331)10 – (576)11
Now,
57611 = 5 × 112 + 7 × 111 + 6 × 110
= 605 + 77 + 6
= 68810
Therefore, 11‘s complement is 133110 – 68810 = 64310
Now, the decimal number has to be changed in the number system of base 11.
Division
Quotient
Generated remainder
643/11
58
5
58/11
5
3
15.
5/11
0
5
Hence the 11‘s complement number is (535)11.
10‘s complement:
rn – r–m – N = 113 – 110 – 57611
= (1331)10 – (1)10 – (576)11
Therefore, 10‘s complement is 133110 – 110 – 68810 = 64210
Now, the decimal number has to be changed in the number system of base 11.
Division
Quotient
Generated remainder
642/11
58
4
58/11
5
3
5/11
0
5
Hence the 10‘s complement number is (534)11.
1.2.3 Binary Arithmetic
We are very familiar with different arithmetic operations, viz. addition, subtraction,
multiplication, and division in a decimal system. Now we want to find out how those same
operations may be performed in a binary system, where only two digits, viz. 0 and 1 exist.
1.2.3.1 Binary Addition
The rules of binary addition are given in Table 1.1.
Augend
0
0
1
1
Addend
0
1
0
1
Table 1.1
Sum
0
1
1
0
Carry
0
0
0
1
Result
0
1
1
10
The procedure of adding two binary numbers is same as that of two decimal numbers. Addition
is carried out from the LSB and it proceeds to higher significant bits, adding the carry resulting
from the addition of two previous bits each time.
1.2.3.2 Binary Subtraction
The rules of binary subtraction are given in Table 1.2.
16.
Minuend
0
0
1
1
Table 1.2
Subtrahend
Difference
0
0
1
1
0
1
1
0
Borrow
0
1
0
0
Binary subtraction is also carried out in a similar method to decimal subtraction. The subtraction
is carried out from the LSB and proceeds to the higher significant bits. When borrow is 1, as in
the second row, this is to be subtracted from the next higher binary bit as it is performed in
decimal subtraction.
Actually, the subtraction between two numbers can be performed in three ways, viz.
a. the direct method,
b. the r‘s complement method, and
c. the (r – 1)‘s complement method.
Subtraction Using the Direct Method
The direct method of subtraction uses the concept of borrow. In this method, we borrow a 1
from a higher significant position when the minuend digit is smaller than the corresponding
subtrahend digit.
1.2.3.3 Binary Multiplication
Binary multiplication is similar to decimal multiplication but much simpler than that. In a binary
system each partial product is either zero (multiplication by 0) or exactly the same as the
multiplicand (multiplication by 1). The rules of binary multiplication are given in Table 1.3.
Multiplicand
0
0
1
1
Table 1.3
Multiplier
0
1
0
1
Result
0
0
0
1
Actually, in a digital circuit, the multiplication operation is done by repeated additions of all
partial products to obtain the full product.
1.2.3.4 Binary Division
Binary division follows the same procedure as decimal division. The rules regarding binary
division are listed in Table 1.4.
17.
Dividend
0
0
1
1
Table 1.4
Divisor
0
1
0
1
Result
Not Allowed
0
Not Allowed
1
1.3 Digital Logic Circuits
Binary logic deals with variables that have two discrete values—1 for TRUE and 0 for FALSE.
A simple switching circuit containing active elements such as a diode and transistor can
demonstrate the binary logic, which can either be ON (switch closed) or OFF (switch open).
Electrical signals such as voltage and current exist in the digital system in either one of the two
recognized values, except during transition.
The switching functions can be expressed with Boolean equations. Complex Boolean
equations can be simplified by a new kind of algebra, which is popularly called Switching
Algebra or Boolean Algebra, invented by the mathematician George Boole in 1854. Boolean
Algebra deals with the rules by which logical operations are carried out.
1.3.1 Basic Definitions
Boolean algebra, like any other deductive mathematical system, may be defined with a set of
elements, a set of operators, and a number of assumptions and postulates. A set of elements
means any collection of objects having common properties. If S denotes a set, and X and Y are
certain objects, then X S denotes X is an object of set S, whereas Y denotes Y is not the
object of set S. A binary operator defined on a set S of elements is a rule that assigns to each pair
of elements from S a unique element from S. As an example, consider this relation X*Y = Z.
This implies that * is a binary operator if it specifies a rule for finding Z from the objects ( X, Y )
and also if all X, Y, and Z are of the same set S. On the other hand, * can not be binary operator
if X and Y are of set S and Z is not from the same set S.
The postulates of a mathematical system are based on the basic assumptions, which make
possible to deduce the rules, theorems, and properties of the system. Various algebraic structures
are formulated on the basis of the most common postulates, which are described as follows.
1. Closer: A set is closed with respect to a binary operator if, for every pair of elements of
S, the binary operator specifies a rule for obtaining a unique element of S. For example,
the set of natural numbers N = {1, 2, 3, 4, ...} is said to be closed with respect to the
binary operator plus ( + ) by the rules of arithmetic addition, since for any X,Y N we
obtain a unique element Z N by the operation X + Y = Z. However, note that the set of
18.
2.
3.
4.
5.
6.
natural numbers is not closed with respect to the binary operator minus (–) by the rules of
arithmetic subtraction because for 1 – 2 = –1, where –1 is not of the set of naturals
numbers.
Associative Law: A binary operator * on a set S is said to be associated whenever
(A*B)*C = A*(B*C) for all A,B,C S.
Commutative Law: A binary operator * on a set S is said to be commutative whenever
A*B = B*A for all A,B S.
Identity Element: A set S is to have an identity element with respect to a binary
operation * on S, if there exists an element E ∈ S with the property E*A = A*X = A.
Example: The element 0 is an identity element with respect to the binary operator + on
the set of integers I = {.... –4, –3, –2, –1, 0, 1, 2, 3, 4, ....} as A + 0 = 0 + A = A.
Similarly, the element 1 is the identity element with respect to the binary operator × as A
× 1 = 1 × A = A.
Inverse: If a set S has the identity element E with respect to a binary operator *, there
exists an element B ∈ S, which is called the inverse, for every A ∈ S, such that A*B = E.
Example: In the set of integers I with E = 0, the inverse of an element A is (A) since A +
(–A) = 0.
Distributive Law: If * and (.) are two binary operators on a set S, * is said to be
distributive over (.), whenever A*(B.C) = (A*B).(A*C).
If summarized, for the field of real numbers, the operators and postulates have the
following meanings:
The binary operator + defines addition.
The additive identity is 0.
The additive inverse defines subtraction.
The binary operator (.) defines multiplication.
The multiplication identity is 1.
The multiplication inverse of A is 1/A, defines division i.e., A. 1/A = 1.
The only distributive law applicable is that of (.) over +
A . (B + C) = (A . B) + (A . C)
1.3.2 DEFINITION OF BOOLEAN ALGEBRA
In 1854 George Boole introduced a systematic approach of logic and developed an algebraic
system to treat the logic functions, which is now called Boolean algebra. In 1938 C.E. Shannon
developed a twovalued Boolean algebra called Switching algebra, and demonstrated that the
properties of twovalued or bistable electrical switching circuits can be represented by this
algebra. The postulates formulated by E.V. Huntington in 1904 are employed for the formal
definition of Boolean algebra. However, Huntington postulates are not unique for defining
Boolean algebra and other postulates are also used. The following Huntington postulates are
19.
satisfied for the definition of Boolean algebra on a set of elements S together with two binary
operators (+) and (.).
1.
(a) Closer with respect to the operator (+).
(b) Closer with respect to the operator (.).
2.
(a) An identity element with respect to + is designated by 0 i.e., A + 0 = 0 + A =
A.
(b) An identity element with respect to . is designated by 1 i.e., A.1 = 1. A = A.
3.
(a) Commutative with respect to (+), i.e., A + B = B + A.
(b) Commutative with respect to (.), i.e., A.B = B.A.
4.
(a) (.) is distributive over (+), i.e., A . (B+C) = (A . B) + (A . C).
(b) (+) is distributive over (.), i.e., A + (B .C) = (A + B) . (A + C).
5. For every element A ∈ S, there exists an element A' ∈ S (called the complement of A)
such that A + A′ = 1 and A . A′ = 0.
6. There exists at least two elements A,B ∈ S, such that A is not equal to B.
Comparing Boolean algebra with arithmetic and ordinary algebra (the field of real numbers), the
following differences are observed:
1. Huntington postulates do not include the associate law. However, Boolean algebra
follows the law and can be derived from the other postulates for both operations.
2. The distributive law of (+) over ( . ) i.e., A+ (B.C) = (A+B) . (A+C) is valid for
Boolean algebra, but not for ordinary algebra.
3. Boolean algebra does not have additive or multiplicative inverses, so there are no
subtraction or division operations.
4. Postulate 5 defines an operator called Complement, which is not available in ordinary
algebra.
5. Ordinary algebra deals with real numbers, which consist of an infinite set of elements.
Boolean algebra deals with the as yet undefined set of elements S, but in the two valued
Boolean algebra, the set S consists of only two elements—0 and 1.
Boolean algebra is very much similar to ordinary algebra in some respects. The symbols (+) and
(.) are chosen intentionally to facilitate Boolean algebraic manipulations by persons already
familiar to ordinary algebra. Although one can use some knowledge from ordinary algebra to
deal with Boolean algebra, beginners must be careful not to substitute the rules of ordinary
algebra where they are not applicable.
It is important to distinguish between the elements of the set of an algebraic structure and
the variables of an algebraic system. For example, the elements of the field of real numbers are
numbers, the variables such as X, Y, Z, etc., are the symbols that stand for real numbers, which
are used in ordinary algebra. On the other hand, in the case of Boolean algebra, the elements of a
set S are defined, and the variables A, B, C, etc., are merely symbols that represent the elements.
20.
At this point, it is important to realize that in order to have Boolean algebra, the following must
be shown.
1. The elements of the set S.
2. The rules of operation for the two binary operators.
3. The set of elements S, together with the two operators satisfies six Huntington postulates.
One may formulate much Boolean algebra, depending on the choice of elements of set S
and the rules of operation. In the subsequent chapters, we will only deal with a twovalued
Boolean algebra i.e., one with two elements. Twovalued Boolean algebra has the applications in
set theory and propositional logic. But here, our interest is with the application of Boolean
algebra to gatetype logic circuits.
1.3.3 Basic Properties And Theorems Of Boolean Algebra
1.3.3.1 Principle of Duality
From Huntington postulates, it is evident that they are grouped in pairs as (a) and (b) and every
algebraic expression deductible from the postulates of Boolean algebra remains valid if the
operators and identity elements are interchanged. This means one expression can be obtained
from the other in each pair by interchanging every element i.e., every 0 with 1, every 1 with 0, as
well as interchanging the operators i.e., every (+) with (.) and every (.) with (+). This important
property of Boolean algebra is called principle of duality.
1.3.3.2 DeMorgan's Theorem
Two theorems that were proposed by DeMorgan play important parts in Boolean algebra.
The first theorem states that the complement of a product is equal to the sum of the
complements. That is, if the variables are A and B, then
(A.B)′ = A′ + B′
The second theorem states that the complement of a sum is equal to the product of the
complements. In equation form, this can be expressed as
(A + B)′ = A′ . B′
The complements of Boolean logic function or a logic expression may be simplified or expanded
by the following steps of DeMorgan‘s theorem.
(a) Replace the operator (+) with (.) and (.) with (+) given in the expression.
(b) Complement each of the terms or variables in the expression.
21.
DeMorgan‘s theorems are applicable to any number of variables. For three variables A, B, and
C, the equations are
(A.B.C)′ = A′ + B′ + C′
and
(A + B + C)′ = A′.B′.C′
1.3.3.3 Other Important Theorems
Theorem 1(a): A + A = A
A + A = (A + A).1
= (A + A) . ( A + A′)
= A + A.A′
=A+0
=A
Theorem 1(b): A . A = A
A . A = (A . A) + 0
= (A . A) + ( A . A′)
= A (A + A′)
=A.1
=A
by postulate 2(b)
by postulate 5
by postulate 4
by postulate 2(a)
by postulate 2(a)
by postulate 5
by postulate 4
by postulate 2(b)
Theorem 2(a): A + 1 = 1
Theorem 2(b): A . 0 = 0
Theorem 3(a): A + A.B = A
A + A.B = A . 1 + A.B
= A ( 1 + B)
=A.1
=A
by postulate 2(b)
by postulate 4(a)
by postulate 2(a)
by postulate 2(b)
Theorem 3(b): A ( A + B ) = A
by duality
The following is the complete list of postulates and theorems useful for twovalued Boolean
algebra.
Postulate 2
(a) A + 0 = A
(b) A.1 = A
Postulate 5
(a) A + A′ = 1
(b) A.A′ = 0
Theorem 1
(a) A + A = A
(b) A.A = A
Theorem 2
(a) A + 1 = 1
(b) A.0 = 0
22.
(A′)′ = A
(a) A + B = B + A
(a) A + (B + C) = (A + B) + C
(a) A(B + C) = A.B + A.C
(a) (A + B)′ = A′.B′
(a) A + A.B = A
Theorem 3, Involution
Theorem 3, Involution
Theorem 4, Associative
Theorem 4, Distributive
Theorem 5, DeMorgan
Theorem 6, Absorption
(b) A.B = B.A
(b) A.(B.C) = (A.B).C
(b) A + B.C = (A + B).(A + C)
(b) (A.B)′ = A′ + B′
(b) A.(A + B) = A
1.3.3.4 Boolean Functions
Binary variables have two values, either 0 or 1. A Boolean function is an expression formed with
binary variables, the two binary operators AND and OR, one unary operator NOT, parentheses
and equal sign. The value of a function may be 0 or 1, depending on the values of variables
present in the Boolean function or expression. For example, if a Boolean function is expressed
algebraically as
F = AB′C
then the value of F will be 1, when A = 1, B = 0, and C = 1. For other values of A, B, C the value
of F is 0.
Boolean functions can also be represented by truth tables. A truth table is the tabular
form of the values of a Boolean function according to the all possible values of its variables. For
an n number of variables, 2n combinations of 1s and 0s are listed and one column represents
function values according to the different combinations. For example, for three variables the
Boolean function F = AB + C truth table can be written as below in Figure below.
A
0
0
0
0
1
1
1
1
B
0
0
1
1
0
0
1
1
C
0
1
0
1
0
1
0
1
F
0
1
0
1
0
1
1
1
A Boolean function from an algebraic expression can be realized to a logic diagram composed of
logic gates. Figure 3.11 is an example of a logic diagram realized by the basic gates like AND,
OR, and NOT gates. In subsequent chapters, more logic diagrams with various gates will be
shown.
23.
1.3.3.5 Simplification Of Boolean Expressions
When a Boolean expression is implemented with logic gates, each literal in the function is
designated as input to the gate. The literal may be a primed or unprimed variable. Minimization
of the number of literals and the number of terms leads to less complex circuits as well as less
number of gates, which should be a designer‘s aim. There are several methods to minimize the
Boolean function. In this chapter, simplification or minimization of complex algebraic
expressions will be shown with the help of postulates and theorems of Boolean algebra.
Example 1. Simplify the Boolean function F=AB+ BC + B′C.
Solution.
F = AB + BC + B′C
= AB + C(B + B′)
= AB + C
Example 2. Simplify the Boolean function F= A + A′B.
Solution.
F = A+ A′B
= (A + A′) (A + B)
=A+B
Example 3. Simplify the Boolean function F= A′B′C + A′BC + AB′.
Solution.
F = A′B′C + A′BC + AB′
= A′C (B′+B) + AB′
= A′C + AB′
Example 4. Simplify the Boolean function F = AB + (AC)′ + AB′C(AB + C).
Solution.
F = AB + (AC)′ + AB′C(AB + C)
= AB + A′ + C′+ AB′C.AB + AB′C.C
= AB + A′ + C′ + 0 + AB′C (B.B′ = 0 and C.C = C)
= ABC + ABC′ + A′ + C′ + AB′C (AB = AB(C + C′) = ABC + ABC′)
= AC(B + B′) + C′(AB + 1) + A′
= AC + C′+A′ (B + B′ = 1 and AB + 1 = 1)
= AC + (AC)′
=1
Example 5. Simplify the Boolean function F = ((XY′ + XYZ)′ + X(Y + XY′))′.
Solution.
F = ((XY′ + XYZ)′ + X(Y + XY′))′
24.
= ((X(Y′ + YZ))′ + XY + XY′)′
= ((X(Y′Z + Y′ + YZ))′ + X(Y + Y′))′ (Y′ = Y′(Z + 1) = Y′Z + Y′)
= (X(Y′ + Z))′ + X)′
= (X′ + (Y′ + Z)′ + X)′
= (1+ YZ′)′
= 1′
=0
Example 3.6. Simplify the Boolean function F = XYZ + XY′Z + XYZ′.
Solution.
F = XYZ + XY′Z + XYZ′
= XZ (Y + Y′) + XY (Z + Z′)
= XZ + XY
= X (Y + Z)
1.3.3.6 CANONICAL AND STANDARD FORMS
Logical functions are generally expressed in terms of different combinations of logical variables
with their true forms as well as the complement forms. Binary logic values obtained by the
logical functions and logic variables are in binary form. An arbitrary logic function can be
expressed in the following forms.
(i) Sum of the Products (SOP)
(ii) Product of the Sums (POS)
Product Term. In Boolean algebra, the logical product of several variables on which a function
depends is considered to be a product term. In other words, the AND function is referred to as a
product term or standard product. The variables in a product term can be either in true form or in
complemented form. For example, ABC′ is a product term.
Sum Term. An OR function is referred to as a sum term. The logical sum of several variables on
which a function depends is considered to be a sum term. Variables in a sum term can also be
either in true form or in complemented form. For example, A + B + C′ is a sum term.
Sum of Products (SOP). The logical sum of two or more logical product terms is referred to as a
sum of products expression. It is basically an OR operation on AND operated variables. For
example, Y = AB + BC + AC or Y = A′B + BC + AC′ are sum of products expressions.
Product of Sums (POS). Similarly, the logical product of two or more logical sum terms is called
a product of sums expression. It is an AND operation on OR operated variables. For example, Y
25.
= (A + B + C)(A + B′ + C)(A + B + C′) or Y = (A + B + C)(A′ + B′ + C′) are product of sums
expressions.
Standard form. The standard form of the Boolean function is when it is expressed in sum of the
products or product of the sums fashion. The examples stated above, like Y = AB + BC + AC or
Y = (A + B + C)(A + B′ + C)(A + B + C′) are the standard forms.
However, Boolean functions are also sometimes expressed in nonstandard forms like F = (AB +
CD)(A′B′ + C′D′), which is neither a sum of products form nor a product of sums form.
However, the same expression can be converted to a standard form with help of various Boolean
properties, as
F = (AB + CD)(A′B′ + C′D′) = A′B′CD + ABC′D′
1 Minterm
A product term containing all n variables of the function in either true or complemented form is
called the minterm. Each minterm is obtained by an AND operation of the variables in their true
form or complemented form. For a twovariable function, four different combinations are
possible, such as, A′B′, A′B, AB′, and AB. These product terms are called the fundamental
products or standard products or minterms. In the minterm, a variable will possess the value 1 if
it is in true or uncomplemented form, whereas, it contains the value 0 if it is in complemented
form. For three variables function, eight minterms are possible as listed in the following table in
Figure below.
A
0
0
0
0
1
1
1
1
B
0
0
1
1
0
0
1
1
C
0
1
0
1
0
1
0
1
Minterm
A′B′C′
A′B′C
A′BC′
A′BC
AB′C′
AB′C
ABC′
ABC
So, if the number of variables is n, then the possible number of minterms is 2n. The main
property of a minterm is that it possesses the value of 1 for only one combination of n input
variables and the rest of the 2n – 1 combinations have the logic value of 0. This means, for the
above three variables example, if A = 0, B = 1, C = 1 i.e., for input combination of 011, there is
only one combination A′BC that has the value 1, the rest of the seven combinations have the
value 0.
26.
Canonical Sum of Product Expression. When a Boolean function is expressed as the
logical sum of all the minterms from the rows of a truth table, for which the value of the function
is 1, it is referred to as the canonical sum of product expression. The same can be expressed in a
compact form by listing the corresponding decimalequivalent codes of the minterms containing
a function value of 1. For example, if the canonical sum of product form of a threevariable logic
function F has the minterms A′BC, AB′C, and ABC′, this can be expressed as the sum of the
decimal codes corresponding to these minterms as below.
F (A,B,C) = (3,5,6)
= m3 + m5 + m6
= A′BC + AB′C + ABC′
where Σ (3,5,6) represents the summation of minterms corresponding to decimal codes 3, 5, and
6.
The canonical sum of products form of a logic function can be obtained by using the
following procedure.
i. Check each term in the given logic function. Retain if it is a minterm,
continue to examine the next term in the same manner.
ii. Examine for the variables that are missing in each product which is not a
minterm. If the missing variable in the minterm is X, multiply that
minterm with (X+X′).
iii. Multiply all the products and discard the redundant terms. Here are some
examples to explain the above procedure.
Example 3.7. Obtain the canonical sum of product form of the following function.
F (A, B) = A + B
Solution. The given function contains two variables A and B. The variable B is missing from the
first term of the expression and the variable A is missing from the second term of the expression.
Therefore, the first term is to be multiplied by (B + B′) and the second term is to be multiplied by
(A + A′) as demonstrated below.
F (A, B) = A + B
= A.1 + B.1
= A (B + B′) + B (A + A′)
= AB + AB′ + AB + A′B
= AB + AB′ + A′B (as AB + AB = AB)
Hence the canonical sum of the product expression of the given function is
F (A, B) = AB + AB′ + A′B.
Example 3.8. Obtain the canonical sum of product form of the following function.
F (A, B, C) = A + BC
Solution. Here neither the first term nor the second term is minterm. The given function contains
three variables A, B, and C. The variables B and C are missing from the first term of the
27.
expression and the variable A is missing from the second term of the expression. Therefore, the
fi rst term is to be multiplied by (B + B′) and (C + C′). The second term is to be multiplied by (A
+ A′). This is demonstrated below.
F (A, B, C) = A + BC
= A (B + B′) (C + C′) + BC (A + A′)
= (AB + AB′) (C + C′) + ABC + A′BC
= ABC + AB′C + ABC′ + AB′C′ + ABC + A′BC
= ABC + AB′C + ABC′ + AB′C′ + A′BC (as ABC + ABC = ABC)
Hence the canonical sum of the product expression of the given function is
F (A, B) = ABC + AB′C + ABC′ + AB′C′ + A′BC.
Example 3.9. Obtain the canonical sum of product form of the following function.
F (A, B, C, D) = AB + ACD
Solution.
F (A, B, C, D) = AB + ACD
= AB (C + C′) (D + D′) + ACD (B + B′)
= (ABC + ABC′) (D + D′) + ABCD + AB′CD
= ABCD + ABCD′ + ABC′D + ABC′D′ + ABCD + AB′CD
= ABCD + ABCD′ + ABC′D + ABC′D′ + AB′CD
Hence above is the canonical sum of the product expression of the given function.
2 Maxterm
A sum term containing all n variables of the function in either true or complemented form is
called the maxterm. Each maxterm is obtained by an OR operation of the variables in their true
form or complemented form. Four different combinations are possible for a twovariable
function, such as, A′ + B′, A′ + B, A + B′, and A + B. These sum terms are called the standard
sums or maxterms. Note that, in the maxterm, a variable will possess the value 0, if it is in true or
uncomplemented form, whereas, it contains the value 1, if it is in complemented form. Like
minterms, for a threevariable function, eight maxterms are also possible as listed in the
following table in Figure below.
A
0
0
0
0
1
1
1
1
B
0
0
1
1
0
0
1
1
C
0
1
0
1
0
1
0
1
Maxterm
A+B+C
A + B + C′
A + B′ + C
A + B′ + C′
A′ + B + C
A′ + B + C′
A′ + B′ + C
A′ + B′ + C′
28.
So, if the number of variables is n, then the possible number of maxterms is 2n. The main
property of a maxterm is that it possesses the value of 0 for only one combination of n input
variables and the rest of the 2n –1 combinations have the logic value of 1. This means, for the
above three variables example, if A = 1, B = 1, C = 0 i.e., for input combination of 110, there is
only one combination A′ + B′ + C that has the value 0, the rest of the seven combinations have
the value 1.
Canonical Product of Sum Expression. When a Boolean function is expressed as the
logical product of all the maxterms from the rows of a truth table, for which the value of the
function is 0, it is referred to as the canonical product of sum expression. The same can be
expressed in a compact form by listing the corresponding decimal equivalent codes of the
maxterms containing a function value of 0. For example, if the canonical product of sums form
of a threevariable logic function F has the maxterms A + B + C, A + B′ + C, and A′ + B + C′,
this can be expressed as the product of the decimal codes corresponding to these maxterms as
below,
F (A,B,C = Π (0,2,5)
= M0 M2 M5
= (A + B + C) (A + B′ + C) (A′ + B + C′)
where Π (0,2,5) represents the product of maxterms corresponding to decimal codes 0, 2, and 5.
The canonical product of sums form of a logic function can be obtained by using the
following procedure.
i. Check each term in the given logic function. Retain it if it is a maxterm,
continue to examine the next term in the same manner.
ii. Examine for the variables that are missing in each sum term that is not a
maxterm. If the missing variable in the maxterm is X, multiply that
maxterm with (X.X′).
iii. Expand the expression using the properties and postulates as described
earlier and discard the redundant terms.
Some examples are given here to explain the above procedure.
Example 3.10. Obtain the canonical product of the sum form of the following function.
F (A, B, C) = (A + B′) (B + C) (A + C′)
Solution. In the above threevariable expression, C is missing from the first term, A is missing
from the second term, and B is missing from the third term. Therefore, CC′ is to be added with fi
rst term, AA′ is to be added with the second, and BB′ is to be added with the third term. This is
shown below.
F (A, B, C) = (A + B′) (B + C) (A + C′)
= (A + B′ + 0) (B + C + 0) (A + C′ + 0)
= (A + B′ + CC′) (B + C + AA′) (A + C′ + BB′)
= (A + B′ + C) (A + B′ + C′) (A + B + C) (A′ + B + C) (A + B + C′) (A + B′ + C′)
29.
[using the distributive property, as X + YZ = (X + Y)(X + Z)]
= (A + B′ + C) (A + B′ + C′) (A + B + C) (A′ + B + C) (A + B + C′)
[as (A + B′ + C′) (A + B′ + C′) = A + B′ + C′]
Hence the canonical product of the sum expression for the given function is
F (A, B, C) = (A + B′ + C) (A + B′ + C′) (A + B + C) (A′ + B + C) (A + B + C′)
Example 3.11. Obtain the canonical product of the sum form of the following function.
F (A, B, C) = A + B′C
Solution. In the above threevariable expression, the function is given at sum of the product
form. First, the function needs to be changed to product of the sum form by applying the
distributive law as shown below.
F (A, B, C) = A + B′C
= (A + B′) (A + C)
Now, in the above expression, C is missing from the first term and B is missing from the second
term. Hence CC′ is to be added with the first term and BB′ is to be added with the second term as
shown below.
F (A, B, C) = (A + B′) (A + C)
= (A + B′ + CC′) (A + C + BB′)
= (A + B′ + C) (A + B′ + C′) (A + B + C) (A + B′ + C)
[using the distributive property, as X + YZ = (X + Y) (X + Z)]
= (A + B′ + C) (A + B′ + C′) (A + B + C)
[as (A + B′ + C) (A + B′ + C) = A + B′ + C]
Hence the canonical product of the sum expression for the given function is
F (A, B, C) = (A + B′ + C) (A + B′ + C′) (A + B + C).
3 Deriving a Sum of Products (SOP) Expression from a Truth Table
The sum of products (SOP) expression of a Boolean function can be obtained from its truth table
summing or performing OR operation of the product terms corresponding to the combinations
containing a function value of 1. In the product terms the input variables appear either in true
(uncomplemented) form if it contains the value 1, or in complemented form if it possesses the
value 0.
Now, consider the following truth table in Figure 3.14, for a threeinput function Y. Here
the output Y value is 1 for the input conditions of 010, 100, 101, and 110, and their
corresponding product terms are A′BC′, AB′C′, AB′C, and ABC′ respectively.
A
0
0
0
Input
B
0
0
1
Output
C
0
1
0
0
0
1
Product Terms
Sum Terms
A+B+C
A + B + C′
A′BC′
30.
0
1
1
1
1
1
0
0
1
1
1
0
1
0
1
0
1
1
1
0
A + B′ + C′
AB′C′
AB′C
ABC′
A′ + B′ + C′
The final sum of products expression (SOP) for the output Y is derived by summing or
performing an OR operation of the four product terms as shown below.
Y = A′BC′ + AB′C′ + AB′C + ABC′
In general, the procedure of deriving the output expression in SOP form from a truth table
can be summarized as below.
i. Form a product term for each input combination in the table, containing an
output value of 1.
ii. Each product term consists of its input variables in either true form or
complemented form. If the input variable is 0, it appears in complemented
form and if the input variable is 1, it appears in true form.
iii. To obtain the fi nal SOP expression of the output, all the product terms are
OR operated.
4 Deriving a Product of Sums (POS) Expression from a Truth Table
As explained above, the product of sums (POS) expression of a Boolean function can also be
obtained from its truth table by a similar procedure. Here, an AND operation is performed on the
sum terms corresponding to the combinations containing a function value of 0. In the sum terms
the input variables appear either in true (uncomplemented) form if it contains the value 0, or in
complemented form if it possesses the value 1. Now, consider the same truth table as shown in
Figure 3.14, for a threeinput function Y. Here the output Y value is 0 for the input conditions of
000, 001, 011, and 111, and their corresponding product terms are A + B + C, A + B + C′, A + B′
+ C′, and A′ + B′ + C′ respectively.
So now, the fi nal product of sums expression (POS) for the output Y is derived by
performing an AND operation of the four sum terms as shown below.
Y = (A + B + C) (A + B + C′) (A + B′ + C′) (A′ + B′ + C′)
In general, the procedure of deriving the output expression in POS form from a truth table
can be summarized as below.
i. Form a sum term for each input combination in the table, containing an
output value of 0.
31.
ii. Each product term consists of its input variables in either true form or
complemented form. If the input variable is 1, it appears in complemented
form and if the input variable is 0, it appears in true form.
iii. To obtain the fi nal POS expression of the output, all the sum terms are
AND operated.
5 Conversion between Canonical Forms
From the above example, it may be noted that the complement of a function expressed as the
sum of products (SOP) equals to the sum of products or sum of the minterms which are missing
from the original function. This is because the original function is expressed by those minterms
that make the function equal to 1, while its complement is 1 for those minterms whose values are
0. According to the truth table given in Figure 3.14:
F (A,B,C) = ( 2,4,5,6)
= m2 + m4 + m5 + m6
= A′BC′ + AB′C′ + AB′C + ABC′.
This has the complement that can be expressed as
F′ (A,B,C) = (0,1,3,7)
= m0 + m1 + m3 + m7
Now, if we take complement of F′ by DeMorgan‘s theorem, we obtain F as
F (A,B,C) = (m0 + m1 + m3 + m7)′
= m0′m1′m3′m′7
= M0M1M3M7
= Π(0,1,3,7)
= (A + B + C)(A + B + C′) (A + B′ + C′) (A′ + B′ + C′).
The last conversion follows from the defi nition of minterms and maxterms as shown in
the tables in Figures 3.12 and 3.13. It can be clearly noted that the following relation holds true
m′j = Mj.
That is, the maxterm with subscript j is a complement of the minterm with the same
subscript j, and vice versa.
This example demonstrates the conversion between a function expressed in sum of
products (SOP) and its equivalent in product of maxterms. A similar example can show the
conversion between the product of sums (POS) and its equivalent sum of minterms. In general,
to convert from one canonical form to other canonical form, it is required to interchange the
symbols Σ and π, and list the numbers which are missing from the original form.
Note that, to fi nd the missing terms, the total 2n number of minterms or maxterms must
be realized, where n is the number of variables in the function.
32.
1.3.4 Digital Logic Gates
As Boolean functions are expressed in terms of AND, OR, and NOT operations, it is easier to
implement the Boolean functions with these basic types of gates. However, for all practical
purposes, it is possible to construct other types of logic gates. The following factors are to be
considered for construction of other types of gates.
Name
Graphic Symbol
Algebraic Function
F = AB
AND
F=A+B
OR
Inverter or
NOT
F = A′
Buffer
A
0
0
1
1
A
0
0
1
1
F=A
F = (AB)′
NAND
F = (A + B)′
NOR
ExclusiveOR
(XOR)
F = AB′ + A′B
=A B
A
0
0
1
1
A
0
0
1
1
A
0
0
1
1
Truth Table
B
0
1
0
1
B
0
1
0
1
A
0
1
A
0
1
B
0
1
0
1
B
0
1
0
1
B
0
1
0
1
F
0
0
0
1
F
0
1
1
1
F
1
0
F
0
1
F
1
1
1
0
F
1
0
0
0
F
0
1
1
0
33.
ExclusiveNOR (XNOR)
F = AB + A′B′
=AB
A
0
0
1
1
B
0
1
0
1
F
1
0
0
1
1. The feasibility and economy of producing the gate with physical parameters.
2. The possibility of extending to more than two inputs.
3. The basic properties of the binary operator such as commutability and associability.
4. The ability of the gate to implement the Boolean functions alone or in conjunction with other
gates.
Out of the 16 functions described in the table in Figure 3.15, we have seen that two are
equal to constant, and four others are repeated twice. Two functions—inhibition and implication,
are impractical to use as standard gates due to lack of commutative or associative properties. So,
there are eight functions—Transfer (or buffer), Complement, AND, OR, NAND, NOR,
ExclusiveOR (XOR), and Equivalence (XNOR) that may be considered to be standard gates in
digital design.
The graphic symbols and truth tables of eight logic gates are shown in Figure above. The
transfer or buffer and complement or inverter or NOT gates are unary gates, i.e., they have single
input, while other logic gates have two or more inputs.
1.4 Flip Flops
The basic 1bit digital memory circuit is known as a flipflop. It can have only two states, either
the 1 state or the 0 state. A flipflop is also known as a bistable multivibrator. Flipflops can be
obtained by using NAND or NOR gates. The general block diagram representation of a flipflop
is shown in Figure 7.3. It has one or more inputs and two outputs. The two outputs are
complementary to each other. If Q is 1 i.e., Set, then Q' is 0; if Q is 0 i.e., Reset, then Q' is 1.
That means Q and Q' cannot be at the same state simultaneously. If it happens by any chance, it
violates the definition of a flipflop and hence is called an undefined condition. Normally, the
state of Q is called the state of the fl ipfl op, whereas the state of Q' is called the complementary
state of the flipflop. When the output Q is either 1 or 0, it remains in that state unless one or
more inputs are excited to effect a change in the output. Since the output of the flipflop remains
in the same state until the trigger pulse is applied to change the state, it can be regarded as a
memory device to store one binary bit.
34.
1.4.1 Types of Flip Flop
There are different types of fl ipfl ops depending on how their inputs and clock pulses cause
transition between two states. We will discuss four different types of flipflops in this chapter,
viz., SR, D, JK, and T. Basically D, JK, and T are three different modifications of the SR flipflop.
1.4.1.1 SR (SetReset) Flipflop
An SR flipflop has two inputs named Set (S) and Reset (R), and two outputs Q and Q'. The
outputs are complement of each other, i.e., if one of the outputs is 0 then the other should be 1.
This can be implemented using NAND or NOR gates. The block diagram of an SR flipflop is
shown in Figure.
SR Flipflop Based on NOR Gates
An SR flipflop can be constructed with NOR gates at ease by connecting the NOR gates back
to back as shown in Figure. The crosscoupled connections from the output of gate 1 to the input
of gate 2 constitute a feedback path. This circuit is not clocked and is classified as an
asynchronous sequential circuit. The truth table for the SR flipflop based on a NOR gate is
shown in the table.
To analyze the circuit shown in above Figure, we have to consider the fact that the output of a
NOR gate is 0 if any of the inputs are 1, irrespective of the other input. The output is 1 only if all
of the inputs are 0. The outputs for all the possible conditions as shown in the table in Figure 7.8
are described as follows.
35.
Inputs
S
0
0
1
1
0
R
0
1
0
1
0
Outputs
Qn+1
Q'n+1
Qn
Q'n
0
1
1
0
0
0

Action
No change
Reset
Set
Forbidden(Undefined)
Indeterminate
Case 1. For S = 0 and R = 0, the fl ipfl op remains in its present state (Qn). It means that the next
state of the fl ipfl op does not change, i.e., Qn+1 = 0 if Qn = 0 and vice versa. First let us assume
that Qn = 1 and Q'n = 0. Thus the inputs of NOR gate 2 are 1 and 0, and therefore its output
Q'n+1= 0. This output Q'n+1 = 0 is fed back as the input of NOR gate 1, thereby producing a 1 at
the output, as both of the inputs of NOR gate 1 are 0 and 0; so Qn+1 = 1 as originally assumed.
Now let us assume the opposite case, i.e., Qn = 0 and Q'n = 1. Thus the inputs of NOR
gate 1 are 1 and 0, and therefore its output Qn+1 = 0. This output Qn+1 =0 is fed back as the input
of NOR gate 2, thereby producing a 1 at the output, as both of the inputs of NOR gate 2 are 0 and
0; so Q'n+1 = 1 as originally assumed. Thus we fi nd that the condition S = 0 and R = 0 do not
affect the outputs of the flipflop, which means this is the memory condition of the SR fl ipfl
op.
Case 2. The second input condition is S = 0 and R = 1. The 1 at R input forces the output of
NOR gate 1 to be 0 (i.e., Qn+1 = 0). Hence both the inputs of NOR gate 2 are 0 and 0 and so its
output Q'n+1 = 1. Thus the condition S = 0 and R = 1 will always reset the flipflop to 0. Now if
the R returns to 0 with S = 0, the flipflop will remain in the same state.
Case 3. The third input condition is S = 1 and R = 0. The 1 at S input forces the output of NOR
gate 2 to be 0 (i.e., Q'n+1 = 0). Hence both the inputs of NOR gate 1 are 0 and 0 and so its output
Qn+1 = 1. Thus the condition S = 1 and R = 0 will always set the flipflop to 1. Now if the S
returns to 0 with R = 0, the flipflop will remain in the same state.
Case 4. The fourth input condition is S = 1 and R = 1. The 1 at R input and 1 at S input forces
the output of both NOR gate 1 and NOR gate 2 to be 0. Hence both the outputs of NOR gate 1
and NOR gate 2 are 0 and 0; i.e., Qn+1 = 0 and Q'n+1 = 0. Hence this condition S = 1 and R = 1
violates the fact that the outputs of a flipflop will always be the complement of each other. Since
the condition violates the basic definition of flipflop, it is called the undefined condition.
Generally this condition must be avoided by making sure that 1s are not applied simultaneously
to both of the inputs.
36.
Case 5. If case 4 arises at all, then S and R both return to 0 and 0 simultaneously, and then any
one of the NOR gates acts faster than the other and assumes the state. For example, if NOR gate
1 is faster than NOR gate 2, then Qn+1 will become 1 and this will make Q'n+1 = 0. Similarly, if
NOR gate 2 is faster than NOR gate 1, then Q'n+1 will become 1 and this will make Qn+1 = 0.
Hence, this condition is determined by the flipflop itself. Since this condition cannot be
controlled and predicted it is called the indeterminate condition.
S'R' Flipfl op Based on NAND Gates
An S'R' flipflop can be constructed with NAND gates by connecting the NAND gates back to
back as shown in Figure 7.9. The operation of the S'R' flipflop can be analyzed in a similar
manner as that employed for the NORbased SR flipflop. This circuit is also not clocked and is
classified as an asynchronous sequential circuit. The truth table for the S'R' flipflop based on a
NAND gate is shown in the table in Figure below.
To analyze the circuit shown in above Figure, we have to remember that a LOW at any input of a
NAND gate forces the output to be HIGH, irrespective of the other input. The output of a NAND
gate is 0 only if all of the inputs of the NAND gate are 1. The outputs for all the possible
conditions as shown in the table are described below.
Inputs
S'
R'
1
1
0
0
1
1
0
1
0
1
Outputs
Qn+1
Q'n+1
Qn
Qn
0
1
1
0
1
1

Action
No change
Reset
Set
Forbidden(Undefined)
Indeterminate
Case 1. For S' = 1 and R' = 1, the fl ipfl op remains in its present state (Qn). It means that the
next state of the flipflop does not change, i.e., Qn+1 = 0 if Qn = 0 and vice versa. First let us
37.
assume that Qn =1 and Q'n = 0. Thus the inputs of NAND gate 1 are 1 and 0, and therefore its
output Qn+1 = 1. This output Qn+1 = 1 is fed back as the input of NAND gate 2, thereby producing
a 0 at the output, as both of the inputs of NAND gate 2 are 1 and 1; so Q'n+1 = 0 as originally
assumed. Now let us assume the opposite case, i.e., Qn = 0 and Q'n = 1. Thus the inputs of
NAND gate 2 are 1 and 0, and therefore its output Q'n+1 = 1. This output Q'n+1 = 1 is fed back as
the input of NAND gate 1, thereby producing a 0 at the output, as both of the inputs of NAND
gate 1 are 1 and 1; so Qn+1 = 0 as originally assumed. Thus we find that the condition S' = 1 and
R' = 1 do not affect the outputs of the flipflop, which means this is the memory condition of the
S'R' flipflop.
Case 2. The second input condition is S' = 1 and R' = 0. The 0 at R' input forces the output of
NAND gate 2 to be 1 (i.e., Q'n+1 = 1). Hence both the inputs of NAND gate 1 are 1 and 1 and so
its output Qn+1 = 0. Thus the condition S' = 1 and R' = 0 will always reset the flipflop to 0. Now
if the R' returns to 1 with S' = 1, the flipflop will remain in the same state.
Case 3. The third input condition is S' = 0 and R' = 1. The 0 at S' input forces the output of
NAND gate 1 to be 1 (i.e., Qn+1 = 1). Hence both the inputs of NAND gate 2 are 1 and 1 and so
its output Q'n+1 = 0. Thus the condition S' = 0 and R' = 1 will always set the flipflop to 1. Now if
the S' returns to 1 with R' = 1, the flipflop will remain in the same state.
Case 4. The fourth input condition is S' = 0 and R' = 0. The 0 at R' input and 0 at S' input forces
the output of both NAND gate 1 and NAND gate 2 to be 1. Hence both the outputs of NAND
gate 1 and NAND gate 2 are 1 and 1; i.e., Qn+1 = 1 and Q'n+1 = 1. Hence this condition S' = 0 and
R' = 0 violates the fact that the outputs of a flipflop will always be the complement of each
other. Since the condition violates the basic definition of a flipflop, it is called the undefined
condition. Generally, this condition must be avoided by making sure that 0s are not applied
simultaneously to both of the inputs.
Case 5. If case 4 arises at all, then S' and R' both return to 1 and 1 simultaneously, and then any
one of the NAND gates acts faster than the other and assumes the state. For example, if NAND
gate 1 is faster than NAND gate 2, then Qn+1 will become 1 and this will make Q'n+1 = 0.
Similarly, if NAND gate 2 is faster than NAND gate 1, then Q'n+1 will become 1 and this will
make Qn+1 = 0. Hence, this condition is determined by the flipflop itself. Since this condition
cannot be controlled and predicted it is called the indeterminate condition.
38.
Thus, comparing the NOR flipflop and the NAND flipflop, we find that they basically
operate in just the complement fashion of each other. Hence, to convert a NANDbased S'R'
flipflop into a NORbased SR flipflop, we have to place an inverter at each input of the flipflop. The resulting circuit is shown in Figure above, which behaves in the same manner as an SR flipflop.
1.4.1.2 Clocked SR FlipFlop
Generally, synchronous circuits change their states only when clock pulses are present. The
operation of the basic flipflop can be modified by including an additional input to control the
behaviour of the circuit. Such a circuit is shown in Figure below.
Block diagram of a clocked SR flipflop.
The circuit shown in Figure above consists of two AND gates. The clock input is
connected to both of the AND gates, resulting in LOW outputs when the clock input is LOW. In
this situation the changes in S and R inputs will not affect the state (Q) of the flipflop. On the
other hand, if the clock input is HIGH, the changes in S and R will be passed over by the AND
gates and they will cause changes in the output (Q) of the flipflop. This way, any information,
either 1 or 0, can be stored in the flipflop by applying a HIGH clock input and be retained for
any desired period of time by applying a LOW at the clock input. This type of flipflop is called
a clocked SR flipflop. Such a clocked SR flipflop made up of two AND gates and two NOR
gates is shown in Figure below.
A clocked NORbased SR flipflop
39.
Now the same SR flipflop can be constructed using the basic NAND latch and two other
NAND gates. The S and R inputs control the states of the flipflop in the same way as described
earlier for the unclocked SR flipflop. However, the flipflop only responds when the clock
signal occurs. The clock pulse input acts as an enable signal for the other two inputs. As long as
the clock input remains 0 the outputs of NAND gates 1 and 2 stay at logic 1. This 1 level at the
inputs of the basic NANDbased SR flip flop retains the present state.
The logic symbol of the SR flipflop is shown in Figure below. It has three inputs: S, R,
and CLK. The CLK input is marked with a small triangle. The triangle is a symbol that denotes
the fact that the circuit responds to an edge or transition at CLK input.
Assuming that the inputs do not change during the presence of the clock pulse, we can express
the working of the SR flipflop in the form of the truth table in Figure 7.16. Here, Sn and Rn
denote the inputs and Qn the output during the bit time n . Qn+1 denotes the output after the pulse
passes, i.e., in the bit time n + 1.
Inputs
S
0
0
1
1
R
0
1
0
1
Output
Qn+1
Qn
0
1

Case 1. If Sn = Rn = 0, and the clock pulse is not applied, the output of the flipflop remains in
the present state. Even if Sn = Rn = 0, and the clock pulse is applied, the output at the end of the
clock pulse is the same as the output before the clock pulse, i.e., Qn+1 = Qn. The first row of the
table indicates that situation.
Case 2. For Sn = 0 and Rn = 1, if the clock pulse is applied (i.e., CLK = 1), the output of NAND
gate 1 becomes 1; whereas the output of NAND gate 2 will be 0. Now a 0 at the input of NAND
40.
gate 4 forces the output to be 1, i.e., Q' = 1. This 1 goes to the input of NAND gate 3 to make
both the inputs of NAND gate 3 as 1, which forces the output of NAND gate 3 to be 0, i.e., Q =
0.
Case 3. For Sn = 1 and Rn = 0, if the clock pulse is applied (i.e., CLK = 1), the output of NAND
gate 2 becomes 1; whereas the output of NAND gate 1 will be 0. Now a 0 at the input of NAND
gate 3 forces the output to be 1, i.e., Q = 1. This 1 goes to the input of NAND gate 4 to make
both the inputs of NAND gate 4 as 1, which forces the output of NAND gate 4 to be 0, i.e., Q' =
0.
Case 4. For Sn = 1 and Rn = 1, if the clock pulse is applied (i.e., CLK = 1), the outputs of both
NAND gate 2 and NAND gate 1 becomes 0. Now a 0 at the input of both NAND gate 3 and
NAND gate 4 forces the outputs of both the gates to be 1, i.e., Q = 1 and Q' = 1. When the CLK
input goes back to 0 (while S and R remain at 1), it is not possible to determine the next state, as
it depends on whether the output of gate 1 or gate 2 goes to 1 first.
1.4.1.3 Clocked D FlipFlop
The D flipflop has only one input referred to as the D input, or data input, and two outputs as
usual Q and Q'. It transfers the data at the input after the delay of one clock pulse at the output Q.
So in some cases the input is referred to as a delay input and the flipflop gets the name delay (D)
flipflop. It can be easily constructed from an SR flipflop by simply incorporating an inverter
between S and R such that the input of the inverter is at the S end and the output of the inverter is
at the R end. We can get rid of the undefined condition, i.e., S = R = 1 condition, of the SR flipflop in the D flipflop. The D flipflop is either used as a delay device or as a latch to store one
bit of binary information. The truth table of D flip flop is given in the table in Figure 7.23. The
structure of the D flipflop is shown in Figure 7.22, which is being constructed using NAND
gates. The same structure can be constructed using only NOR gates.
41.
Input
Dn
0
1
Output
Qn+1
0
1
Case 1. If the CLK input is low, the value of the D input has no effect, since the S and R inputs
of the basic NAND flipflop are kept as 1.
Case 2. If the CLK = 1, and D = 1, the NAND gate 1 produces 0, which forces the output of
NAND gate 3 as 1. On the other hand, both the inputs of NAND gate 2 are 1, which gives the
output of gate 2 as 0. Hence, the output of NAND gate 4 is forced to be 1, i.e., Q = 1, whereas
both the inputs of gate 5 are 1 and the output is 0, i.e., Q' = 0. Hence, we find that when D = 1,
after one clock pulse passes Q = 1, which means the output follows D.
Case 3. If the CLK = 1, and D = 0, the NAND gate 1 produces 1. Hence both the inputs of
NAND gate 3 are 1, which gives the output of gate 3 as 0. On the other hand, D = 0 forces the
output of NAND gate 2 to be 1. Hence the output of NAND gate 5 is forced to be 1, i.e., Q' = 1,
whereas both the inputs of gate 4 are 1 and the output is 0, i.e., Q = 0. Hence, we find that when
D = 0, after one clock pulse passes Q = 0, which means the output again follows D.
1.4.1.4 JK flipflop
A JK flipflop has very similar characteristics to an SR flipflop. The only difference is that the
undefined condition for an SR flipflop, i.e., Sn = Rn = 1 condition, is also included in this case.
Inputs J and K behave like inputs S and R to set and reset the flipflop respectively. When J = K
= 1, the flipflop is said to be in a toggle state, which means the output switches to its
complementary state every time a clock passes.
The data inputs are J and K, which are ANDed with Q' and Q respectively to obtain the
inputs for S and R respectively. A JK flipflop thus obtained is shown in Figure below. The
truth table of such a flipflop.
42.
Inputs
Jn
0
0
1
1
Kn
0
1
0
1
Output
Qn+1
Qn
0
1
Q'n
Case 1. When the clock is applied and J = 0, whatever the value of Q'n (0 or 1), the output of
NAND gate 1 is 1. Similarly, when K = 0, whatever the value of Qn (0 or 1), the output of gate 2
is also 1. Therefore, when J = 0 and K = 0, the inputs to the basic flipflop are S = 1 and R = 1.
This condition forces the flipflop to remain in the same state.
Case 2. When the clock is applied and J = 0 and K = 1 and the previous state of the flipflop is
reset (i.e., Qn = 0 and Q'n = 1), then S = 1 and R = 1. Since S = 1 and R = 1, the basic flipflop
does not alter the state and remains in the reset state. But if the flipflop is in set condition (i.e.,
Qn = 1 and Q'n = 0), then S = 1 and R = 0. Since S = 1 and R = 0, the basic flipflop changes its
state and resets.
Case 3. When the clock is applied and J = 1 and K = 0 and the previous state of the flipflop is
reset (i.e., Qn = 0 and Q'n = 1), then S = 0 and R = 1. Since S = 0 and R = 1, the basic fl ipfl op
changes its state and goes to the set state. But if the flipflop is already in set condition (i.e., Qn =
1 and Q'n = 0), then S = 1 and R = 1. Since S = 1 and R = 1, the basic flipflop does not alter its
state and remains in the set state.
Case 4. When the clock is applied and J = 1 and K = 1 and the previous state of the flipflop is
reset (i.e., Qn = 0 and Q'n = 1), then S = 0 and R = 1. Since S = 0 and R = 1, the basic flipflop
changes its state and goes to the set state. But if the flipflop is already in set condition (i.e., Qn =
1 and Q'n = 0), then S = 1 and R = 0. Since S = 1 and R = 0, the basic flipflop changes its state
and goes to the reset state. So we find that for J = 1 and K = 1, the flipflop toggles its state from
set to reset and vice versa. Toggle means to switch to the opposite state.
1.4.1.5 T Flip Flop
With a slight modification of a JK flipflop, we can construct a new flipflop called a T flip flop.
If the two inputs J and K of a JK flipflop are tied together it is referred to as a T flipflop.
Hence, a T flipflop has only one input T and two outputs Q and Q'. The name T flipflop
actually indicates the fact that the flipflop has the ability to toggle. It has actually only two
states—toggle state and memory state. Since there are only two states, a T flip flop is a very
43.
good option to use in counter design and in sequential circuits design where switching an
operation is required. The truth table of a T flipflop is given below.
T
0
0
1
1
Qn
0
1
0
1
Qn+1
0
1
1
0
If the T input is in 0 state (i.e., J = K = 0) prior to a clock pulse, the Q output will not change
with the clock pulse. On the other hand, if the T input is in 1 state (i.e., J = K = 1) prior to a clock
pulse, the Q output will change to Q' with the clock pulse. In other words, we may say that, if T
= 1 and the device is clocked, then the output toggles its state.
The truth table shows that when T = 0, then Qn+1 = Qn, i.e., the next state is the same as
the present state and no change occurs. When T = 1, then Qn+1 = Q'n, i.e., the state of the flipflop
is complemented. The circuit diagram of a T flipflop is shown in Figure below.
1.4.2 Triggering Of FlipFlops
Flipflops are synchronous sequential circuits. This type of circuit works with the application of
a synchronization mechanism, which is termed as a clock. Based on the specific interval or point
in the clock during or at which triggering of the flipflop takes place, it can be classified into two
different types—level triggering and edge triggering. A clock pulse starts from an initial value of
0, goes momentarily to 1, and after a short interval, returns to the initial value.
1.4.2.1 Level Triggering of Flipflops
If a flipflop gets enabled when a clock pulse goes HIGH and remains enabled throughout the
duration of the clock pulse remaining HIGH, the flipflop is said to be a level triggered flipflop.
If the flipflop changes its state when the clock pulse is positive, it is termed as a positive level
triggered f ipflop. On the other hand, if a NOT gate is introduced in the clock input terminal of
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the flipflop, then the flipflop changes its state when the clock pulse is negative, it is termed as a
negative level triggered flipflop.
The main drawback of level triggering is that, as long as the clock pulse is active, the
flipflop changes its state more than once or many times for the change in inputs. If the inputs do
not change during one clock pulse, then the output remains stable. On the other hand, if the
frequency of the input change is higher than the input clock frequency, the output of the flipflop
undergoes multiple changes as long as the clock remains active. This can be overcome by using
either masterslave flipflops or the edgetriggered flipflop.
1.4.2.2 Edgetriggering of Flipflops
A clock pulse goes from 0 to 1 and then returns from 1 to 0. Figure 7.46 shows the two
transitions and they are defined as the positive edge (0 to 1 transition) and the negative edge (1 to
0 transition). The term edgetriggered means that the flipflop changes its state only at either the
positive or negative edge of the clock pulse.
One way to make the flipflop respond to only the edge of the clock pulse is to use capacitive
coupling. An RC circuit is shown in Figure 7.47, which is inserted in the clock input of the flipflop. By deliberate design, the RC time constant is made much smaller than the clock pulse
width. The capacitor can charge fully when the clock goes HIGH. This exponential charging
produces a narrow positive spike across the resistor. Later, the trailing edge of the pulse results in
a narrow negative spike. The circuit is so designed that one of the spikes (either the positive or
negative) is neglected and the edge triggering occurs due to the other spike.
1.4.2.3 Excitation Table Of a FlipFlop
The truth table of a flipfl op is also referred to as the characteristic table of a flipflop, since this
table refers to the operational characteristics of the flipflop. But in designing sequential circuits,
we often face situations where the present state and the next state of the flipflop is specified, and
we have to find out the input conditions that must prevail for the desired output condition. By
present and next states we mean to say the conditions before and after the clock pulse
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respectively. For example, the output of an SR flipflop before the clock pulse is Qn = 1 and it is
desired that the output does not change when the clock pulse is applied.
Now from the characteristic table of an SR flipflop (Figure 7.20), we obtain the
following conditions:
1. S = R = 0 (second row)
2. S = 1, R = 0 (sixth row).
We come to the conclusion from the above conditions that the R input must be 0, whereas the S
input may be 0 or 1 (i.e., don‘tcare). Similarly, for all possible situations, the input conditions
can be found out. A tabulation of these conditions is known as an excitation table. The table in
below gives the excitation table for SR, D, JK, and T flipflops. These conditions are derived
from the corresponding characteristic tables of the flipflops.
Present
State (Qn)
0
0
1
1
Next
State (Qn+1)
0
1
0
1
SR FF
Sn
Rn
0
X
1
0
0
1
X
0
D FF
Dn
0
1
0
1
JK FF
Jn
0
1
X
X
Kn
X
X
1
0
TFF
Tn
0
1
1
0
Excitation table of different flipflops
1.5 Adders
Various informationprocessing jobs are carried out by digital computers. Arithmetic operations
are among the basic functions of a digital computer. Addition of two binary digits is the most
basic arithmetic operation. The simple addition consists of four possible elementary operations,
which are 0+0 = 0, 0+1 = 1, 1+0 = 1, and 1+1 = 10. The first three operations produce a sum of
one digit, but the fourth operation produces a sum consisting of two digits. The higher significant
bit of this result is called the carry. A combinational circuit that performs the addition of two bits
as described above is called a halfadder. When the augend and addend numbers contain more
significant digits, the carry obtained from the addition of two bits is added to the next higherorder pair of significant bits. Here the addition operation involves three bits—the augend bit,
addend bit, and the carry bit and produces a sum result as well as carry. The combinational
circuit performing this type of addition operation is called a fulladder. In circuit development
two halfadders can be employed to form a fulladder.
46.
1.5.1 Design of Halfadders
As described above, a halfadder has two inputs and two outputs. Let the input variables augend
and addend be designated as A and B, and output functions be designated as S for sum and C for
carry. The truth table for the functions is below.
Input Variables
A
B
0
0
0
1
1
0
1
1
Output Variables
S
C
0
0
1
0
1
0
0
1
From the truth table in Figure 5.2, it can be seen that the outputs S and C functions are similar to
ExclusiveOR and AND functions respectively, as shown in Figure below. The Boolean
expressions are
S = A′B+AB′ and
C = AB.
Figure below shows the logic diagram to implement the halfadder circuit.
1.5.2 Design of Fulladders
A combinational circuit of fulladder performs the operation of addition of three bits—the
augend, addend, and previous carry, and produces the outputs sum and carry. Let us designate
the input variables augend as A, addend as B, and previous carry as X, and outputs sum as S and
carry as C. As there are three input variables, eight different input combinations are possible. The
truth table is shown below according to its functions.
X
0
Input Variables
A
0
B
0
Output Variables
S
C
0
0
47.
0
0
0
1
1
1
1
0
1
1
0
0
1
1
1
0
1
0
1
0
1
1
1
0
1
0
0
1
0
0
1
0
1
1
1
To derive the simplified Boolean expression from the truth table, the Karnaugh map method is
adopted as in shown below.
A′ B′
X′
X
A′B
AB
1
1
AB′
1
1
Map for function S
A′ B′
X′
X
A′B
AB
AB′
1
1
1
1
Map for function C
The simplified Boolean expressions of the outputs are
S = X′A′B + X′AB′ + XA′B′ + XAB and
C = AB + BX + AX.
The logic diagram for the above functions is shown below. It is assumed complements of
X, A, and B are available at the input source.
48.
Note that one type of configuration of the combinational circuit diagram for fulladder is
realized in below, with twoinput and threeinput AND gates, and three input and fourinput OR
gates. Other configurations can also be developed where number and type of gates are reduced.
For this, the Boolean expressions of S and C are modified as follows.
S = X′A′B + X′AB′ + XA′B′ + XAB
= X′ (A′B + AB′) + X (A′B′ + AB)
= X′ (A B) + X (A B)′
=X A B
C = AB + BX + AX = AB + X (A + B)
= AB + X (AB + AB′ + AB + A′B)
= AB + X (AB + AB′ + A‘B)
= AB + XAB + X (AB′ + A‘B)
= AB + X (A B)
Logic diagram according to the modified expression is
You may notice that the fulladder developed in above Figure consists of two 2input AND
gates, two 2input XOR (ExclusiveOR) gates and one 2input OR gate. This contains a reduced
number of gates as well as type of gates as compared to actual Figure. Also, if compared with a
halfadder circuit, the fulladder circuit can be formed with two halfadders and one OR gate.
1.6 Registers
A register is a group of binary storage cells capable of holding binary information. A group of
flipflops constitutes a register, since each flipflop can work as a binary cell. An nbit register,
has n flipflops and is capable of holding nbits of information. In addition to flipflops a register
can have a combinational part that performs dataprocessing tasks.
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Various types of registers are available in MSI circuits. The simplest possible register is
one that contains no external gates, and is constructed of only flipflops. Figure 8.1 shows such a
type of register constructed of four SR flipflops, with a common clock pulse input. The clock
pulse enables all the flipflops at the same instant so that the information available at the four
inputs can be transferred into the 4bit register. All the flipflops in a register should respond to
the clock pulse transition. Hence they should be either of the edgetriggered type or the masterslave type. A group of flipflops sensitive to the pulse duration is commonly called a gated latch.
Latches are suitable to temporarily store binary information that is to be transferred to an
external destination. They should not be used in the design of sequential circuits that have
feedback connections.
1.6.1 Shift Register
A register capable of shifting its binary contents either to the left or to the right is called a shift
register. The shift register permits the stored data to move from a particular location to some
other location within the register. Registers can be designed using discrete flipflops (SR, JK,
and Dtype).
The data in a shift register can be shifted in two possible ways:
(a) serial shifting and
(b) parallel shifting.
The serial shifting method shifts one bit at a time for each clock pulse in a serial manner,
beginning with either LSB or MSB. On the other hand, in parallel shifting operation, all the data
(input or output) gets shifted simultaneously during a single clock pulse. Hence, we may say that
parallel shifting operation is much faster than serial shifting operation.
There are two ways to shift data into a register (serial or parallel) and similarly two ways
to shift the data out of the register. This leads to the construction of four basic types of registers
as shown in Figures below. All of the four configurations are commercially available as TTL
MSI/LSI circuits. They are:
1. Serial in/Serial out (SISO) – 54/74L91, 8 bits
2. Serial in/Parallel out (SIPO) – 54/74164, 8 bits
3. Parallel in/Serial out (PISO) – 54/74265, 8 bits
4. Parallel in/Parallel out (PIPO) – 54/74198, 8 bits.
50.
Serial data
Serial Data
n bit
input
output
(a) Serial In/Serial Out
Serial data
n bit
input
MSB
LSB
Parallel Data Output
(b) Serial In/Parallel Out
Parallel Data Input
MSB
LSB

Serial Data
n bit
output
(c) Parallel In/Serial Out
Parallel Data Input
MSB
LSB

n bit
MSB
LSB
Parallel Data Output
(d) Parallel In/Parallel Out
51.
1.6.2 SerialIn–SerialOut Shift Register
From the name itself it is obvious that this type of register accepts data serially, i.e., one bit at a
time at the single input line. The output is also obtained on a single output line in a serial fashion.
The data within the register may be shifted from left to right using shiftleft register, or may be
shifted from right to left using shiftright register.
1.6.2.1 Shiftright Register
A shiftright register can be constructed with either JK or D flipflops as shown in Figure 8.3. A
JK flipflop–based shift register requires connection of both J and K inputs. Input data are
connected to the J and K inputs of the left most (lowest order) flipflop. To input a 0, one should
apply a 0 at the J input, i.e., J = 0 and K = 1 and vice versa. With the application of a clock pulse
the data will be shifted by one bit to the right. In the shift register using D fl ipfl op, D input of
the left most flipflop is used as a serial input line. To input 0, one should apply 0 at the D input
and vice versa.
The clock pulse is applied to all the flipflops simultaneously. When the clock pulse is applied,
each flipflop is either set or reset according to the data available at that point of time at the
respective inputs of the individual flipflops. Hence the input data bit at the serial input line is
entered into flipflop A by the first clock pulse. At the same time, the data of stage A is shifted
into stage B and so on to the following stages. For each clock pulse, data stored in the register is
shifted to the right by one stage. New data is entered into stage A, whereas the data present in
stage D are shifted out (to the right).
1.6.2.2 Shiftleft Register
A shiftleft register can also be constructed with either JK or D flipflops as shown in Figure
below. Let us now illustrate the entry of the 4bit number 1110 into the register, beginning with
52.
the rightmost bit. A 0 is applied at the serial input line, making D = 0. As the first clock pulse is
applied, flipflop A is RESET, thus storing the 0. Next a 1 is applied to the serial input, making
D = 1 for flipflop A and D = 0 for flipflop B, because the input of flipflop B is connected to
the QA output.
When the second clock pulse occurs, the 1 on the data input is ―shifted‖ to the flipflop
A and the 0 in the flipflop A is ―shifted‖ to flipflop B. The 1 in the binary number is now
applied at the serial input line, and the third clock pulse is now applied. This 1 is entered in flipflop A and the 1 stored in flipflop A is now ―shifted‖ to flipflop B and the 0 stored in flipflop
B is now ―shifted‖ to flipflop C. The last bit in the binary number that is the 1 is now applied at
the serial input line and the fourth clock pulse is now applied. This 1 now enters the flipflop A
and the 1 stored in flipflop A is now ―shifted‖ to flipflop B and the 1 stored in flipflop B is
now ―shifted‖ to flipflop C and the 0 stored in flipflop C is now ―shifted‖ to flipflop D. Thus
the entry of the 4bit binary number in the shiftright register is now completed.
1.6.2.3 8bit Serialin–Serialout Shift Register
The pinout and logic diagram of IC 74L91 is shown in Figure 8.6. IC 74L91 is actually an
example of an 8bit serialin–serialout shift register. This is an 8bit TTL MSI chip. There are
eight SR flipflops connected to provide a serial input as well as a serial output. The clock input
at each flipflop is negative edgetriggered. However, the applied clock signal is passed through
an inverter. Hence the data will be shifted on the positive edges of the input clock pulses.
An inverter is connected in between R and S on the first flipflop. This means that this
circuit functions as a Dtype flipflop. So the input to the register is a single liner on which the
data can be shifted into the register appears serially. The data input is applied at either A (pin 12)
or B (pin 11). The data level at A (or B) is complemented by the NAND gate and then applied to
the R input of the first flipflop. The same data level is complemented by the NAND gate and
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then again complemented by the inverter before it appears at the S input. So, a 0 at input A will
reset the first flipflop (in other words this 0 is shifted into the first flipflop) on a positive clock
transition.
The NAND gate with A and B inputs provide a gating function for the input data stream
if required, if gating is not required, simply connect pins 11 and 12 together and apply the input
data stream to this connection.
1.6.3 SerialIn–ParallelOut Register
In this type of register, the data is shifted in serially, but shifted out in parallel. To obtain the
output data in parallel, it is required that all the output bits are available at the same time. This
can be accomplished by connecting the output of each flipflop to an output pin. Once the data is
stored in the flipflop the bits are available simultaneously.
1.6.3.1 8bit Serialin–Parallelout Shift Register
The pinout and logic diagram of IC 74164 is shown in Figure 8.7. IC 74164 is an example of an
8bit serialin–parallelout shift register. There are eight SR flipflops, which are all sensitive to
negative clock transitions. The logic diagram of this is same as previous one with only two
exceptions: (1) each flipflop has an asynchronous CLEAR input; and (2) the true side of each
flipflop is available as an output—thus all 8 bits of any number stored in the register are
available simultaneously as an output (this is a parallel data output).
Hence, a low level at the CLR input to the chip (pin 9) is applied through an amplifier
and will reset every flipflop. As long as the CLR input to the chip is LOW, the flipflop outputs
will all remain low. It means that, in effect, the register will contain all zeros. Shifting of data
into the register in a serial fashion is exactly the same as the IC 74L91. Data at the serial input
may be changed while the clock is either low or high, but the usual hold and setup times must be
observed. The data sheet for this device gives hold time as 0.0 ns and setup time as 30 ns. Now
we try to analyze the gated serial inputs A and B. Suppose that the serial data is connected to B;
then A can be used as a control line. Here‘s how it works:
54.
A is held high: The NAND gate is enabled and the serial input data passes through the NAND
gate inverted. The input data is shifted serially into the register.
A is held low: The NAND gate output is forced high, the input data steam is inhibited, and the
next clock pulse will shift a 0 into the first flipflop. Each succeeding positive clock pulse will
shift another 0 into the register. After eight clock pulses, the register will be full of zeros.
Example 8.1. How long will it take to shift an 8bit number into a 74164 shift register if the
clock is set at 1 MHz?
Solution. A minimum of eight clock Pulses will be required since the data is entered serially.
One clock pulse period is 1000 ns, so it will require 8000 ns minimum.
1.6.4 ParallelIn–SerialOut Register
In the preceding two cases the data was shifted into the registers in a serial manner. We now can
develop an idea for the parallel entry of data into the register. Here the data bits are entered into
the flipflops simultaneously, rather than a bitbybit basis. A 4bit parallelin–serialout register
is illustrated in Figure below. A, B, C, and D are the four parallel data input lines and SHIFT /
LOAD (SH / LD) is a control input that allows the four bits of data at A, B, C, and D inputs to
enter into the register in parallel or shift the data in serial. When SHIFT / LOAD is HIGH, AND
gates G1, G3, and G5 are enabled, allowing the data bits to shift right from one stage to the next.
When SHIFT / LOAD is LOW, AND gates G2, G4, and G6 are enabled, allowing the data bits at
the parallel inputs. When a clock pulse is applied, the flipflops with D = 1 will be set and the
flipflops with D = 0 will be reset, thereby storing all the four bits simultaneously. The OR gates
allow either the normal shifting operation or the parallel dataentry operation, depending on
which of the AND gates are enabled by the level on the SHIFT / LOAD input.
55.
1.6.5 ParallelIn–ParallelOut Register
There is a fourth type of register already before, which is designed such that data can be shifted
into or out of the register in parallel. The parallel input of data has already been discussed in the
preceding section of parallelin–serialout shift register. Also, in this type of register there is no
interconnection between the flipflops since no serial shifting is required. Hence, the moment the
parallel entry of the data is accomplished the data will be available at the parallel outputs of the
register. A simple parallelin–parallel out shift register is shown below.
Here the parallel inputs to be applied at PA, PB, PC, and PD inputs are directly connected to the
D inputs of the respective flipflops. On applying the clock transitions, these inputs are entered
into the register and are immediately available at the outputs QA, QB, QC, and QD.
1.7 Counters
Counters are one of the simplest types of sequential networks. A counter is usually constructed
from one or more flipflops that change state in a prescribed sequence when input pulses are
received. A counter driven by a clock can be used to count the number of clock cycles. Since the
clock pulses occur at known intervals, the counter can be used as an instrument for measuring
time and therefore period of frequency. Counters can be broadly classified into three categories:
(i) Asynchronous and Synchronous counters.
(ii) Single and multimode counters.
(iii) Modulus counters.
The asynchronous counter is simple and straightforward in operation and construction and
usually requires a minimum amount of hardware. In asynchronous counters, each flip flop is
triggered by the previous flipflop, and hence the speed of operation is limited. In fact, the
settling time of the counter is the cumulative sum of the individual settling times of the flipflops. This type of counters is also called ripple or serial counter.
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