Your SlideShare is downloading. ×
Lvs
Lvs
Lvs
Lvs
Lvs
Lvs
Lvs
Lvs
Lvs
Lvs
Lvs
Lvs
Lvs
Lvs
Lvs
Upcoming SlideShare
Loading in...5
×

Thanks for flagging this SlideShare!

Oops! An error has occurred.

×
Saving this for later? Get the SlideShare app to save on your phone or tablet. Read anywhere, anytime – even offline.
Text the download link to your phone
Standard text messaging rates apply

Lvs

215

Published on

0 Comments
0 Likes
Statistics
Notes
  • Be the first to comment

  • Be the first to like this

No Downloads
Views
Total Views
215
On Slideshare
0
From Embeds
0
Number of Embeds
0
Actions
Shares
0
Downloads
4
Comments
0
Likes
0
Embeds 0
No embeds

Report content
Flagged as inappropriate Flag as inappropriate
Flag as inappropriate

Select your reason for flagging this presentation as inappropriate.

Cancel
No notes for slide

Transcript

  • 1. Design SpecificationsThe bottom-up design flow for a transistor-level circuit layout always starts with a set of designspecifications. The "specs" typically describe the expected functionality (Boolean operations) of thedesigned block, as well as the maximum allowable delay times, the silicon area and other propertiessuch as power dissipation. Usually, the design specifications allow considerable freedom to the circuitdesigner on issues concerning the choice of a specific circuit topology, individual placement of thedevices, the locations of input and output pins, and the overall aspect ratio (width-to-height ratio) of thefinal design. Note that the limitations spelled out in the initial design specs typically require certaindesign trade-offs, such as increasing the dimensions of the transistors in order to reduce the delaytimes.In a large-scale design, the initial design specifications may also evolve during the design process toaccomodate other specs or limitations.This implies that the designer(s) of individual blocks or modules must communicate clearly andfrequently about the spec updates, in order to avoid later inconsistencies.As an example, the initial design specs of a one-bit binary full adder circuit are listed below: • Technology: 0.8 um twin-well CMOS • Propagation delay of "sum" and "carry_out" signals < 1.2 ns (worst case) • Transition times of "sum" and "carry_out" signals <1.2 ns (worst case) • Circuit area < 1500 um^2 • Dynamic power dissipation (at VDD=5 V and fmax=20 MHz) < 1 mWIt can be seen that one can design a number of different adders (with different topologies, differentmaximum delays, different total silicon areas, etc.), all of which essentially conform to the specs listedabove. This indicates that the starting point of a typical bottom-up design process usually leaves thedesigner a considerable amount of design freedom.Schematic Capture Please follow the example link (button) for a detailed description of "Schematic Capture".The traditional method for capturing (i.e. describing) your transistor-level or gate-level design is via theschematic editor. Schematic editors provide simple, intuitive means to draw, to place and to connectindividual components that make up your design. The resulting schematic drawing must accuratelydescribe the main electrical properties of all components and their interconnections. Also included inthe schematic are the power supply and ground connections, as well as all "pins" for the input andoutput signals of your circuit. This information is crucial for generating the corresponding netlist,which is used in later stages of the design. The generation of a complete circuit schematic is thereforethe first important step of the transistor-level design flow. Usually, some properties of the components(e.g. transistor dimensions) and/or the interconnections between the devices are subsequently modifiedas a result of iterative optimization steps. These later modifications and improvements on the circuitstructure must also be accurately reflected in the most current version of the corresponding schematic.
  • 2. Symbol Creation Please follow the example link (button) for a detailed description of "Symbol Creation".If a certain circuit design consists of smaller hierarchical components (or modules), it is usually verybeneficial to identify such modules early in the design process and to assign each such module acorresponding symbol (or icon) to represent that circuit module. This step largely simplifies theschematic representation of the overall system. The "symbol" view of a circuit module is an icon thatstands for the collection of all components within the module.A symbol view of the circuit is also required for some of the subsequent simulation steps, thus, theschematic capture of the circuit topology is usually followed by the creation of a symbol to representthe entire circuit. The shape of the icon to be used for the symbol may suggest the function of themodule (e.g. logic gates - AND, OR, NAND, NOR), but the default symbol icon is a simple rectangularbox with input and output pins. Note that this icon can now be used as the building block of anothermodule, and so on, allowing the circuit designer to create a system-level design consisting of multiplehierarchy levels.
  • 3. Simulation Please follow the example link (button) for a detailed description of "Simulation".After the transistor-level description of a circuit is completed using the Schematic Editor, the electricalperformance and the functionality of the circuit must be verified using a Simulation tool. The detailedtransistor-level simulation of your design will be the first in-depth validation of its operation, hence, itis extremely important to complete this step before proceeding with the subsequent design optimizationsteps. Based on simulation results, the designer usually modifies some of the device properties (such astransistor width-to-length ratio) in order to optimize the performance.The initial simulation phase also serves to detect some of the design errors that may have been createdduring the schematic entry step. It is quite common to discover errors such as a missing connection oran unintended crossing of two signals in the schematic.The second simulation phase follows the "extraction" of a mask layout (post-layout simulation), toaccurately assess the electrical performance of the completed design.
  • 4. Mask Layout • Manual Layout Example • Automatic Layout Example (Device Level Placer)The creation of the mask layout is one of the most important steps in the full-custom (bottom-up)design flow, where the designer describes the detailed geometries and the relative positioning of eachmask layer to be used in actual fabrication, using a Layout Editor. Physical layout design is very tightlylinked to overall circuit performance (area, speed and power dissipation) since the physical structuredetermines the transconductances of the transistors, the parasitic capacitances and resistances, andobviously, the silicon area which is used to realize a certain function. On the other hand, the detailedmask layout of logic gates requires a very intensive and time-consuming design effort.The physical (mask layout) design of CMOS logic gates is an iterative process which starts with thecircuit topology and the initial sizing of the transistors. It is extremely imporant that the layout designmust not violate any of the Layout Design Rules, in order to ensure a high probability of defect-freefabrication of all features described in the mask layout.
  • 5. Please follow this example link for a detailed description of the main procedures in "Mask LayoutDesign".Another alternative of generating the mask layout is to make use of automated tools. Please follow thisexample link for a detailed description of generating a layout from a schematic using the device levelplacer.Design Rule Check (DRC) Please follow this example link for a description of how to run DRC on a layout.The created mask layout must conform to a complex set of design rules, in order to ensure a lowerprobability of fabrication defects. A tool built into the Layout Editor, called Design Rule Checker, isused to detect any design rule violations during and after the mask layout design. The detected errorsare displayed on the layout editor window as error markers, and the corresponding rule is alsodisplayed in a separate window. The designer must perform DRC (in a large design, DRC is usuallyperformed frequently - before the entire design is completed), and make sure that all layout errors areeventually removed from the mask layout, before the final design is saved.
  • 6. Circuit Extraction Please follow the example link (button) for a detailed description of "Circuit Extraction".Circuit extraction is performed after the mask layout design is completed, in order to create a detailednet-list (or circuit description) for the simulation tool. The circuit extractor is capable of identifying theindividual transistors and their interconnections (on various layers), as well as the parasitic resistancesand capacitances that are inevitably present between these layers. Thus, the "extracted net-list" canprovide a very accurate estimation of the actual device dimensions and device parasitics that ultimatelydetermine the circuit performance. The extracted net-list file and parameters are subsequently used inLayout-versus-Schematic comparison and in detailed transistor-level simulations (post-layoutsimulation).
  • 7. Layout versus Schematic Check Please follow the example link (button) for a detailed description of "Layout versus Schematic Check".After the mask layout design of the circuit is completed, the design should be checked against theschematic circuit description created earlier. The design called "Layout-versus-Schematic (LVS)Check" will compare the original network with the one extracted from the mask layout, and prove thatthe two networks are indeed equivalent. The LVS step provides an additional level of confidence forthe integrity of the design, and ensures that the mask layout is a correct realization of the intendedcircuit topology. Note that the LVS check only guarantees topological match: A successful LVS will notguarantee that the extracted circuit will actually satisfy the performance requirements. Any errors thatmay show up during LVS (such as unintended connections between transistors, or missingconnections/devices, etc.) should be corrected in the mask layout - before proceeding to post-layoutsimulation. Also note that the extraction step must be repeated every time you modify the mask layout.Post-layout Simulation Please follow the example link (button) for a detailed description of "Post-Layout Simulation".
  • 8. The electrical performance of a full-custom design can be best analyzed by performing a post-layoutsimulation on the extracted circuit net-list. At this point, the designer should have a complete masklayout of the intended circuit/system, and should have passed the DRC and LVS steps with noviolations. The detailed (transistor-level) simulation performed using the extracted net-list will providea clear assessment of the circuit speed, the influence of circuit parasitics (such as parasitic capacitancesand resistances), and any glitches that may occur due to signal delay mismatches.If the results of post-layout simulation are not satisfactory, the designer should modify some of thetransistor dimensions and/or the circuit topology, in order to achieve the desired circuit performanceunder "realistic" conditions, i.e., taking into account all of the circuit parasitics. This may requiremultiple iterations on the design, until the post-layout simulation results satisfy the original designrequirements.Finally, note that a satisfactory result in post-layout simulation is still no guarantee for a completelysuccessful product; the actual performance of the chip can only be verified by testing the fabricatedprototype. Even though the parasitic extraction step is used to identify the realistic circuit conditions toa large degree from the actual mask layout, most of the extraction routines and the simulation modelsused in modern design tools have inevitable numerical limitations. This should always be one of themain design considerations, from the very beginning.After all, there is no substitute for the "real silicon" !Example :Example : Postlayout Simulation (CMOS Inverter) Step 1 : Extracting from the LayoutThe mask layout only contains physical data. In fact it just contains coordinates of rectangles drawn indifferent colors (layers). The extraction process identifies the devices and generates a netlist associatedwith the layout.Make sure you have a layout window with a finished design ready. Make sure that the design does notcontain any DRC errors.1. From the Verify menu select the option Extract( verify --> Extract )A new window with extraction options will appear. The default options will only extract ideal devices.This ideal case would reasult in a list much similar to the schematic. For a more accuraterepresentation, however, we will have to take the parasitic effects into account. To enable the extractionof parasitic devices, a selection parameter called a switch has to be specified. You can type the switchinto the designated box, or you can select it from a menu using the Set Switches option.The switch specified in the example (above) to enable extracting the parasitic capacitances is calledExtract_parasitic_caps.
  • 9. Check the Command Interpreter Window (the main window when you start Cadence) for errors afterextraction.Following a successfull extraction you will see a new cell view called extracted for your cell in thelibrary manager. See the following section for accessing the extracted view.Example : Postlayout Simulation (CMOS Inverter) Step 2 : The Extracted Cell ViewFollowing the extraction step a new cellview is generated in your library. This cell view is calledextracted view.Try loading the cellview. It will open up a layout that looks almost identical to the layout you haveextracted. You will notice that only the I/O pins appear as solid blocks and all other shapes appear asoutlines.The red rectangles indicate that there are a number of instances within this hierarchy. Try pressingShift-F to see all of the hierarchy.This will reveal a number of symbols. If you zoom in you will be able to identify individual elements,such as transistors and capacitors. You will notice that the parameters (e.g. channel dimensions) ofthese devices represent the values they were drawn in the layout view.Apart from your actual devices you will notice a number of elements, mainly capacitors in yourextracted cell view. These are not actual devices, they are parasitic capacitances, side effects formed bydifferent layers you used for your layout.
  • 10. The next step will be to correpond the extracted netlist to that of the schematic. This is called theLayout Versus Schematic checking. This will ensure that the schematic that we have drawn and thelayout are identical.Example : Postlayout Simulation (CMOS Inverter) Step 3 : Layout Versus SchematicIn this step we are going to compare the schematic and the extracted layout to see if they are identical.1. From the Verify menu select the option LVS.If you had previously run a LVS check, this would pop-up a small warning box. Make sure that theoption Form Contents is selected in this box.The top half of the LVS options window is split into two parts. The part on the left corresponds to theschematic cell view and the right part corresponds to the extracted cell view that are to be compared.Make sure that the entries in these boxes represent the values for your circuit.Although there are a number of options for LVS, the default options will be enough for basicoperations, select Run to start the comparison.The comparison algorithm will run in the background, the result of the LVS run will be displayed in amessage box. Be patient, even for a very small design the LVS run can take some time (minutes).The succeeded message in the above message box, indicates that the LVS program has finishedcomparing the netlists, NOT THAT THE CIRCUITS MATCH. It might be the case that the LVS wassuccessful in comparing the netlists and came up with the result that both circuits were different.
  • 11. To see the actual result of an LVS run you have to examine the output of the LVS run. The Outputoption is right next to the Run commandYou can take a look at the complete LVS result here. The most important part of the report can be foundin the figure above. It states that the netlists did indeed match. If you discover that there is a mismatch,you must go back to the layout view and correct the error(s).Most of the other options on the LVS form, are for finding mismatches between two netlists and togenerate netlists that include only parasitic effects relevant to one part of the circuit.Example : Postlayout Simulation (CMOS Inverter) Step 4 : Summary of the Cell Views.So far you have created a number of cell views corresponding to the same circuit. In this section wewant to review all of these cellviews and discuss why they are used.1. Schematic viewFor any design, the schematic should be the first cell view to be created. The schematic will be thebasic reference of your circuit.2. Symbol viewAfter you are done with the schematic, you will need to simulate your design. The proper way of doingthis is to create a seperate test schematic and include your circuit as a block. Therefore you will need tocreate a symbol.3. Layout viewThis is the actual layout mask data that will be fabricated. It can be generated by automated tools ormanually.4. Extracted viewAfter the layout has been finalized, it is extracted, devices and parasitic elements are identified and anetlist is formed.
  • 12. 5. Test SchematicA separate cell is used to as a test bench. This test bench includes sources, loads and the circuit to betested. The test cell usually consists of a single schematic only.Example : Postlayout Simulation (CMOS Inverter) Step 5 : Simulating the Extracted Cell ViewAfter a successful LVS you will have two main cell views for the same circuit. The first one is theschematic, which is your initial (ideal) design, the second is the extracted, that is based on the layoutand in addition to the basic circuit includes all the layout associated parasitic effects. Since both ofthese views refer to the same circuit they can be interchanged.In this example we are going to re-run the simulation example, but we will make the simulator to usethe extracted cell view instead of the schematic cell view.Make sure that you are in the test schematic, that you used to simulate your design earlier.1. Start Analog Artist using Tools --> Analog Artist
  • 13. The Analog Artist window will pop-up.2. From the Setup menu choose the Environment option.A new dialog box controlling various parameters of Analog Artist will pop-up.The line that we will have to alter is called the Switch View List. This entry is an ordered list of cellviews that contain information that can be simulated. The simulator (in fact the netlister) will searchuntil it finds one of these cellviews. The default entry does not contain an extracted cellview. We willsimply add an entry for extracted cellview in front of the schematic cellview.As a result of this modification, the simulator will use the extracted cell view of the cell, if one isavailable.3. Choose analysesIn the simulation example a transient analysis was used, this time we will use a DC simulation. In a DCsimulation the value of any voltage or current source is varied over a specified range. It is used toobtain input/output characteristics of circuits.The basic options of the DC analysis are not very straight-forward. The first step is to determine whatparameter will be swept.Choose Component Parameter as the Sweep Variable.You can select the parameter from the schematic window after you click on Select Component.As each component has a number of parameters, you will be given a list of parameters associated withthe component you select.
  • 14. In the example given above we have selected the DC voltage of the voltage source as the sweepvariable.After we have selected the variable we can decide, the range where the variable will change.This example changes the DC voltage source connected to the input from 0 Volts to 3.3 Volts.The last parameter determines how the sweep will be performed. A linear sweep will increment thevalue of the sweep variable by a fixed amount. The example below uses a step size of 10 millivolts.From this point on the simulation will continue just as it has been described in the Simulation Tutorial,except for the fact that the results will now include parasitic effects from the actual layout.This site contains a complete on-line tutorial for a typical bottom-up design flow using CADENCECustom IC Design Tools (version 97A). The examples were generated using the HP 0.6 umCMOS14TB process technology files, prepared at North Carolina State University (NCSU) and madeavailable through MOSIS.
  • 15. Please click on any box in the design flow (below) to see a detailed description of the corresponding design step, and to view the design examples.

×