About I am a Masters student of Electrical Engineering, actively seeking a full-time opportunity in Digital/ASIC Design & Verification
Very Sound Knowledge of UVM Methodology
Hands on Experience with UVM, SystemVerilog Assertions and Constrained Random Verification Verification techniques
Good Knowledge and Experience related to Digital Circuit Design using Cadence Virtuoso and Simulations using Cadence Spectre.
Passionate about CMOS, Digital Design and ASIC !!
I am available to start immediately !!
Please have a look at my experience in a Remarkable Company like SanDisk Corporation :-
•10+ Months of professional experience in SanDisk Corporation related to ASIC-FPGA Prototyping,Verif.