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Vlsi physical design automation on partitioning
Vlsi physical design automation on partitioning
Vlsi physical design automation on partitioning
Vlsi physical design automation on partitioning
Vlsi physical design automation on partitioning
Vlsi physical design automation on partitioning
Vlsi physical design automation on partitioning
Vlsi physical design automation on partitioning
Vlsi physical design automation on partitioning
Vlsi physical design automation on partitioning
Vlsi physical design automation on partitioning
Vlsi physical design automation on partitioning
Vlsi physical design automation on partitioning
Vlsi physical design automation on partitioning
Vlsi physical design automation on partitioning
Vlsi physical design automation on partitioning
Vlsi physical design automation on partitioning
Vlsi physical design automation on partitioning
Vlsi physical design automation on partitioning
Vlsi physical design automation on partitioning
Vlsi physical design automation on partitioning
Vlsi physical design automation on partitioning
Vlsi physical design automation on partitioning
Vlsi physical design automation on partitioning
Vlsi physical design automation on partitioning
Vlsi physical design automation on partitioning
Vlsi physical design automation on partitioning
Vlsi physical design automation on partitioning
Vlsi physical design automation on partitioning
Vlsi physical design automation on partitioning
Vlsi physical design automation on partitioning
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Vlsi physical design automation on partitioning

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vlsi seminar report

vlsi seminar report

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  • Maximum difference between partition sizes is usually specified as a percentage. For example, if 5% is the maximum allowable imbalance, then a partition cannot have more than 55% of the vertices (or sum of vertex weights) in a 2-way partitioning solutionWhat does cutsize mean?It refers to the number (sum of weights) of the edges that are “cut”, i.e., connect two vertices from two different partitions
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    • 1. VLSI Physical Design Automation Introduction , partitioning Sushil kundu Roll No:20084056 Registration No: 1954 Dept. of Applied Electronics & Instrumentation Engg., University Institute of Technology burdwan
    • 2. Intended Audience• VLSI CAD (also known as EDA – electronic design automation) students, in particular for chip implementation (physical design)• Circuit designers to understand how tools work behind the scene• Process engineers to tune process that is more circuit/physical design friendly• Mathematical/Computer Science majors who want to find tough problems to solve – Lots of VLSI physical design problems can be formulated into combinatorial optimization or mathematical programming problems. – Actually, most CAD problems are NP-complete -> heuristics
    • 3. Objective of this LectureTo review the materials used in fabrication of VLSI devices.To review the structure of devices and process involved in fabricating different types of VLSI circuits.To review the basic algorithm concepts. Understand the process of VLSI layout design. Study the basic algorithms used in layout design of VLSI circuits. Learn about the physical design automation techniques used in the best-known academic and commercial layout systems.
    • 4. Physical Design• Converts a circuit description into a geometricdescription.– This description is used for fabrication of the chip.• Basic steps in the physical design cycle:1. Partitioning2. Floorplanning3. placement4. Routing5. Compaction
    • 5. So, what is Partitioning?System Level Partitioning System PCBsBoard Level Partitioning Chips Chip Level Partitioning Subcircuits / Blocks 6
    • 6. Why partition ?• Ask Lord Curzon  – The most effective way to solve problems of high complexity : Parallel CAD Development• System-level partitioning for multi-chip designs – Inter-chip interconnection delay dominates system performance• IO Pin Limitation• In deep-submicron designs, partitioning defines local and global interconnect, and has significant impact on circuit performance 7
    • 7. Importance of Circuit Partitioning Divide-and-conquer methodology The most effective way to solve problems of high complexityE.g.: min-cut based placement, partitioning-based test generation,… System-level partitioning for multi-chip designs inter-chip interconnection delay dominates system performance. Circuit emulation/parallel simulation partition large circuit into multiple FPGAs (e.g. Quickturn), or multiple special-purpose processors (e.g. Zycad). Parallel CAD development Task decomposition and load balancing In deep-submicron designs, partitioning defines local and global interconnect, and has significant impact on circuit performance…… ……
    • 8. Objectives• Since each partition can correspond to a chip, interesting objectives are: – Minimum number of partitions • Subject to maximum size (area) of each partition – Minimum number of interconnections between partitions • Since they correspond to off-chip wiring with more delay and less reliability • Less pin count on ICs (larger IO pins, much higher packaging cost) – Balanced partitioning given bound for area of each partition 9
    • 9. Partitioning: Partitioning is the task of dividing a circuit into smaller parts .The objective is to partition the circuit into parts, so that the sizeof each component is within prescribed ranges and the number ofconnections between the components is minimized . Different ways to partition correspond to different circuitimplementations . Therefore, a good partitioning can significantlyimprove circuit performance and reduce layout costs .• Decomposition of a complex system into smaller subsystems – Done hierarchically – Partitioning done until each subsystem has manageable size – Each subsystem can be designed independently• Interconnections between partitions minimized – Less hassle interfacing the subsystems – Communication between subsystems usually costly
    • 10. Partitioning of a CircuitInput size: 48Cut 1=4 Cut 2=4Size 1=15 Size 2=16 Size 3=17
    • 11. Hierarcahical Partitioning• Levels of partitioning: – System-level partitioning: Each sub-system can be designed as a single PCB – Board-level partitioning: Circuit assigned to a PCB is partitioned into sub-circuits each fabricated as a VLSI chip – Chip-level partitioning: Circuit assigned to the chip is divided into manageable sub- circuits NOTE: physically not necessary
    • 12. Delay at Different Levels of Partitions x A B D C 10xPCB1 PCB2 20x 13
    • 13. Partitioning: Formal Definition• Input: – Graph or hypergraph – Usually with vertex weights – Usually weighted edges• Constraints – Number of partitions (K-way partitioning) – Maximum capacity of each partition OR maximum allowable difference between partitions• Objective – Assign nodes to partitions subject to constraints s.t. the cutsize is minimized• Tractability- Is NP-complete  14
    • 14. Circuit Representation• Netlist: B – Gates: A, B, C, D A – Nets: {A,B,C}, {B,D}, {C,D} C D• Hypergraph: – Vertices: A, B, C, D – Hyperedges: {A,B,C}, {B,D}, {C,D} B – Vertex label: Gate size/area A – Hyperedge label: Importance of net (weight) C D
    • 15. Circuit Partitioning: Formulation Bi-partitioning formulation: Minimize interconnections between partitions c(X,X’) X X’ • Minimum cut: min c(x, x’) • minimum bisection: min c(x, x’) with |x|= |x’| • minimum ratio-cut: min c(x, x’) / |x||x’| 16
    • 16. A Bi-Partitioning Example a c 100 e 100 100 100 100 9 min-cut 4 b 10 d 100 f mini-ratio-cut min-bisection Min-cut size=13 Min-Bisection size = 300 Min-ratio-cut size= 19Ratio-cut helps to identify natural clusters 17
    • 17. Iterative Partitioning Algorithms• Greedy iterative improvement method (Deterministic) – [Kernighan-Lin 1970]• Simulated Annealing (Non-Deterministic) 18
    • 18. Restricted Partition Problem• Restrictions: – For Bisectioning of circuit – Assume all gates are of the same size – Works only for 2-terminal nets• If all nets are 2-terminal, hypergraph  graph b b a a c d c d Hypergraph Graph Representation Representation 19
    • 19. Problem Formulation• Input: A graph with – Set vertices V (|V| = 2n) – Set of edges E (|E| = m) – Cost cAB for each edge {A, B} in E• Output: 2 partitions X & Y such that – Total cost of edge cuts is minimized – Each partition has n vertices• This problem is NP-Complete!!!!! 20
    • 20. A Trivial Approach• Try all possible bisections and find the best one• If there are 2n vertices, # of possibilities = (2n)! / n!2 = nO(n)• For 4 vertices (a,b,c,d), 3 possibilities 1. X={a,b} & Y={c,d} 2. X={a,c} & Y={b,d} 3. X={a,d} & Y={b,c}• For 100 vertices, 5x1028 possibilities• Need 1.59x1013 years if one can try 100M possbilities per second 21
    • 21. Definitions• Definition 1: Consider any node a in block X. The contribution of node a to the cutset is called the external cost of a and is denoted as Ea, where Ea =Σcav (for all v in Y)• Definition 2: The internal cost Ia of node a in X is defined as follows: Ia =Σcav (for all v in X)
    • 22. Example• External cost (connection) Ea = 2• Internal cost Ia = 1 X b Y c a d
    • 23. Idea of KL Algorithm• Da = Decrease in cut value if moving a = Ea-Ia – Moving node a from block X to block Y would decrease the value of the cutset by Ea and increase it by Ia X b Y X b Y c c a d a d Da = 2-1 = 1 Db = 1-1 = 0
    • 24. Idea of KL Algorithm• Note that we want to balance two partitions• If switch A & B, gain(A,B) = DA+DB-2cAB – cAB : edge cost for AB X B Y X B Y C C D A A D gain(A,B) = 1+0-2 = -1
    • 25. Idea of KL Algorithm• Start with any initial legal partitions X and Y• A pass (exchanging each vertex exactly once) is described below: 1. For i := 1 to n do From the unlocked (unexchanged) vertices, choose a pair (A,B) s.t. gain(A,B) is largest Exchange A and B. Lock A and B. Let gi = gain(A,B) 2. Find the k s.t. G=g1+...+gk is maximized 3. Switch the first k pairs• Repeat the pass until there is no improvement (G=0)
    • 26. Example X Y X Y 1 4 4 1 2 5 2 5 3 6 3 6Original Cut Value = 9 Optimal Cut Value = 5 A good step-by-step example in SY book
    • 27. Time Complexity of KL• For each pass, – O(n2) time to find the best pair to exchange. – n pairs exchanged. – Total time is O(n3) per pass.• Better implementation can get O(n2log n) time per pass.• Number of passes is usually small.
    • 28. Recap of Kernighan-Lin’s Algorithm Pair-wise exchange of nodes to reduce cut size Allow cut size to increase temporarily within apass Compute the gain of a swap Repeat Perform a feasible swap of max gain Mark swapped nodes “locked”; u v a Update swap gains;Until no feasible swap; v uFind max prefix partial sum in gain sequence g1, lockedg2, …, gmMake corresponding swaps permanent. Start another pass if current pass reduces thecut size (usually converge after a few passes)
    • 29. Other Partitioning Methods• KL and FM have each held up very well• Min-cut / max-flow algorithms – Ford-Fulkerson – for unconstrained partitions• Ratio cut• Genetic algorithm• Simulated annealing
    • 30. References and Copyright Textbooks referred (none required)  [Mic94] G. De Micheli “Synthesis and Optimization of Digital Circuits” McGraw-Hill, 1994.  [CLR90] T. H. Cormen, C. E. Leiserson, R. L. Rivest “Introduction to Algorithms” MIT Press, 1990.  [Sar96] M. Sarrafzadeh, C. K. Wong “An Introduction to VLSI Physical Design” McGraw-Hill, 1996.  [She99] N. Sherwani “Algorithms For VLSI Physical Design Automation” Kluwer Academic Publishers, 3rd edition, 1999.
    • 31. THANK YOU

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