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Not bridge  south bridge archexture Not bridge south bridge archexture Presentation Transcript

  • 1 Homework • Reading – None (Finish all previous reading assignments) • Machine Projects – Continue with MP5 • Labs – Finish lab reports by deadline posted in lab
  • 2 Hierarchy for 80286 Memory and I/O • IBM PC-AT (“Advanced Technology” in 1984) • DOS 3.0 Operating System • PC-AT bus evolved into Industry Standard Bus • Many manufacturers built ISA-based PCs/cards • ISA Bus – Slow 6 MHz evolved to 8 MHz or 125 nsecs/cycle – Address Bus 20 bits – Data Bus 16 bits
  • 3 IBM PC-AT Reference: http://www.vintage-computer.com/ibmpcat.shtml
  • 4 Big Picture (80286) RTC Keyboard Serial Port Parallel Port Floppy Disk 80286 RAM Memory ROM Memory ISA Bus: 20/16 bits, 8 MHz (125 nsecs/cycle) Hard Disk
  • 5 Hierarchy for 80486 Memory and I/O • CPU Clock: 66 MHz • Local Bus or CPU Bus – “Fast” 33MHz / 32 bits wide • Expansion Bus Controller (CPU-ISA Bridge) • ISA Bus (Legacy) – “Slow” 8 MHz or 125 nsecs/cycle – Address Bus 20 bits – Data Bus 16 bits
  • 6 Big Picture (80486) CPU Local bus or CPU bus: fast (33 MHz, 32 bits) [30 nsec./cycle] Memory Cache Video Adapter Disk Expansion Bus Controller RTC ISA bus: slow (8 MHz, 8/16 bits) [125 nsec./cycle] Keyboard Serial Port Parallel Port Floppy Disk System ROM
  • 7 Competition for ISA replacement • Many vendors proposed busses to replace ISA as the technology improved – IBM: Micro Channel Architecture (MCA) – Extended Industry Standard Architecture (EISA) – VESA Local Bus – Intel: Peripheral Component Interconnect (PCI) • PCI had won commercial battle by mid-90’s • For a while PCs had a mix of ISA and PCI slots
  • 8 Hierarchy for Pentium 4 Memory and I/O • CPU Clock Speed – “Fast” 2 – 2.5 GHz • CPU “Front End” Bus Speed – “Fast” 533 MHz / 64 bits wide evolved to 800 MHz • CPU-PCI Bridge (“North Bridge”) • PCI Bus (Most prevalent peripheral bus after ISA) – “Medium Speed”: 33 or 66 MHz / 32 or 64 bits wide • PCI-ISA Bridge (“South Bridge”) • ISA Bus (Most prevalent “Legacy” peripheral bus) – “Slow Speed”: 8 Mhz / 20 and 16 Bits
  • 9 The Big Picture (Pentium) Pentium CPU CPU bus: fast (100 MHz, 64 bits) [10 nsec./cycle] MemoryCache Video Adapter System ROM Expansion Bus Controller RTC ISA bus: slow (8 MHz, 8/16 bits) [125 nsec./cycle] Keyboard Serial Port Parallel Port Floppy Disk PCI Controller PCI bus: fast (33 MHz, 32/64 bits) [30 nsec./cycle] Disk “South Bridge” “North Bridge”
  • 10 Motherboard Chipsets • The motherboard chip set provides the core logic and manages the motherboard's functions. • Several companies (including ATI, Intel, and nVidia) make motherboard chip sets, most of which offer the same basic features. • The variants of nVidia's nForce4 chip set were the most widely used on the boards though Intel's 975X Express has become increasingly popular for Intel- based motherboards.
  • 11 North Bridge Expansion Bus Controller (CPU-PCI) “North Bridge” M/IO# D/C# W/R# AEN# A31-A3 BE7# - BE0# CLK BRDY# CPU Bus PCI Bus AD[31:0] C/BE#[3:0] FRAME# TRDY# IRDY# STOP# REQ# GNT# D31-D0
  • 12 South Bridge Expansion Bus Controller (PCI-ISA) “South Bridge” CLK MEMR# MEMW# IOR# IOW# INTA# A23-A0 PCI Bus ISA Bus AD[31:0] C/BE#[3:0] FRAME# TRDY# IRDY# STOP# REQ# GNT# D23-D0
  • 13 Pentium 4 CPU Specifications • The Pentium 4 Processor –Introduced: May 6, 2002 –512KB level-two cache –Operating at 533 MHz “front side bus” speed –Available now at 2.53 GHz, 2.4 GHz and 2.26 GHz and is priced at $637, $562 and $423, respectively, in 1,000-unit quantities. –Benchmarks: SPECint*_base2000 score of 882 SPECfp*_base2000 score of 860 –"Springdale" will have a FSB speed of 800 MHz
  • 14 Pentium CPU Block Diagram
  • 15 Enhancing Performance • “Pipelining is an implementation technique in which multiple instructions are overlapped in execution”, (Patterson and Hennessey, “Computer Organization and Design”, p. 436) Sequential Execution: Pipelined Execution: Reg Read ALU Operation Instruction Fetch Data Memory Reg Write Load Word 8 ns Reg Read ALU Operation Instruction Fetch Data Memory Reg Write 8 ns Reg Read Instruction Fetch Load Word Load Word Reg Read ALU Operation Instruction Fetch Data Access Reg Write Load Word 2 ns Reg Read ALU Operation Instruction Fetch Data Memory Reg Write Reg Read Instruction Fetch Load Word Load Word ALU Operation Data Memory Reg Write 2 ns 2 ns
  • 16 Pipeline Example (Cont’d) • Pipelining improves the overall performance by increasing instruction throughput per unit time not decreasing execution time of an individual instruction • Ideal speedup is number of stages in the pipeline • Do we achieve this? Sometimes / Not always –Notice the idle time in the pipe at certain times –Flushing pipeline during conditional jumps –Data being calculated by previous instruction may be needed too early in the next instruction
  • 17 Superscalar Processors IF OF EX OS IF OF EX OS IF OF EX OS IF OF EX OS IF OF EX OS IF OF EX OS IF OF EX OS IF OF EX OS IF OF EX OS IF OF EX OS 0 1 2 3 4 5 6 7 8 9 Time in Base Cycles • More than one execution pipeline executing in parallel • Note: Possible coordination problems must be resolved
  • 18 Custom Digital Signal Processor • Application is hard real time system – processing analog modem waveforms • Computations based on complex arithmetic • Rotation of a vector (e.g. carrier frequency) – Complex multiply • Filtering of a sequence of signal samples – Loop doing complex multiply and addition
  • 19 Digital Signal Processor Architecture Signal Processing Controller (SPC) Fetch and Execute Instructions Multiplier-Accumulator-Ram (Real) Multiplier-Accumulator-Ram (Imaginary) Data Bus Real MAR Chip Select Imaginary MAR Chip Select Address/Modulo Registers ALU ALUMemoryMemory SPC Program MemoryR0 R1 N0 N1 Controlling Host Processor (68000) Analog/Digital Converter From Phone Line Digital/Analog Converter To Phone Line Address Bus
  • 20 Addresses and Complex Data • Addresses stored in SPC Registers – Pointers to complex data in MAR memories – Register post increment modes: Increment by one Decrement by one Increment by one modulo specified N register Decrement by one modulo specified N register • Complex numbers stored in MAR memories: – Real part in one MAR (Real MAR) – Imaginary part in other MAR (Imaginary MAR)
  • 21 Multiplier-Accumulator-RAM X-Register Y-RegisterMultiplier Adder 256 Words of RAM Memory Accumulator MPY MAC To Other MARFrom Other MAR Address from SPC Selector Chip Select From SPC Selector
  • 22 SPC/MAR Assembly Programming • Complex Multiply (RR0 * RR1 – IR0 * IR1) + i (RR0 * IR1 + RR1 * IR0) YPP.P MP.R1 Load both Y from own memory at R1 address MPY.P MR.R0 Multiply both with real memory at R0 address YMM.R MI.R1 Load minus real Y from imag memory at R1 address YPP.I MR.R1 Load imag Y from real memory at R1 address MAC.P MI.R0 Multiply/add both with imag memory at R0 address NOP Result not ready yet: NOP or housekeeping NOP Result not ready yet: NOP or housekeeping STA.P MP.R0 Store each acc. in own memory at R0 address