crosstalk minimisation using vlsi

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  • 1. Minimisation of crosstalk in VLSI 1 Presented By: Subhradeep Mitra Ankita Dutta Paramita Sau Debanjana Biswas (Mca Students of Rajabazar sc. College)
  • 2. 2 Outlines • VLSI DESIGN CYCLE • PHYSICAL DESIGN CYCLE • ROUTING • PHASES OF ROUTING • CROSSTALK OVERVIEW •EFFECT OF CROSSTALK •HOW TO MINIMIZE CROSSTALK •HOW TO PREVENT CROSSTALK • CONCLUSION •REFERENCES
  • 3. 3 VLSI Design Cycle • The VLSI design cycle starts with a formal specification of a VLSI chip follows a series of steps, and eventually produces a packaged chip The steps included into the VLSI Design Cycle are as follows : • System Specification • Architectural Design • Behavioral or Functional Design • Logic Design • Circuit Design • Physical Design • Fabrication • Packaging, Testing and Debugging
  • 4. 4 Physical Design Cycle The input of the physical design cycle is a circuit diagram and the output is the layout of the circuit. This is accomplished in several stages. The stages are following:- 1) Partitioning 2) Floorplanning and Placement 3) Routing 4) Compaction 5) Extraction and verification
  • 5. 5 Routing The Routing is to locate a set of wires in the routing space that connect all the nets in the net list.The capacity of channels width of wires, and wire crossing often need to be taken into consideration.  Problem :  Input : • Netlist • Timing budget for typically critical nets • Placement information including location of blocks, location of pins in the block boundary, location of the I/O pins on the chip boundary etc.  Output : • Geometric layouts of all nets
  • 6. 6  Objectives of Routing: • Minimize the total wire length • Minimize the no of layers ( fewer layer is less expensive) •Minimize the no of vias,bends i.e. completing all connection without increasing the chip area • Minimize the crosstalk
  • 7. 7 PHASES OF ROUTING:- Routing Global Routing Detailed Routing Line Routing Maze Routing Channel Routing Switch Box Routing
  • 8. 8 Global Routing:-. • It‟s the first phase of routing and generates a „loose‟ route for each net. • Minimize the total wire length • Minimize running time •The global routing considers the entire layout. • This routing consists of three distinct phases- i. Region Definition ii. Region Assignment iii. Pin Assignment Global Routing
  • 9. 9 Detailed Routing:- • It‟s the second phase, of routing to finds the actual geometric layout of each net within the assigned routing regions. • Three types of detailed routing methods:- i) Channel Routing ii) 2-D Switchbox Routing iii) 3-D Switchbox Routing • Channel Routing 2-D Switchbox 3-D switchbox • If the switchbox or channels are unroutable without a large expansion, global routing to be done again Detailed Routing
  • 10. 10 Crosstalk 1. Mutual inductance (magnetic field) 2. Mutual capacitance (electric field)  Definition : The electromagnetic coupling of a signal from one conductor to another is called as crosstalk  Crosstalk can be classified into the following two types:
  • 11. 11 1. Mutual Inductance : • Mutual inductance Lm induces current from a driver line onto a quiet line by means of the magnetic field. • The mutual inductance Lm will inject a voltage noise onto the victim proportional to the rate of change of the current on the driver line. The magnitude of this noise is calculated as
  • 12. 12 • Due to the recent trends of higher aspect ratios and lower spacing between signal lines, the coupling capacitance is becoming significant. Also the vertical height has not been scaled down . 2. Mutual Capacitance:-
  • 13. 13 • If one line is switching and the other line is steady the energy transfer through the coupling capacitance results in a glitch on the quiet line • The inductively induced voltages were generally negligible compared to the effects of the parasitic capacitances of the interconnect lines. • The interconnect capacitance is modeled as Mutual Capacitance. d(Vvictim – Vdriver) dt
  • 14. 14 Crosstalk induced noise: Crosstalk is the result of mutual capacitance Cm in conjunction with mutual inductance Lm between adjacent conductors. For simplicity and for measuring the magnitude of noise induced on to the adjacent transmission lines we have to consider the two terms : • Near-end-crosstalk • Far-end-crosstalk
  • 15. 15 • The current generated on the victim line due to mutual capacitance will split and flow toward both ends of the adjacent line. • The current generated on the victim line due to mutual inductance will flow from the far end toward the near end of the victim line • As a result, the crosstalk currents flowing toward the near and far ends can be broken down into several components: •Near end crosstalk is always positive •Far end crosstalk is always negative
  • 16. 16 Effects of Crosstalk: • Signal Integrity Illustration • Noise on Delay effect • Destroying Local Information • Timing Noise
  • 17. 17 1. Signal Integrity Illustration: The term Signal Integrity (SI) addresses two concerns in the electrical design aspects – the timing and the quality of the signal. Due to crosstalk: •the signal doesn’t reach its destination when it is supposed to •when it gets there, it is not in good condition
  • 18. 1818 2. Noise on delay effect Depending on the signal switching directions of the signals on the driver and victim nets, the impact of interconnect cross-talk can be either, •negative (increasing signal propagation time) •positive (decreasing signal propagation time), which may cause setup- or hold-time violations.
  • 19. 19 3. Destroying local information: When noise acts against a normally static signal, it can destroy the local information carried by the static node in the circuit and ultimately result in incorrect machine-state stored in a latch. 4. Timing noise This includes the noise by, • Skew – that is the DC components of the noise • Jitter – that is the AC components of the noise
  • 20. 20 Basic Approaches in Crosstalk Avoidance  Segregation / Spacing / Ground Shielding  Net Ordering  Layer Assignment
  • 21. 21 N oisy R egion Q uiet R egion Segregation Spacing Extra space Segregation / Spacing/ Ground Shielding (1)
  • 22. 22 Segregation / Spacing/ Ground Shielding (2)  Segregation : Dividing many (noisy) and less(quiet) signal transition wire and merging group by group.(use with shielding)  Spacing : Spacing can be of two types:  Increasing line spacing capacitive coupling can be decreased.  Widening metal wires decrease the effect of capacitive coupling by increasing the line to ground capacitance to the total capacitance ratio.  Shielding : blocking signal line with ground line to minimize signal interference to the other wire.(ground bounce occurs and must broaden the ground line)  Shielding type 1  Shieling type 2
  • 23. 23 Net Ordering  Left : Unordered track permutation  Right : Ordered track permutation for minimizing crosstalk SS SS LL LL LL SS SS LL LL LL  Net ordering is used for minimize crosstalk-critical region between each lines. When, long line and long line is close together, crosstalk between them is more larger than long line and short line. So, we must change the permutation of track for minimizing crosstalk.
  • 24. 24 Layer Assignment O rdered net Layer1 U nodered net Layer2 Layer3  When using more than 3 layer in channel routing, adjacent signal wire in same layer results crosstalk. For example, left figure makes more crosstalk than right.  Layer assignment problem is solved by integer linear programming or dynamic programming method.
  • 25. 25 Minimize Crosstalk: Rule of Thumb • Widen spacing S between the lines as much as routing restrictions will allow • Minimize H while achieving the target impedance of the design • Use differential routing techniques for critical nets
  • 26. 26 •Routing adjacent layers orthogonal if there is significant inter layer coupling • If possible routing the signals on a strip layer or as an embedded micro- strip to eliminate velocity variation • Minimize parallel run lengths between signals, routing with short parallel sections and minimize long coupled sections between nets • If possible, use slow edge rates (with extreme caution on timing uncertainty)
  • 27. 27 Recently FinFET is used instead of CMOS in VLSI because, FinFET can be significantly more power efficient than CMOS at the same gate length. Conclusion : • Future scope : • NP-hard problem • Optimal solution are taken because some other constraints are there like wire length and congestion
  • 28. 28 References : • “Algorithms for VLSI Physical design Automation by – Naveed Sherwani • “VLSI Design Automation” – Kia Bazragar • J.J.Xiong & L.He.IEEE Transon CAD, 2008 • US PATIENT, PATINENT NO : US 6, 218, 631B1
  • 29. 29 Thank You…