Ignou mca mcs 12 solved assignment 2011


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Ignou mca mcs 12 solved assignment 2011

  1. 1. Course Code : MCS-012Course Title : Computer Organisation and Assembly Language ProgrammingAssignment Number : MCA(1)/012/Assign/2011Maximum Marks : 100Weightage : 25%Last Dates for Submission : 15th April, 2011 (For January Session) 15th October, 2011 (For July Session)There are four questions in this assignment, which carries 80 marks. Rest 20 marks are for viva voce. You may use illustrations and diagrams to enhance the explanations. Please go through the guidelines regarding assignments given in the Programme Guide for the format of presentation. Answer to each part of the question should be confined to about 300 words.Question 1:(a) Perform the following arithmetic operations using binary signed 2’s complement notation for integers. You may assume that the maximum size of integers is of 10 bits including the sign bit. (Please note that the numbers given here are in decimal notation) (3 Marks)i) Add – 498 and 260Ans:ii) Subtract 456 from – 56Ans: Page 1
  2. 2. iii) Add 256 and 255Ans:(b) Convert the hexadecimal number: FA BB C9 into binary, octal and decimal. (1 Mark)Ans1: (FA BB C9)16 = (0110011001001011000111)2Ans2: (FA BB C9)16 = (77735711)8Ans3: (FA BB C9)16 = (16759753)10(c) Convert the following string into equivalent ASCII code – “Copyright © 2001 - 2011”. Include ASCII code of spaces between words in the resultant ASCII. Are these codes same as that used in Unicode? (2 Marks)Ans: 43h6fh70h79h72h69h67h68h74h20h28h43h29h20h32h30h30h30h20h32h30h31h31h Character ASCII UNICODE C 43H 0043 o 6FH 006F p 70H 0070 y 79H 0079 r 72H 0072 i 69H 0069 g 67H 0067 h 68H 0068 t 74H 0074 space 20H 0020 ( 28H 0028 c 43H 0043 ) 29H 0029 space 20H 0020 2 32H 0032 0 30H 0030 0 30H 0030 0 30H 0030 space 20H 0020 Page 2
  3. 3. 2 32H 0032 0 30H 0030 1 31H 0031 1 31H 0031 Yes the codes are same in ASCII & UNICODE(d) Design a logic circuit that accepts a four digit binary input and creates an odd parity bit, a sign check bit and a more than two zero value test bit. The odd parity bit is created for the four bit data. The sign bit is set to 1 if the left most bit of the data is 1. Zero value bit is set to 1 if three of the input bits are zero. Draw the truth table and use K-map to design the Boolean expressions for each of the output bits. Draw the resulting circuit diagram using AND – OR – NOT gates. (5 Marks)Ans: Page 3
  4. 4. (e ) A sequential circuit has two D flip flops A and B, two inputs x and y and one output z. Flip flops input equations and the circuit output are as follows: (5 Marks) DA = x B’ DB = y A + x’ A’ z=A+B (i) Draw the circuit diagram for the above. ClockX Y CxB’ A D A CyA’ A’ Z Cx’A’ B D B CyA+x’A’ B’ (ii) Tabulate the state table for the flip flops. Present State Next State x y A B A B 0 0 0 0 0 0 0 1 0 0 1 0 0 0 1 1 0 1 0 0 0 1 0 1 0 1 1 0 0 1 1 1 1 0 0 0 1 0 0 1 Page 4
  5. 5. 1 0 1 0 1 0 1 1 1 1 0 0 1 1 0 1 1 1 1 0 1 1 1 1(f) Design a floating point representation of 32 bits closer to IEEE 754 format except that the exponent of the representation should be of 4 bits only. You may assume that the mantissa is in normalised form; the exponent bias of 7; and one bit is used for the sign bit. Represent the number (89.125) 10 using this format . (4 Marks)Ans:Question 2:(a) A RAM has a capacity of 64 K × 64. (2 Marks) (i) How many data input and data output lines does this RAM need to have? Ans: 64, since the word size is 64. (ii) How many address lines will be needed for this RAM? Ans: 64K = 64 × 1024 = 65536 words. Hence, there are 65536 memory addresses. Since 65536 = 16 2 it requires 16 bits address code to specify one of 65536 addresses. Page 5
  6. 6. (b) Consider a RAM of 256 words with a word size of 16 bits. Assume that this memory have a cache memory of 8 Blocks with block size of 32 bits. For the given memory and Cache in the statements as above, draw a diagram to show the address mapping of RAM and Cache, if direct memory to cache mapping scheme is used. (4 Marks)Ans: Page 6
  7. 7. (c) You want to read a file from a disk. Explain how the I/O will be performed if (4 Marks) (i) Interrupt Driven Input/ Output Scheme is used. Ans: With interrupt driven I/O, when the interface determines that the device is ready for data transfer, it generates an interrupt request to the computer. Upon detecting the external interrupt signal, the processor stops the task it is processing, branches to a service program to process the I/O transfer, and then returns to the task it was originally performing which results in the waiting time by the processor being reduced. The interrupt-driven I/O mechanism for transferring a block of data is shown in Figure. Please note that after issuing a read command (for input) the CPU goes off to do other useful work while I/O interface proceeds to read data from the associated device. On the completion of an instruction cycle, the CPU checks for interrupts (which will occur when data is in data register of I/O interface and it now needs CPU’s attention). Now CPU saves the important register and processor status of the executing program in a stack and requests the I/O device to provide its data, which is placed on the data bus by the I/O device. After taking the required action with the data, the CPU can go back to the program it was executing before the interrupt. Interrupt-Processing The occurrence of an interrupt fires a numbers of events, both in the processor hardware and software. Figure 8 shows a sequence. When an I/O device completes an I/O operation, the following sequence of hardware events occurs: 1. The device issues an interrupt signal to the processor. 2. The processor finishes execution of the current instruction before responding to the interrupt. 3. The processor tests for the interrupts and sends an acknowledgement signal to the device that issued the interrupt. Page 7
  8. 8. 4. The minimum information required to be stored for the task being currently executed, before the CPU starts executing the interrupt routine (using its registers) are: (a) The status of the processor, which is contained in the register called program status word (PSW), and (b) The location of the next instruction to be executed, of the currently executing program, which is contained in the program counter (PC).5. The processor now loads the PC with the entry location of the interrupt-handling program that will respond to this interrupting condition. Once the PC has been loaded, the processor proceeds to execute the next instruction, that is the next instruction cycle, which begins with an instruction fetch. Because the instruction fetch is determined by the contents of the PC, the result is that control is transferred to the interrupt-handler program. The execution results in the following operations:6. The PC & PSW relating to the interrupted program have already been saved on the system stack. In addition, the contents of the processor registers are also needed to be saved on the stack that are used by the called Interrupt Servicing Routine because these registers may be modified by the interrupt-handler. Figure shows a simple example. Here a user program is interrupted after the instruction at location N. The contents of all of the registers plus the address of the next instruction (N+1) are pushed on to the stack.7. The interrupt handler next processes the interrupt. This includes determining of the event that caused the interrupt and also the status information relating to the I/O operation.8. When interrupt processing is complete, the saved register values are retrieved from the stack and restored to the registers, which are shown in Figure .9. The final step is to restore the values of PSW and PC from the stack. As a result, the instruction to be executed will be from the previously interrupted program. Page 8
  9. 9. (ii) Direct Memory Access is used. In both interrupt-driven and programmed I/O, the processor is busy with executing input/output instructions and the I/O transfer rate is limited by the speed with which the processor can test and service a device. What about a technique that requires minimal intervention of the CPU for input/output? These two types of drawbacks can be overcome with a more efficient technique known as DMA, which acts as if it has taken over control from the processor. Hence, the question is: why do we use DMA interface? It is used primarily when a large amount of data is to be transferred from the I/O device to the Memory. DMA Function Although the CPU intervention in DMA is minimised, yet it must use the path between interfaces that is the system bus. Thus, DMA involves an additional interface on the system bus. A technique called cycle stealing allows the DMA interface to transfer one data word at a time, after which it must return control of the bus to the processor. The processor merely delays its operation for one memory cycle to allow the directly memory I/O transfer to “steal” one memory cycle. When an I/O is requested, the processor issues a command to the DMA interface by sending to the DMA interface the following information (Figure 10): • Which operations (read or write) to be performed, using the read or write control lines. • The address of I/O devices, which is to be used, communicated on the data lines. • The starting location on the memory where the information will be read or written to be communicated on the data lines and is stored by the DMA interface in its address register. • The number of words to be read or written is communicated on the data lines and is stored in the data count register. The DMA interface transfers the entire block of data, one word at a time, directly to or from memory, without going through the processor. When the transfer is complete, the DMA interface sends an interrupt signal to the processor. Thus, in DMA the processor involvement can be restricted at the beginning and end of the transfer, which can be shown as in the figure above. But the question is when should the DMA take control of the bus? For this we will recall the phenomenon of execution of an instruction by the processor. Figure 11 below shows the five cycles for an instruction execution. The Figure also shows the five points where a DMA request can be responded to and a point where the interrupt request can be responded to. Please note that an Page 9
  10. 10. interrupt request is acknowledged only at one point of an instruction cycle, and that is at the interrupt cycle.(d) Find the average disk access time that reads or writes a 512 byte sector. Assume that the disk rotates at 12000 rpm; each track of the disk has 100 sectors and data transfer rate of the disk is 100 MB/second. (Please calculate data transfer time for the disk in addition to the seek time and latency time). Also find out what is meant by the controller overhead in the context of disk access time. (2 Marks)Ans:(e) What is the purpose of FAT? Explain. (2 Marks) (Word limit for the answer is 200 words ONLY)Ans: The FAT file system was first introduced in the days of MS-DOS way back in 1981. The purpose of the File Allocation Table is to provide the mapping between clusters - the basic unit of logical storage on a disk at the operating system level - and the physical location of data in terms of cylinders, tracks and sectors - the form of addressing used by the drives hardware controller. The FAT contains an entry for every file stored on the volume that contains the address of the files starting cluster. Each cluster contains a pointer to the next cluster in the file, or an end-of- file indicator at (0xFFFF), which indicates that this cluster is the end of the file. The diagram shows three files: File1.txt uses three clusters, File2.txt is a fragmented file that requires three Page 10
  11. 11. clusters and File3.txt fits in one cluster. In each case, the file allocation table entry points to the first cluster of the file(f) Define each of the following term. Explain the main purpose / use / advantage of the term.(Word Limit for answer of each part is 50 words ONLY) (6 Marks) (i) DIMM Ans: Dual Inline Memory Module or DIMM is a series of Random Access Memory (RAM) chips mounted on a small printed circuit board. The entire circuit collectively forms a memory module. DIMMs are commonly used in personal computers, servers and high-end workstations. The DIMM makes physical contact with the data bus of the computer through teeth like connectors that fit into a socket on the mother board. DIMMs use a 64-bit data path, since processors used in personal computers including the Intel Pentium have a 64-bit data width. (ii) LCD monitors Ans: LIQUID CRYSTAL DISPLAYS (LCD) LCDs are the screens of choice for portable computers and lightweight screens. They consume very little electricity and have advanced technologically to quite good resolutions and colour support. They were developed by the company RCA in the 1960s. LCDs function simply by blocking available light so as to render display patterns. (iii) Core of a processor Ans: The "core" in a processor is the microprocessor inside of the CPU (Central Processing Unit). It is the part of the processor that actually performs the reading and executing of instructions. For example, if we have a Dual Core CPU then we have 2 microprocessors inside of the CPU, this allows us to do two things at once, as a microprocessor can only do one thing at a time the only exception to this is Multi-Threading which allows one core to do the work of multiple cores, but its not as fast as having multiple cores. (iv) SATA Ans: Serial ATA (SATA or Serial Advanced Technology Attachment) is a computer bus interface for connecting host bus adapters to mass storage devices such as hard disk drives and optical drives. Serial ATA was designed to replace the older ATA (AT Attachment) standard (also known as EIDE), offering several advantages over the older parallel ATA (PATA) interface: reduced cable-bulk and cost (7 conductors versus 40), native hot swapping, faster data transfer through higher signaling rates, and more efficient transfer through an (optional) I/O queuing protocol. Page 11
  12. 12. SATA host-adapters and devices communicate via a high-speed serial cable over two pairs of conductors. In contrast, parallel ATA (the redesignation for the legacy ATA specifications) used a 16-bit wide data bus with many additional support and control signals, all operating at much lower frequency. To ensure backward compatibility with legacy ATA software and applications, SATA uses the same basic ATA and ATAPI command-set as legacy ATA devices.(v) RAID level 5Ans: This level belongs to independent access category. Its main features are: a) Employs independent access as that of level 4 and distributes the parity strips across all disks. b) The distribution of parity strips across all drives avoids the potential input/output bottleneck found in level 4. I/O Request Rate Read is Excellent while write is fair Data Transfer Rate Read is fair while write is poor It is used in High request rate read intensive, data lookup applications(vi) Zone Bit Recording (ZBR) in the context of disksAns: Zone Bit Recording (ZBR) is used by disk drives to store more sectors per track on outer tracks than on inner tracks. It is also called Zone Constant Angular Velocity (Zone CAV or Z-CAV or ZCAV). On a disk consisting of concentric tracks, the physical track length may or may not be increased with distance from the center hub. Therefore, holding storage density constant, the track storage capacity likewise increases with distance from the center. ZBR is a compromise between CLV (which packs the most bits onto a disk, but has very slow seek times) and CAV (which has faster seek times, but stores fewer bits on a disk). Hard disk controllers implement ZBR by varying the rate at which it reads and writes - faster on outer tracks. Some other ZBR drives, such as the 3.5" floppy drives in the Apple IIGS and older Macintosh computers, spin the medium faster when reading or writing inner tracks. One side effect of ZBR is the raw data transfer rate of the disk when reading the outside tracks is much higher -- in some disks, about double -- the data transfer rate of the same disk when reading the "inner" (closest to the hub) tracks. Page 12
  13. 13. Question 3:(a) Assume that a new programming language has been developed that have an extensive use of data and instruction arrays. Such a programming language requires efficient handling of arrays. This language supports call by reference as arrays are being passed by reference. The language does not support recursion. You have been assigned the task to design the addressing modes for a machine that supports this new programming language. List four addressing mode that must be supported by such a machine. Give justification of the selection of each of the addressing modes. (4 Marks)Ans: Types of Addressing Modes Each instruction of a computer specifies an operation on certain data. The are various ways of specifying address of the data to be operated on. These different ways of specifying data are called the addressing modes. The most common addressing modes are: • Immediate addressing mode • Direct addressing mode • Indirect addressing mode • Register addressing mode • Register indirect addressing mode • Displacement addressing mode • Stack addressing mode To specify the addressing mode of an instruction several methods are used. Most often used are : a) Different operands will use different addressing modes. b) One or more bits in the instruction format can be used as mode field. The value of the mode field determines which addressing mode is to be used. The effective address will be either main memory address of a register. Immediate Addressing: This is the simplest form of addressing. Here, the operand is given in the instruction itself. This mode is used to define a constant or set initial values of variables. The advantage of this mode is that no memory reference other than instruction fetch is required to obtain operand. The disadvantage is that the size of the number is limited to the size of the address field, which most instruction sets is small compared to word length. INSTRUCTION OPERAND Direct Addressing: Page 13
  14. 14. In direct addressing mode, effective address of the operand is given in the address field of theinstruction. It requires one memory reference to read the operand from the given location andprovides only a limited address space. Length of the address field is usually less than theword length.Ex : Move P, Ro, Add Q, Ro P and Q are the address of operand.Indirect Addressing:Indirect addressing mode, the address field of the instruction refers to the address of a wordin memory, which in turn contains the full length address of the operand. The advantage ofthis mode is that for the word length of N, an address space of 2N can be addressed. Hedisadvantage is that instruction execution requires two memory reference to fetch theoperand Multilevel or cascaded indirect addressing can also be used.Register Addressing:Register addressing mode is similar to direct addressing. The only difference is that theaddress field of the instruction refers to a register rather than a memory location 3 or 4 bitsare used as address field to reference 8 to 16 generate purpose registers. The advantages ofregister addressing are Small address field is needed in the instruction.Register Indirect Addressing:This mode is similar to indirect addressing. The address field of the instruction refers to aregister. The register contains the effective address of the operand. This mode uses onememory reference to obtain the operand. The address space is limited to the width of theregisters available to store the effective address.Displacement Addressing:In displacement addressing mode there are 3 types of addressing mode. They are :1) Relative addressing2) Base register addressing3) Indexing addressing.This is a combination of direct addressing and register indirect addressing. The valuecontained in one address field. A is used directly and the other address refers to a registerwhose contents are added to A to produce the effective address.Stack Addressing: Page 14
  15. 15. Stack is a linear array of locations referred to as last-in first out queue. The stack is a reserved block of location, appended or deleted only at the top of the stack. Stack pointer is a register which stores the address of top of stack location. This mode of addressing is also known as implicit addressing.(b) Assume a hypothetical machine that has only PC, AC, MAR, IR, DR and Flag registers. (you may assume the roles of these registers same as that are defined in general for a von Neumann machine) The instruction of this machine can take only one direct operand. It has an instruction: INC X; // increments the operand stored at location X. The result of increment is left in AC. Show the steps for fetch and execute operations of the instructions using suitable micro- operations. Make and state suitable assumptions, if any. (5 Marks)Ans: Program counter or PC: The program counter, or PC (also called the instruction pointer to a seminal Intel instruction set, such as the 8080 or 4004, or instruction address register, or just part of the instruction sequencer in some computers) is a processor register that indicates where the computer is in its instruction sequence. Depending on the details of the particular computer, the PC holds either the address of the instruction being executed, or the address of the next instruction to be executed. In most processors, the program counter is incremented automatically after fetching a program instruction, so that instructions are normally retrieved sequentially from memory, with certain instructions, such as branches, jumps and subroutine calls and returns, interrupting the sequence by placing a new value in the program counter. Such jump instructions allow a new address to be chosen as the start of the next part of the flow of instructions from the memory. They allow new values to be loaded (written) into the program counter register. A subroutine call is achieved simply by reading the old contents of the program counter, before they are overwritten by a new value, and saving them somewhere in memory or in another register. A subroutine return is then achieved by writing the saved value back in to the program counter again. Accumulator (AC): In a computers central processing unit (CPU), an accumulator is a register in which intermediate arithmetic and logic results are stored. Without a register like an accumulator, it would be necessary to write the result of each calculation (addition, Page 15
  16. 16. multiplication, shift, etc.) to main memory, perhaps only to be read right back again foruse in the next operation. Access to main memory is slower than access to a register likethe accumulator because the technology used for the large main memory is slower (butcheaper) than that used for a register.The canonical example for accumulator use is summing a list of numbers. Theaccumulator is initially set to zero, then each number in turn is added to the value in theaccumulator. Only when all numbers have been added is the result held in theaccumulator written to main memory or to another, non-accumulator, CPU register.An accumulator machine, also called a 1-operand machine, or a CPU with accumulator-based architecture, is a kind of CPU in which—although it may have several registers—the CPU always stores the results of most calculations in one special register—typicallycalled "the" accumulator of that CPU. Historically almost all early computers wereaccumulator machines; and many microcontrollers still popular as of 2010 (such as the68HC12, the PIC micro, the 8051 and several others) are basically accumulatormachines.Modern CPUs are typically 2-operand or 3-operand machines—the additional operandsspecify which one of many general purpose registers (also called "general purposeaccumulators"[1]) are used as the source and destination for calculations. These CPUs arenot considered "accumulator machines".The characteristic which distinguishes one register as being the accumulator of acomputer architecture is that the accumulator (if the architecture were to have one) wouldbe used as an implicit operand for arithmetic instructions. For instance, a CPU might havean instruction like: ADD memaddressThis instruction would add the value read from the memory location at memaddress tothe value from the accumulator, placing the result in the accumulator. The accumulator isnot identified in the instruction by a register number; it is implicit in the instruction andno other register can be specified in the instruction. Some architectures use a particularregister as an accumulator in some instructions, but other instructions use registernumbers for explicit operand specification.MAR:The Memory Address Register (MAR) is a CPU register that either stores the memoryaddress from which data will be fetched to the CPU or the address to which data will besent and stored.In other words, MAR holds the memory location of data that needs to be accessed. Whenreading from memory, data addressed by MAR is fed into the MDR (memory dataregister) and then used by the CPU. When writing to memory, the CPU writes data fromMDR to the memory location whose address is stored in MAR. Page 16
  17. 17. The Memory Address Register is half of a minimal interface between a microprogramand computer storage. The other half is a memory data register.Far more complex memory interfaces exist, but this is the least that can work.IR (Instruction register):Instruction register is the part of a CPUs control unit that stores the instructioncurrently being executed or decoded. In simple processors each instruction to be executedis loaded into the instruction register which holds it while it is decoded, prepared andultimately executed, which can take several steps.More complicated processors use a pipeline of instruction registers where each stage ofthe pipeline does part of the decoding, preparation or execution and then passes it to thenext stage for its step. Modern processors can even do some of the steps of out of order asdecoding on several instructions is done in parallel.Decoding the opcode in the instruction register includes determining the instruction,determining where its operands are in memory, retrieving the operands from memory,allocating processor resources to execute the command (in superscalar processors), etcDR:Data registers are used to hold numeric values such as integer and floating-point values. In someolder and low end CPUs, a special data register, known as the accumulator, is used implicitly formany operations.Flag Registers:The FLAGS register is the status register in Intel x86 microprocessors that contains the currentstate of the processor. This register is 16-bits wide. Its successors, the EFLAGS and RFLAGSregisters are 32-bits and 64-bits wide, respectively. The wider registers retain compatibility withtheir smaller predecessorsSteps for instruction executionStep 1:The first step of instruction execution is to fetch the instruction that is to be executed. To do sowe require:• Address of the “instruction to be fetched”. Normally Program counter (PC) register stores this information.• Now this address is converted to physical machine address and put on address bus with the help of a buffer register sometimes called Memory Address Register (MAR).• This, coupled with a request from control unit for reading, fetches the instruction on the data bus, and transfers the instruction to Instruction Register (IR).• On completion of fetch PC is incremented to point to the next instruction. Page 17
  18. 18. In Step 2: • The IR is decoded; let us assume that Instruction Register contains an instruction. ADD Memory location B with general purpose register R1 and store result in R1, then control unit will first instruct to: • Get the data of memory location B to buffer register for data (DR) using buffer address register (MAR) by issuing Memory read operation. • This data may be stored in a general purpose register, if so needed let us say R2 • Now, ALU will perform addition of R1 & R2 under the command of control unit and the result will be put back in R1. The status of ALU operation for example result in zero/non zero, overflow/no overflow etc. is recorded in the status register. • Similarly, the other instructions are fetched and executed using ALU and register under the control of the Control UnitThe number and the nature of registers is a key factor that differentiates among computers. For example,Intel Pentium has about 32 registers. Some of these registers are special registers and others are general-purpose registers. Some of the basic registers in a machine are:• All von-Neumann machines have a program counter (PC) (or instruction counter IC), which is a register that contains the address of the next instruction to be executed.• Most computers use special registers to hold the instruction(s) currently being executed. They are called instruction register (IR).• There are a number of general-purpose registers. With these three kinds of registers, a computer would be able to execute programs.• Other types of registers: • Memory-address register (MAR) holds the address of next memory operation (load or store). • Memory-buffer register (MBR) holds the content of memory operation (load or store). • Processor status bits indicate the current status of the processor. Sometimes it is combined with the other processor status bits and is called the program status word (PSW).A few factors to consider when choosing the number of registers in a CPU are:• CPU can access registers faster then it can access main memory.• For addressing a register, depending on the number of addressable registers a few bit addresses is needed in an instruction. These address bits are definetly quite less in comparison to a memory address. For example, for addressing 256 registers you just need 8 bits, whereas, the common memory size of 1MB requires 20 address bits, a difference of 60%.• Compilers tend to use a small number of registers because large numbers of registers are very difficult to use effectively. A general good number of registers is 32 in a general machine.• Registers are more expensive than memory but far less in number.From a user’s point of view the register set can be classified under two basic categories. Programmer Visible Registers: These registers can be used by machine or assembly language programmers to minimize the references to main memory. Status Control and Registers: These registers cannot be used by the programmers but are used to control the CPU or the execution of a program. Page 18
  19. 19. (c) Assume that you have a machine as shown in section 3.2.2 of Block 3 having the micro-operations as given in Figure 10 on page 62 of Block 3. Consider that R1 and R2 both are 8 bit registers and contains 11110101 and 01011010 respectively. What will be the values of select inputs, carry-in input and result of operation if the following micro-operations are performed? (For each micro-operation you may assume the initial value of R1 and R2 as defined above) (2 Marks) 1) Subtract R1 from R2Ans: 2) Increment R1Ans: Page 19
  20. 20. 3) Shift Left R1Ans: 4) Add R1, R2 with an initial input carry bit as 1Ans: Page 20
  21. 21. (d) What are the different types of Control Units? Explain the hardwired control unit with the hep of a diagram. (Word limit is 150 words) (3 Marks)Ans: A variety of techniques have been used to organize a control unit. Most of them fall into two major categories: 1. Hardwired control organization 2. Micro programmed control organization. In the hardwired organization, the control unit is designed as a combinational circuit. That is, the control unit is implemented by gates, flip-flops, decoder and other digital circuits. Hardwired control units can be optimized for fast operations. The block diagram of control unit is shown in Figure . The major inputs to the circuit are instruction register, the clock, and the flags. The control unit uses the opcode of instruction stored in the IR register to perform different actions for different instructions. The control unit logic has a unique logic input for each opcode. This simplifies the control logic. This control line selection can be performed by a decoder. n n A decoder will have n binary inputs and 2 binary outputs. Each of these 2 different input patterns will activate a single unique output line. The clock portion of the control unit issues a repetitive sequence of pulses for the SS duration of micro-operation(s). These timing signals control the sequence of execution of instruction and determine what control signal needs to applied at what time for instruction execution. Page 21
  22. 22. (e) What is an instruction pipeline? What are the problems of an instruction pipeline? How can you optimise the instruction pipeline in RISC processors? (3 Marks) (Word limit 150 words) Ans: An instruction pipeline is a technique used in the design of computers and other digital electronic devices to increase their instruction throughput (the number of instructions that can be executed in a unit of time). The fundamental idea is to split the processing of a computer instruction into a series of independent steps, with storage at the end of each step. This allows the computers control circuitry to issue instructions at the processing rate of the slowest step, which is much faster than the time needed to perform all steps at once. The term pipeline refers to the fact that each step is carrying data at once (like water), and each step is connected to the next (like the links of a pipe.) The origin of pipelining is thought to be either the ILLIAC II project or the IBM Stretch project though a simple version was used earlier in the Z1 in 1939 and the Z3 in 1941 Disadvantages of Pipelining: 1. A non-pipelined processor executes only a single instruction at a time. This prevents branch delays (in effect, every branch is delayed) and problems with serial instructions being executed concurrently. Consequently the design is simpler and cheaper to manufacture. 2. The instruction latency in a non-pipelined processor is slightly lower than in a pipelined equivalent. This is because extra flip flops must be added to the data path of a pipelined processor. 3. A non-pipelined processor will have a stable instruction bandwidth. The performance of a pipelined processor is much harder to predict and may vary more widely between different programs.Optimization of Pipelining in RISC ProcessorsRISC machines can employ a very efficient pipeline scheme because of the simple and regular instructions. Like all other instruction pipelines RISC pipeline suffer from the problems of data dependencies and branching instructions. RISC optimizes this problem by using a technique called delayed branching.One of the common techniques used to avoid branch penalty is to pre-fetch the branch destination also. RISC follows a branch optimization technique called delayed jump as shown in the example given below: Page 22
  23. 23. (f) Why do you use large numbers of registers in RISC processors? Assume that a RISC machine has 64 registers out of which 8 are reserved for the Global variables. How will these registers be used for parameter passing for subroutine calls? Explain with the help of diagram ` (3 Marks)Ans: In general, the register storage is faster than the main memory and the cache. Also the register addressing uses much shorter addresses than the addresses for main memory and the cache. However, the numbers of registers in a machine are less as generally the same chip contains the ALU and control unit. Thus, a strategy is needed that will optimize the register use and, thus, allow the most frequently accessed operands to be kept in registers in order to minimize register- memory operations. Such optimisation can either be entrusted to an optimising complier, which requires techniques for program analysis; or we can follow some hardware related techniques. The hardware approach will require the use of more registers so that more variables can be held in registers for longer periods of time. This technique is used in RISC machines. On the face of it the use of a large set of registers should lead to fewer memory accesses, however in general about 32 registers were considered optimum. Since most operand references are to local variables of a function in C they are the obvious choice for storing in registers. Some registers can also be used for global variables. However, the problem here is that the program follows function call - return so the local variables are related to most recent local function, in addition this call - return expects saving the context of calling program and return address. This also requires parameter passing on call. On return, from Page 23
  24. 24. a call the variables of the calling program must be restored and the results must be passed back to the calling program. RISC register file provides a support for such call- returns with the help of register windows. Register files are broken into multiple small sets of registers and assigned to a different function. A function call automatically changes each of these sets. The use from one fixed size window of registers to another, rather than saving registers in memory as done in CISC. Windows for adjacent procedures are overlapped. This feature allows parameter passing without moving the variables at all. The following figure tries to explain this concept: Assumptions: Register file contains 64 registers. Let them be called by register number 0 – 64. The diagram shows the use of registers: when there is call to function A (fA) which calls function B (fB) and function B calls function C (fC). Registers Nos. Used for 0–7 Global variables required by fA, fB, and fC Function A Function B Function C 8-9 Unused 10 – 15 Used by parameters of fC that may be passed Temporary variables of (6 Registers) to next call function C 16 – 25 Used for local variable of fC Local variables of (10 Registers) function C 26 – 31 Used by parameters that were passed from Temporary variables of Parameters of function C (6 Registers) fB -> fC function B 32 – 41 Local variables of fB Local variables of (10 Registers) function B42 – 47 Parameters that were passed from fA to fB Temporary Parameters of function B(6 Registers) variables of function A 48 – 57 Local variable of fA Local variables of (10 Registers) function A 58 – 64 Parameter passed to fA Parameters of (6 Registers) function A Page 24
  25. 25. Question 4:(a) Write an 8086 assembly Language Program with proper comments to concatenate two strings that are available in the memory. The concatenated string is stored in memory location different from the two strings. You may assume that the end of a string character is ‘$’. Make suitable assumptions, if any. (8 Marks)Ans : DATA SEGMENT STR1 DB "ENTER FIRST STRING HERE ->$" STR2 DB "ENTER SECOND STRING HERE ->$" STR3 DB "CONCATED STRING :->$" STR11 DB "FIRST STRING : ->$" STR22 DB "SECOND STRING: ->$" INSTR1 DB 20 DUP("$") INSTR2 DB 20 DUP("$") N DB ? N1 DB ? NEWLINE DB 10,13,"$" DATA ENDS CODE SEGMENT ASSUME DS:DATA,CS:CODE START: MOV AX,DATA MOV DS,AX LEA SI,INSTR1 LEA DI,INSTR2 ;GET STRING MOV AH,09H LEA DX,STR1 INT 21H MOV AH,0AH MOV DX,SI INT 21H MOV AH,09H LEA DX,NEWLINE INT 21H MOV AH,09H LEA DX,STR2 Page 25
  28. 28. CODE ENDS END START(b) Write a program in 8086 assembly language to convert a two digit number, which is stored in the memory as ASCII digits in two consecutive bytes, into an equivalent packed BCD number. The BCD number should be left in the AL register. For example, if the two memory locations contain characters ‘4’ and ‘5’ respectively, the program will output 0100 0101 in the AL register. (6 Marks)Ans : name "convert" ; this program uses a subroutine written in 8086 assembly language ; that can be used for converting a string of number ; (max of 4 ascii digit) to equivalent packed bcd digits. ; bcd is binary coded decimal. ; this program does no screen output. ; to see results click "vars". org 100h jmp start string db 1234 ; 4 ascii digits. packed_bcd dw ? ; two bytes (word) to store 4 digits. start: lea bx, string lea di, packed_bcd call pack_to_bcd_and_binary ret ; return to operating system. ; subroutine written in 8086 assembly language ; that can be used for converting a string of number ; (max of 4 ascii digit) to equivalent packed ; bcd digits. ; input parameters: ; bx - address of source string (4 ascii digits). ; output: ; di - must be set to address for packed bcd (2 bytes). Page 28
  29. 29. pack_to_bcd_and_binary proc nearpusha; point to 2 upper digits of packed bcd:; (assumed that we have 4 digits)add di, 1; loop only for 2 because every time we; read 2 digits (2 x 2 = 4 digits)mov cx, 2; reset packed bcd:mov word ptr [di], 0 ; to convert a char (0..9) to digit we need ; to subtract 48 (30h) from its ascii code, ; or just clear the upper nibble of a byte. ; mask: 00001111b (0fh)next_digit:mov ax, [bx] ; read 2 digits.and ah, 00001111band al, 00001111b; 8086 and all other Intels microprocessors store less; significant byte at lower address.xchg al, ah; move first digit to upper nibble:shl ah, 4; pack bcd:or ah, al; store 2 digits:mov [di], ah; next packed bcd:sub di, 1; next word (2 digits):add bx, 2loop next_digitpoparetpack_to_bcd_and_binary endp Page 29
  30. 30. (c) Write a simple subroutine that accepts a parameter value. The subroutine checks if the passed parameter value is Zero (0). If the value is ZERO the subroutines output a string “Divide Overflow” and terminates the execution, other wise it allows the calling program to continue. (6 Marks)Ans:/* ******************************************************************************A simple subroutine thet accepts a parameter value and checks if the passed parameter value is Zero(0). If the value is ZERO the subroutine outputs a string "Divide Overflow" and terminates the execution, otherwise it allows the calling program to continue********************************************************************************/#include<stdio.h>#include<stdlib.h>int chk_input(int in){ if(in==0){ printf("Divide Overflown"); exit(1); /* terminate Program*/}else{return(0); /* continue execution*/}}void main(){int i=89,in,flg;printf("A Program to divide 89 by any number suppliednPlease enter divisor:");scanf("%d",&in);flg=chk_input(in);if(flg==0){ printf("%d divided by %d =%fn",i,in,float(i/in));}}/* End of Program */ -------------- Page 30