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System partitioning in VLSI and its considerations
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System partitioning in VLSI and its considerations

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  • Partitioning can be done in the RTL design phase when the design engineer partitions the entire design into sub-blocks and then proceeds to design each module. These modules are linked together in the main module called the TOP LEVEL module. This kind of partitioning is commonly referred to as Logical Partitioning.Efficient designing of any complex system necessitates decomposition of the same into a set of smaller subsystems. Subsequently, each subsystem can bedesigned independently and simultaneously to speed up the design process. The process of decomposition is called partitioning .Three broad parameters to be taken into consideration:1. The system must be decomposed carefully so that the original functionality of the system remains intact. 2. An interface specification is generated during the decomposition, which is used to connect all the subsystems. The system decomposition should ensure minimization of the interface interconnections between any two subsystems.3. Finally, the decomposition process should be simple and efficient so that the time required for the decomposition is a small fraction of the total design time.
  • The greatest challenge in modern VLSI design is not in designing the individual transistors but rather in managing system complexity. Modern System-On-Chip (SOC) designs combine memories, processors, high speed I/O interfaces, and dedicated application-specific logic on a single chip. They use hundreds of millions (soon billions) of transistors. The implementation must be divided among large teams of engineers. If the implementation is too rigidly partitioned, each block can be optimized without regard to its neighbors, leading to poor system results.Conversely, if every task is interdependent with every other task, design will progress too slowly. Design managers face the challenge of choosing a suitable tradeoff between these extremes.
  • The partitioning of a system into a group of PCBs is called the system level partitioning. The partitioning of a PCB into chips is called the board levelpartitioning while the partitioning of a chip into smaller sub circuits is called the chip level partitioning.
  • 1.Interconnections between partitions: The number of interconnections at any level of partitioning have to be minimized. Reducing the interconnections not only reduces the delay but also reduces the interface between the partitions making it easier for independent design and fabrication.A large number of interconnections increase the design area as well as complicate the task of the placement and routing algorithms. Minimizationof the number of interconnections between partitions is called the mincut problem. The minimization of the cut is a very important objective function for partitioning algorithms for any level or any style of design.2. Delay due to partitioning: The partitioning of a circuit might cause a critical path to go in between partitions a number of times. As the delay between partitions is significantly larger than the delay within a partition, this is an important factor which has to be considered while partitioning high performance circuits. This is an objective function for partitioning algorithms for all levels of design.3. # of terminals: Partitioning algorithms at any level must partition the circuit so that the number of nets required to connect a subcircuit to other subcircuits does not exceed the terminal count of the subcircuit. In case of system level partitioning, this limit is decided by the maximum number of terminals available on a PCB connector which connects the PCB to the system bus. In case of board level partitioning, this limit is decided by the pin count of the package used for the chips. In case of chip level partitioning, the number of terminals of a subcircuit is determined by the perimeter of the area used by the subcircuit. At any level, the number of terminals for a partition is a constraint for the partitioning algorithm 4. Number of partitions: The number of partitions appears as a constraint in the partitioning problem at system level and board level partitioning.This prevents a system from having too many PCBs and a PCB from having too many chips. A large number of partitions may ease the design of individual partitions but they may also increase the cost of fabrication and the number of interconnections between the partitions. At the same time, if the number of partitions is small, the design of these partitions might still be too complex to be handled efficiently. At chip level, the number of partitions is determined, in part, by the capability of the placement algorithm. 5. Area of each partition: In case of system level partitioning, the area of each partition (board) is fixed and hence this factor appears as a constraint for the system level partitioning problem. In case of board level partitioning, although it is important to reduce the area of each partition (chip) to a minimum to reduce the cost of fabrication, there is also an upper bound on the area of a chip, Hence, in this case also, the area appears as a constraint for the partitioning problem. At chip level, the size of each partition is not so important as long as the partitions are balanced.
  • -input_filesfilesSpecifies that a partition is to be created by using one or more Verilog files. The structure of the Verilog files does not matter. Each module mustbe defined only once. All unused modules will remain as independent top modules.-reset overrides | partition | keepouts | allResets some or all of the computed parameters in the partition. Possible choices are overrides, which resets any areas or utilization settings thatwere overridden; partition, which resets any partitioning choices that were made manually or through autopartitioning; keepouts, which resets anykeepouts that were set; or all, which does all of these things.-auto_partition instance_count | areaChooses autopartitioning as part of the partitioning for this object. You can choose instance_count, which balances partitions based on equalizing thenumber of instances in each partition, or you choose area, which balances partitions based on the size of the area.-physicalIndicates that the blocks in the module_name_list will be labelled as physical (and logical) blocks, labelling them as partitions. Note that thetop block in a design is by definition physical and logical. This option is mutually exclusive with the -logical option.-logicalIndicates that the blocks in the module_name_list will be labelled as logical-only blocks, labelling them as internal (logical) hierarchy. Notethat the top block in a design is by definition physical and logical. This option is mutually exclusive with the -physical option.-area sub_block_areaAllows you to set or to override the area for a given block within the hierarchy. This option should be used in a top-down design flow when one ormore (presumably large) blocks are missing, but their estimated area is known. This can result in more properly considering the missing blocksexpected contribution during area-based autopartitioning and during topdown, black-box shaping and floorplanning. There is no restriction on whetheror not the overridden block is a physical block. In some circumstances a block might already have a well-defined area but the designers are aware that a change is coming that will result in a different area. A designer can get a head start on refloorplanning the design by overriding the area on the current version of the block. Note that in this case, using this option will fail with an error message unless it is used with the -force-fP option.-internal_keepoutkeepoutSets an internal keepout on the given blocks. This keepout will be added to the area of the block. If that block is partitioned into a physical block,it will become larger by the internal keepout. The default internal keepout is 0.-external_keepoutkeepoutSets an external keepout on the given blocks. This keepout will be added to the the area of the block but it will not cause the partitioned physical blockto become larger. Note, however, that adding to the area of the block will cause the parents of this block to be larger. The default external keepout is 0.-utilization block_utilizationAllows you to specify the utilization on modules. There are two ways to do this. First, if used with the -input_files option, it will set a defaultutilization on all modules. Second, if used with a module_name_list, it will override the default utilization on the specified modules. The setutilization is used along with the leaf cell areas to compute the required area for the physical blocks. Note that in some cases you might need to usethe -force option to have this work.-aspect_ratiofloatAllows you to specify a target aspect ratio (height/width) for the chip to be created using the -create top_level_floorplan option. The default aspectratio is 1.

System partitioning in VLSI and its considerations System partitioning in VLSI and its considerations Presentation Transcript

  • System partitioning & its considerations Subash John CGB0911005 VSD 531 M.Sc. [Engg.] in VLSI System Design Module Title: IC planning & implementation Module Leader: Mr. Chandramohan P. M. S. Ramaiah School of Advanced Studies 1
  • Contents• Introduction• Physical design flow• Need for partitioning• Rules of partitioning• Methods of partitioning• Tool based partitioning• Conclusion• References M. S. Ramaiah School of Advanced Studies 2
  • Introduction• Decomposition of a complex system into smaller subsystems• Each subsystem can be designed independently speeding up the design process• Decomposition scheme has to minimize the interconnections between the subsystems• Decomposition is carried out hierarchically until each subsystem is of manageable size• This is done mainly to separate different functional blocks and also to make placement and routing easier Figure 1. Bad partitioning results in more delay [2] M. S. Ramaiah School of Advanced Studies 3
  • Components of partitioning• Inputs – A set of components or modules – A netlist: In the form of weighted graph or hyper graph: nodes representing modules; edge or hyper edge representing a net• Outputs – A set of sub circuits that when connected, function as the original circuit – Terminals required for each sub circuit to be connected to other sub circuits Figure 2. (a) Network (b) Graph [2] M. S. Ramaiah School of Advanced Studies 4
  • Physical design flow Partitioning Floor Planning Power planning Placement CTS RoutingFigure 3. Physical flow [2] M. S. Ramaiah School of Advanced Studies 5
  • Need for partitioning• Dividing a net list into clusters to minimize # of inter-cluster connections• Becomes more critical with VDSM• Influences the final quality of placement, global routing & detail routing• System size increases – Need to minimize design coupling• Interconnect dominates chip performance – Have to minimize number of block-to-block connections (e.g. global buses)• Helps reduce chip area – Minimizes length of global wires M. S. Ramaiah School of Advanced Studies 6
  • Partitioning at different levels PartitioningSystem Board level Chip level level Figure 4. Levels of partitioning [3] M. S. Ramaiah School of Advanced Studies 7
  • 5 Golden rules of partitioning• Interconnections between partitions – Reducing interconnections reduces the delay & interface between the partitions making it easier for independent design and fabrication• Delay due to partitioning – Partitioning of a circuit might cause a critical path to go in between partitions a number of times• Number of terminals – Number of nets required to connect a sub circuit to other sub circuits does not exceed the terminal count of the sub circuit.• Number of partitions – Large number of partitions may ease the design of individual partitions but they may also increase the cost of fabrication and the number of interconnections between the partitions• Area of each partition M. S. Ramaiah School of Advanced Studies 8
  • Methods of partitioning• Constructive or iterative – Constructive algorithms determine a partitioning from the graph describing the circuit or system, whereas iterative methods aim at improving the quality of an existing partitioning solution• Deterministic or probabilistic – Deterministic programs generate the same solution each time they are started. Probabilistic methods result in differing solutions because they are based on random numbers M. S. Ramaiah School of Advanced Studies 9
  • Partitioning example I Input size: 48Cut 1=4 Cut 2=4Size 1=15 Size 2=16 Size 3=17 Figure 5. Partitioning example [2] M. S. Ramaiah School of Advanced Studies 10
  • Partitioning example II A constructed partition using logic A partitioning cell C as a seed. It iswith five external difficult toconnections (nets get from this local minimum, with 2, 4, 5, 6, and seven external8)—the minimum connections (2, 3, 5, number. 7, 9,11,12), Figure 6. Partitioning example [2] M. S. Ramaiah School of Advanced Studies 11
  • Partitioning example III 776 65 4 Figure 7. Partitioning example [2] M. S. Ramaiah School of Advanced Studies 12
  • Tool based partitioning• create_partition - Creates and manipulates partitions in a design through command-line specification, auto partitioning or manual GUI-based changes create_partition [-input_files files] [-reset overrides | partition | keepouts | all] [-auto_partition instance_count | area] [-area sub_block_area] [-internal_keepout keepout] [-external_keepout keepout] [-utilization block_utilization] [-aspect_ratio float] [-output_dir dir_name] [-create verilog_files | design | top_level_floorplan] [-verbose] [module_name_list] create_partition -input_files {myDesign.v} -utilization 0.85 –reset all –aspect_ratio .7 -auto_partition instance_count M. S. Ramaiah School of Advanced Studies 13
  • Tool based partitioning• optimize_netlist_hierarchy - Modifies the net-list tree structure in order to create physically partition-able hierarchy nodes in the top level such that the size of the nodes are well-balanced while minimizing the number of top level nets that need to connect to hierarchy block interface. optimize_netlist_hierarcy -netlist_files filelist -top topName [-opaque_modules modulelist] [-filename filename] [-max_partition_to_chip_ratio sizeRatio] [-keep_top_hier modulelist] [-hier_marker symbol] [-max_hier_mod_depth level] [-max_num_nodes count] optimize_netlist_hierarchy -netlist_files input.v -top MYTOP - max_partition_to_chip_ratio 0.3 -keep_top_hier {PDB08DGZ PDIANA2PC PDIDGZ} - max_num_nodes 500 -hier_marker / -output nlout M. S. Ramaiah School of Advanced Studies 14
  • Benefits of tool based partitioning• Identifies an optimal partitioning scheme for a given design, such that the blocks can be implemented independently• Ensures that the size of the partitions are balanced by either area or instance count• Minimizes the number of top-level nets connecting to one of more block I/O ports• Partitions the netlist without changing the functionality. M. S. Ramaiah School of Advanced Studies 15
  • Summary• Partitioning divides a large circuit into a group of smaller sub circuits• These sub circuits can be designed independently and simultaneously to speed up the design process• In the tool based flow, constraints can be given to generate an efficient partitioned netlist M. S. Ramaiah School of Advanced Studies 16
  • References1. Arnab Sarkar (2008), ‘VLSI Physical Design Automation’ available from <http://conf05.iitkgp.ac.in/avlsi/logf/summercourse/2008/Physical_Design_A rnab.pdf> Retrieved on 01st Apr 20122. Michael John & Sebastian Smith (1997), ‘Application Specific Integrated Circuit’. Massachusetts: Addison-Wesley Publishing Company3. Naveed Sherwani (1999) ‘Algorithms for Physical Design Automation’. Dordrecht: Kluwer Academic Publishers4. Newton, Keutzer & Orshansky (2000) Partitioning of Physical Design, University of California, Berkeley, CA5. Synopsys Inc. (2009), ‘IC Compiler Design Planning User Guide’. M. S. Ramaiah School of Advanced Studies 17
  • Thank YouM. S. Ramaiah School of Advanced Studies 18
  • RemarksSl. No. Topic Max. marks Marks obtained 1 Quality of slides 5 2 Clarity of subject 5 3 Presentation 5 4 Effort and question handling 5 Total 20 M. S. Ramaiah School of Advanced Studies 19