DDR2 SDRAM Controller By Pramod K Roshan M Titus Subash John Varun S
DDR1 vs. DDR2
Power up & initialization
Power down mode
DDR SDRAM Technology
Transfers data twice per cycle on both edges of the clock signal – Double pumping
“ Double Data Rate" refers to the fact that a DDR SDRAM with a certain clock frequency achieves nearly twice the bandwidth of a single data rate (SDR) SDRAM running at the same clock frequency.
DDR1 vs. DDR2 Power consumption 2.5V 1.5V Reduces memory system power demand Data rate (MT/s per pin) 333 400 667 800 533 667 800 1066 Migration to higher data bandwidth Chip densities Up to 1Gb Up to 4Gb High-density components enable large memory subsystems with fewer chip counts Prefetch buffers 2 4 Enables faster clock rates Internal banks 4 4 and 8 1Gb and higher density DDR2 devices have 8 banks for better performance
Clock (Input): CK and CK’ are differential clock inputs. All address and control input signals are sampled on the crossing of the positive edge of CK and negative edge of CK’.
Chip Select(CS)Input: All commands are masked when CS’ is registered HIGH.
Clock Enable(CKE ) Input:
CKE must be maintained HIGH throughout read and write accesses.
Taking CKE LOW provides Precharge Power-Down and Self Refresh operation (all banks idle), or Active Power-Down (row Active in any bank). CKE is synchronous for power down entry and exit, and for self refresh entry. CKE is asynchronous for self refresh exit.
RAS’, CAS’, WE ‘(Command inputs): RAS, CAS and WE (along with CS’) define the command being entered.
DM(Data Mask)Input: DM is an input mask signal for write data. Input data is masked when DM is sampled HIGH coincident with that input data during a Write access. DM is sampled on both edges of DQS.
BA0 - BA2 ( Bank Address )Input: Define to which bank an Active, Read, Write or Precharge command is being applied (For 256Mb and 512Mb, BA2 is not applied). Bank address also determines if the mode register or one of the extended mode registers is to be accessed during a MRS or EMRS command cycle.
Provide the row address for Active commands and the column address and Auto Precharge bit for Read/Write commands to select one location out of the memory array in the respective bank.
A10 is sampled during a Precharge command to determine whether the Precharge applies to one bank (A10 LOW) or all banks (A10 HIGH). If only one bank is to be precharged, the bank is selected
DQ ( Data)I/O: Bi-directional data bus.
Data Strobe (I/O): Output with read data, input with write data for source synchronous operation
Accesses begin with the registration of an Active command, which is then followed by a Read or Write command.
The address bits registered coincident with the active command are used to select the bank and row to be accessed (BA0-BA2 select the bank; A0-A13 select the row).
The address bits registered coincident with the Read or Write command are used to select the starting column location for the burst access and to determine if the auto precharge command is to be issued.
Read and write accesses are burst oriented; accesses start at a selected location and continue for a burst length of 4 or 8 in a programmed sequence
Power up & Initialization
Prior to normal operation, the DDR2 SDRAM must be initialized in a predefined manner.
Operational procedures other than those specified may result in undefined operation.
For DDR2 SDRAMs, both bits BA0 and BA1 must be decoded for Mode/Extended Mode Register Set (MRS/EMRS) commands.
All four Mode Registers must be initialized prior to operation. The registers may be initialized in any order.
For the capacitors to retain their value, all rows in all banks must be refreshed at least once every 64ms
All banks must be in the idle mode prior to issuing a REFRESH command
The addressing is generated by the internal refresh controller
This makes the address bits a “Don’t Care” during a REFRESH command.
If PD occurs when all banks are idle -> Precharge PD
If PD occurs when at least one row is active -> Active PD
Entering power-down deactivates the input and output buffers, excluding CK, CK#, ODT, and CKE.
PD modes do not perform any REFRESH operations. Thus the duration of PD mode is limited by the refresh requirements.
Fig. Power down mode
Table 1. Truth Table - DDR2 commands
Programming the mode registers
For application flexibility, burst length, burst type, CAS latency, DLL reset function, write recovery time (WR) are user defined variables and must be programmed with a Mode Register Set (MRS) command.
Additionally, DLL disable function, driver impedance, additive CAS latency, ODT (On Die Termination), single-ended strobe, and OCD (off chip driver impedance adjustment) are also user defined variables and must be programmed with an Extended Mode Register Set (EMRS) command.
Contents of the MR/EMR can be altered by re-executing the MRS or EMRS Commands. Even if the user chooses to modify only a subset of the MR or EMR(#) variables, all variables within the addressed register must be redefined when the MRS or EMRS commands are issued.