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ATE Testers Overview
 

ATE Testers Overview

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Overview of testers usage for debug

Overview of testers usage for debug

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  • nice info.. it reminds me at work way back 2009, during my days in Intel Philippines as a Sr. Test Technicians, I really miss the troubleshooting in S9k tester IX and GX as well in Advantest CMT T2000.
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    ATE Testers Overview ATE Testers Overview Presentation Transcript

    • ATE Testers Overview Jun-2005
    • Testers Overview
      • CWMA Component Debug Testers
      • Comparison of VNG and S9K Testers
      • Testers Channel Connection Style
      • Functional Test Content and Tools
        • Levels
        • Timing
        • Patterns
    • CWMA CD Testers
      • CD is using three tester types
        • S9K EXA/KX testers (3 x EXA + 2 x KX)
          • Speed up to 800MT/S (200MHz FSB)
          • Running on Solaris 2.5.1 - SunOS 5.5.1
          • EXA05 - EXA09, KX09 - KX10
        • S9K EXC testers (x 1.5)
          • Speed up to1600 MT/S (400MHz FSB)
          • Running on Solaris 2.5.1 - SunOS 5.5.1
          • EXA03, EXA04
        • IMS Vanguard I testers (x 7)
          • Speed up to 1100MT/s (266MHz FSB)
          • Running on Linux 2.4
          • ilvng02 - ilvng08
      Testers Comparison
    • S9K EXA/KX vs. IMS VNG
      • Production oriented Tester
      • Debug oriented Tester
      • Slower tester (internally) with single path flow
      • Faster tester (internally) with Flow control & Binning
      • No compilation is required on Test Program changes
      • Test Program changes require compilation
      • Interactive and easy to use. Equipped with friendly GUI
      • Complicated to use - needs Gift-VT as user interface
      • Run single pattern (1-2M)
      • Run multiple patterns (64M)
      • Air Cooled system
      • Liquid Cooled system
      • Capable up to 800MT/s
      • Capable up to 1100MT/s
      • Small Footprint & Mobile
      • Big Footprint and special infrastructure requirements
    • Test Types
      • DC Test
        • Static
        • Dynamic
      • AC Test/Functional Test
        • Functional Pass/Fail
        • Parameters Searches
    • AC/Functional Test
      • Testing Terms & Definitions
      • Tester Channel connections style
      • S9K PEC Diagram
      • Functional Test Content
    • Testing Terms & Definitions
      • DUT - D evice U nder T est
      • TIU - T ester I nterface U nit
      • PEC - P in E lectronic C ard
      • Tester Channel
        • Hardware interface to connect DUT active pin to the tester
          • Each DUT active pin is connected to a unique tester channel
        • Channel types
          • Input
          • Output
          • I/O
        • Channel connection types
          • Single wired
          • Fly by / DTL - D ual T ransmission L ine
    • TIU - Tester Interface Unit Device Under Test TIU
    • Tester Channel - S9K style 01011 00011
    • Tester Channel - IMS style VTERM
    • PEC 5 Block Diagram (S9K KX)
    • Functional Test Content Pattern Timing Levels Func. Test
    • Levels Content
      • Power Supplies Definitions:
        • Voltage Range and Level
        • Current Range, Set and Limit
        • Power on/off Sequence
        • Settling Delay
      • Pin Levels Definitions:
        • VIL, VIH
        • VOL, VOH
        • IOL, IOH
        • VTerm
        • Vref (Switching ILOADs)
        • VCL, VCH
      • Calibration Values
        • VIL, VIH
        • DUT Capacitance
      I/O PIN
    • Levels Control
      • Controlling Level parameters is done by
        • IMS - DC Setup
        • S9K - LevelTool
    • Timing Content
      • Global Tester Timing
        • Tester Period - Driven from the Tester master oscillator
        • Cycle Time - The smallest tester transaction activity
        • Define Tester Drive/Compare data rate
      • Pin Timing (waveform)
        • Driving Edge(s) position
          • Drive constant values: D0, D1
          • Drive patterns data: DF, DF_, DF2, DF2_
        • Strobe Type and position
          • Window, Edge
          • Strobe constant Values: T0, T1
          • Strobe patterns data: TF, TF_, TF2, TF2_, TZ, X
        • Pre initialize Values
          • PF, PZ, P1, P0, PX
    • Timing Control
      • Controlling Timing parameters is done by
        • IMS - AC Setup
        • S9K - TimingTool
    • Pattern Content
      • Pattern is an ordered succession of Vector s
      • Vector contains the DUT I/O status per a single cycle.
        • Device input data - (Tester drive)
        • Device output data - (Tester compare)
        • Pointer to the relevant timing waveform
        • Vector may contain special instructions for the tester
      • Pattern is used by tester if configured by the Timing
      Waveform1 11110000 10000 10 1 0 0 1 Waveform2 11110000 10000 10 1 0 0 1 Repeat 499 Waveform3 LLLLHHLLL HHLLL LL x x L L
    • Pattern Instructions
      • Pattern instructions control the tester behavior
      • Flow Control Instructions
        • Continue to next vector
        • Call subroutine
        • Unconditional Jump
        • Conditional Jump
        • Repeat n times
        • Loop n times
        • Generate Triggers
      • Acquisition Control Instructions
        • Start/Stop acquire data
    • Pattern Control
      • Controlling Pattern content is done by
        • IMS - Pattern Tool
        • S9K - VectorTool
    • Waveform
      • Define relations between Pattern data & timing
      Tester Cycle Duration (10ns) Waveform2 11110000 10000 10 1 0 0 1 Pattern Data: 1 Drive State (DF) @ 2ns 2ns Waveform: Pattern Data: 0 Drive State (DF) @ 5ns 5ns Waveform: 5ns Pattern Data: 0 Drive One (D1) @ 5ns Waveform: Pattern Data: 1 Compare (TF) @ 5ns Waveform: 5ns
    • Tester Cycle
      • The smallest Tester Transaction activity
      • The Transaction activity is a combination of Timing Definitions, Pattern data and Levels Definitions
      • A single tester cycle has one or more delays for every DUT signal
      • The delays specify where data changes on input pins, and where data is sampled on output pins
      Tester Cycle Duration Input Group Input Group Output Group Sample Point Tester Cycle Duration Input Group Input Group Output Group Data 1 Data 1 Sample Point Tester Cycle Duration Input Group Input Group Output Group Data 0 Data 0 Sample Point Tester Cycle Duration Input Group Input Group Output Group Delay 1 Delay 2
    • Test
      • A Test is an ordered succession of individual tester cycles.
      • The end of one tester cycle is the beginning of the next.
      • Tester Data is a combination of timing definitions and pattern data
      Cycle Start Tester Cycle N Input Group Input Group Output Group Sample Point Tester Cycle N+1 Tester Cycle N+2 Data 1 Data 0 Data Z
    • Tester Memory Local Memory Capture Memory
      • Size of 1MB to 64MB
      • Single Pattern to Patterns Lists
      • Size of 128KB to 2MB
      • Capture Errors or Acquire data
      Subroutine Memory
      • RMA - R elative M emory A ddress
      • TC - T est C ount
    • Backups
    • Increasing Tester Data Rate
      • Increase Tester I/O data rate can be achieved by Hardware, Software or both solutions:
      • Software Solution (Memory Penalty)
        • AVM mode on KX
      • Hardware Solution (Channels Penalty)
        • Multiplexing Two channels
        • 2X Mode on IMS is used to double the data rate for the FBS channels.
    • Increasing Tester Data Rate
      • Increase Tester I/O data rate can be achieved by Hardware, Software or both solutions:
      • Hardware Solution (Channels Penalty)
        • Multiplexing Channels. Use to double Data Rate for FSB channels.
          • 2X Mode on IMS
          • Mux Mode on S9K GX
        • Special Add on cards - H igh S peed C lock C ard (8x)
      • Software Solution (Memory Penalty)
        • AVM mode on KX - A ccelerate V ector M ode
      • Hardware & Software Solution
        • FlexMux + AVM Modes on EXA 3000 (4x)
    • Vanguard I General Description
      • Base Clock oscillator 2ns-4ns
      • Maximum clock freq. FC550 500MHz
      • Maximum data rate DM550 550Mbits/s (1x)
      • Maximum data rate DM1100 1100Mbits/s (2x)
      • 1M pattern memory depth (2M in 2x mode)
      • Max 512 x DM500 Channels + 8 high speed clock o/p
      • Period resolution 5ps
      • Drivers rise/fall time 450ps
      • Edge Placement Accuracy +/-50ps
      • Edge Placement resolution 10ps
      • Driver Voltage range -2.5Vto +4V
      • Voltage setting resolution 2.5mV
    • Testers Comparison Yes Yes Yes Yes Yes Yes N/A N/A Pattern Chain/Loop Yes Yes Yes Yes Yes Yes N/A N/A Keep Alive N/A N/A Yes Yes Yes Yes N/A N/A Split Timing Mode +/-100ps +/-50ps +/-50ps +/-50ps +/-75ps +/-100ps +/-125ps +/-175ps Edge Placement Acc. 7.8125pS 10pS 9.765pS 9.765pS 9.765pS 9.765pS 39.062pS Period Resolution 5ns 0ns 5ns 0ns 2ns 2.2ns 5ns 5ns Round Trip @ Pogo 128MB 2MB 64MB 64MB 64MB 64MB 32MB 32MB Local Memory DM250 DM1100 PEC76 PEC5.1 PEC5 PEC5 PEC4 PEC3 PEC Type 24K 2MB 124Kx2 124Kx2 124Kx2 124Kx2 16Kx2 16K Capture Memory 4K N/A 4K 4K 4K 4K 4K 4K Subroutine Memory Vector Memory 4ns 2ns 5ns 5ns 5ns 5ns 9.6ns 9.6ns Event Timing Res. Timing Details - - 1600MT/s - - - - - F8 - MUX AVM F2 - - - 1000MT/s - - 400MT/s - HW MUX - - 800MT/s 800MT/s 800MT/s - - - F4 - AVM F2 500MT/s 1100MT/s 400MT/s 400MT/s 400MT/s 400MT/s 208MT/s 208MT/s F2 250MT/s 550MT/s 200MT/s 200MT/s 200MT/s 200MT/s 104MT/s 104MT/s F1 Data Rate CMT IMS EXA KX-RAC KX IX GX FX System