ATE Pattern Structure Basics

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ATE Pattern Structure Basics

  1. 1. Pattern Structure & Basics
  2. 2. Topics: <ul><li>What is a pattern? </li></ul><ul><ul><li>01000101010101010…and more. </li></ul></ul><ul><li>What comprises a pattern? </li></ul><ul><ul><li>Data, Pindef, Vecdef, etc. </li></ul></ul><ul><li>How does it all work? </li></ul><ul><ul><li>Pattern Components + Test Program => Tester Does Stuff </li></ul></ul><ul><li>Pattern Example/Overview </li></ul>
  3. 3. What is a pattern? <ul><li>A pattern is… </li></ul><ul><ul><li>A collection of data that precisely describes the activity of each tester pin at bus clock resolution. </li></ul></ul><ul><ul><ul><li>The activity is executed by the tester via the test program. </li></ul></ul></ul><ul><ul><li>Generated by converting a trace, the output of a test simulated on an RTL model, that contains data at core clock resolution. </li></ul></ul><ul><ul><li>Created specifically for each tester, taking into account the requirements and capabilities of different types of testers (S9K, CMT, ST2, IMS). </li></ul></ul>
  4. 4. Pattern Components <ul><li>Pindef – defines the connection between pattern data and tester channels. </li></ul><ul><ul><ul><li>#avm ENABLE </li></ul></ul></ul><ul><ul><ul><li>pindef ynh_fsbf2 { </li></ul></ul></ul><ul><ul><ul><li><12:12:1999 12:12:12>, </li></ul></ul></ul><ul><ul><ul><li>TWO_BIT_BURST = TRUE, </li></ul></ul></ul><ul><ul><ul><li>PACKAGE YNH_M_K_Cviu { </li></ul></ul></ul><ul><ul><ul><li>BCLK1t0_1_x1 = IO ,F2 ,ADJACENT ,BIN ,{54},{&quot;A21&quot;}, </li></ul></ul></ul><ul><ul><ul><li>BCLK1t0_0_x1 = IO ,F2 ,ADJACENT ,BIN ,{55},{&quot;A22&quot;}, </li></ul></ul></ul><ul><ul><ul><li>RESETnn_x1 = IO ,F2 ,ADJACENT ,BIN ,{57},{&quot;B1&quot;}, </li></ul></ul></ul><ul><ul><ul><li>INITnn = IO ,F2 ,ADJACENT ,BIN ,{170},{&quot;B3&quot;}, </li></ul></ul></ul><ul><ul><ul><li>VCC_x1 = PWR ,{HCDPS2},{&quot;AA21&quot;}, </li></ul></ul></ul><ul><ul><ul><li>VSS = PWR ,{GND},{&quot;AA25&quot;}, </li></ul></ul></ul><ul><ul><ul><li>}, </li></ul></ul></ul><ul><ul><ul><li>PINGROUP { </li></ul></ul></ul><ul><ul><ul><li>input = {A20Mnn,BPRInn,DEFERnn,DPSLPnn,DPWRnn,IGNNEnn,INITnn,LINT0,LINT1, </li></ul></ul></ul><ul><ul><ul><li> PREQnn,PWRGOOD_x1,RESETnn_x1,rsnn,SLPnn,SMInn,STPCLKnn,TCK_x1,TDI_x1, </li></ul></ul></ul><ul><ul><ul><li> TMS_x1,TRDYnn,TRSTnn,BCLK1t0_1_x1,BCLK1t0_0_x1}, </li></ul></ul></ul><ul><ul><ul><li>} </li></ul></ul></ul><ul><ul><ul><li>}; </li></ul></ul></ul>
  5. 5. Pattern Components <ul><li>Vecdef – defines the sequences associated with each pin for a specific vector. </li></ul><ul><ul><li>VECTOR_DEF E_00000 = </li></ul></ul><ul><ul><li>{ </li></ul></ul><ul><ul><li>PERIOD = Period_1, </li></ul></ul><ul><ul><li>BCLK1t0_1_x1 = d_d 0/1 @, </li></ul></ul><ul><ul><li>BCLK1t0_0_x1 = d_d 0/1 @, </li></ul></ul><ul><ul><li>RESETnn_x1 = nop_nop 0/1 @, </li></ul></ul><ul><ul><li>INITnn = d_d 0/1 @, </li></ul></ul><ul><ul><li>AACLKPH_x1 = s_s 0/1 @, </li></ul></ul><ul><ul><li>DCLKPH_x1 = s_s 0/1 @, </li></ul></ul><ul><ul><li>; pin names in pindef order seq sym </li></ul></ul><ul><ul><li>; seq = timing sequence name, must be predefined in the timing </li></ul></ul><ul><ul><li>; sym = vector data symbols for '0' and '1' </li></ul></ul><ul><ul><li>} </li></ul></ul>
  6. 6. Pattern Components <ul><li>Vector – contains the tester data for each specific tester period. </li></ul><ul><li>; opcode (operand) Vec_Def pattern data csim_ts ; tstr_cyc ; tstr_rma ; info </li></ul><ul><li>MAIN_F; </li></ul><ul><li>; B B </li></ul><ul><li>; C C </li></ul><ul><li>; L L R A </li></ul><ul><li>; K K E A D </li></ul><ul><li>; 1 1 S C C </li></ul><ul><li>; t t E L L </li></ul><ul><li>; 0 0 T I K K B L </li></ul><ul><li>; _ _ n N P P B B P B O </li></ul><ul><li>; 1 0 n I H H R R R N C </li></ul><ul><li>; _ _ _ T _ _ 0 1 I R K </li></ul><ul><li>; x x x n x x n n n n n </li></ul><ul><li>; 1 1 1 n 1 1 n n n n n </li></ul><ul><li>INC E_00007 { 00 11 00 11 11 11 00 11 11 11 11 } ; 420243.1 ; 3 ; 2 ; FS_TARESUMECLK;IDLE </li></ul><ul><li>INC E_00029 { 11 00 00 11 11 11 00 11 11 11 11 } ; 420257.1 ; 4 ; 3 </li></ul><ul><li>INC E_00007 { 00 11 00 11 11 11 00 11 11 11 11 } ; 420271.1 ; 5 ; 4 ; FS_TARESUMECLK;IDLE </li></ul><ul><li>INC E_00029 { 11 00 00 11 11 11 00 11 11 11 11 } ; 420285.1 ; 6 ; 5 ; </li></ul><ul><li>; Where: Vec_Def = Vector Definition Label </li></ul><ul><li>; csim_ts = Csim Time Stamp - Time stamp from the logic simulation that corresponds to this vector. </li></ul><ul><li>; tstr_cyc = Tester Cycle - Number of tester cycles execute up to this point </li></ul><ul><li>; tstr_rma = Tester Relative Main Address - assuming the pattern was loaded at Address '0', what </li></ul><ul><li>; address would this be? Think of this as the number of vectors executed up to this point. </li></ul><ul><li>; info = Other interesting facts about this vector - usually the TAP State and TAP Instruction </li></ul>
  7. 7. Basic Structure/Interaction: <ul><li>KX Period 1 – One (1) vector line per half bus cycle. Most pins only use F2 Data. Note : data pins are an exception to this (see below). </li></ul><ul><ul><li>Ex: </li></ul></ul>bclk 1 RMA 0 0 1 1 D63t48nn_63 1 1 0 0 VEC_DEF E_00136 E_00124 Timing &quot;s_s&quot;, 3, { PZ, TF @HDO_a, TF2 @HDO_b } &quot;d_d&quot;, 0, { PZ, DF2 @(bclk_drv_1) }
  8. 8. Basic Structure/Interaction: KX <ul><li>Main Memory </li></ul><ul><li>Subroutine Memory </li></ul>PreAmble (Long Reset) PLL Warmup Fuse LSD/LCP MidAmble (Short Reset) Init Routine Pattern (Individual Test) 64M Vectors Subroutines DO_NOTHING LONG_PLL_WarmUP REAL_LONG_PLL_WarmUp _______________________ GIFT Pad Area (Tools) 4K Vectors
  9. 9. Basic Structure: What else is in a pattern? <ul><li>Comments – Inactive line begin w/ “;” </li></ul><ul><ul><li>Header contains pin names delimiting columns. </li></ul></ul><ul><ul><li>Other comments give information to the user about what is happening or allow for post processing capabilities. </li></ul></ul><ul><ul><ul><li>; VCF_INSERT_PREAMBLE_HERE </li></ul></ul></ul><ul><ul><ul><li>; JTAG STRAP register setting </li></ul></ul></ul><ul><ul><ul><li>; Power on configuration setting </li></ul></ul></ul><ul><li>Labels – Active lines ending w/ a “;” </li></ul><ul><ul><li>Linked directly to a specific RMA such that tester software can jump to specific labels (and therefore a specific vector in the pattern). </li></ul></ul><ul><ul><ul><li>Ex. CPUres; - placed on the vector containing the rising edge of pin RESET . </li></ul></ul></ul>
  10. 10. Basic Structure: Reset & Initialization <ul><li>Generated from the “init_r1” test </li></ul><ul><li>Detailed information can be found at: http://mpgsites.intel.com/sites/MPGBD/PDE/TVPV/Yonah/Reset-Sequence/ </li></ul><ul><li>Noteworthy labels: </li></ul><ul><ul><li>pre_<b/e>_<PATNAME> </li></ul></ul><ul><ul><li>UNLOCKinstr<Start/End> </li></ul></ul><ul><ul><li>JTAGunlock_<Start/End> </li></ul></ul><ul><ul><li>PLLTESTinstr<Start/End> </li></ul></ul><ul><ul><li>JTAGpllTest_<Start/End> </li></ul></ul><ul><ul><li>JTAGSTRAPinstr<Start/End> </li></ul></ul><ul><ul><li>JTAGstraps_<Start/End> </li></ul></ul><ul><ul><li>FUSEinstr<Start/End> </li></ul></ul><ul><ul><li>JTAG_WRITE_FUSE_* </li></ul></ul><ul><ul><li><LSD/LCP>LOAD </li></ul></ul><ul><ul><li>mid_<b/e>_<PATNAME> </li></ul></ul><ul><ul><li>SIGCTLinstr<Start/End> </li></ul></ul><ul><ul><li>JTAGsigCtl_<Start/End> </li></ul></ul><ul><ul><li>JTAGSTRAPinstr<Start/End> </li></ul></ul><ul><ul><li>JTAGstraps_<Start/End> </li></ul></ul><ul><ul><li>RESUMECLKinstr<Start/End> </li></ul></ul><ul><ul><li>CPUres </li></ul></ul><ul><ul><li>FSB2Vector_1_<X> </li></ul></ul><ul><ul><li>ADS1cmp </li></ul></ul><ul><ul><li>POC_Active </li></ul></ul>
  11. 11. KX Example: <ul><li>Location: /nfs/iil/proj/yonah/tvpv12/eng/tvpv/validation/esherer/kx_example/ </li></ul><ul><li>What files do we see? </li></ul><ul><ul><li>*.m9k (*.e9k is not shown but denotes compiled pattern) </li></ul></ul><ul><ul><li>*.m9k.data </li></ul></ul><ul><ul><li>*.h </li></ul></ul><ul><li>What are the differences between the Pre/Mid Ambles and the Test Pattern itself in terms of content location? </li></ul><ul><ul><li>Pre/Mid Ambles are self contained in one *.m9k </li></ul></ul><ul><ul><li>Test Pattern contains all required directives in *.m9k (which “includes” the *.m9k.data file) </li></ul></ul><ul><ul><li>All 3 “patterns” use the same COMMON files for VEC_DEFS & Subroutine memory. </li></ul></ul>

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