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ATE Pattern Structure Basics

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Info for ATE pattern composition basic introduction

Info for ATE pattern composition basic introduction

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• 1. Pattern Structure & Basics
• 2. Topics:
• What is a pattern?
• 01000101010101010ā¦and more.
• What comprises a pattern?
• Data, Pindef, Vecdef, etc.
• How does it all work?
• Pattern Components + Test Program => Tester Does Stuff
• Pattern Example/Overview
• 3. What is a pattern?
• A pattern isā¦
• A collection of data that precisely describes the activity of each tester pin at bus clock resolution.
• The activity is executed by the tester via the test program.
• Generated by converting a trace, the output of a test simulated on an RTL model, that contains data at core clock resolution.
• Created specifically for each tester, taking into account the requirements and capabilities of different types of testers (S9K, CMT, ST2, IMS).
• 4. Pattern Components
• Pindef ā defines the connection between pattern data and tester channels.
• #avm ENABLE
• pindef ynh_fsbf2 {
• <12:12:1999 12:12:12>,
• TWO_BIT_BURST = TRUE,
• PACKAGE YNH_M_K_Cviu {
• BCLK1t0_1_x1 = IO ,F2 ,ADJACENT ,BIN ,{54},{&quot;A21&quot;},
• BCLK1t0_0_x1 = IO ,F2 ,ADJACENT ,BIN ,{55},{&quot;A22&quot;},
• RESETnn_x1 = IO ,F2 ,ADJACENT ,BIN ,{57},{&quot;B1&quot;},
• INITnn = IO ,F2 ,ADJACENT ,BIN ,{170},{&quot;B3&quot;},
• VCC_x1 = PWR ,{HCDPS2},{&quot;AA21&quot;},
• VSS = PWR ,{GND},{&quot;AA25&quot;},
• },
• PINGROUP {
• input = {A20Mnn,BPRInn,DEFERnn,DPSLPnn,DPWRnn,IGNNEnn,INITnn,LINT0,LINT1,
• PREQnn,PWRGOOD_x1,RESETnn_x1,rsnn,SLPnn,SMInn,STPCLKnn,TCK_x1,TDI_x1,
• TMS_x1,TRDYnn,TRSTnn,BCLK1t0_1_x1,BCLK1t0_0_x1},
• }
• };
• 5. Pattern Components
• Vecdef ā defines the sequences associated with each pin for a specific vector.
• VECTOR_DEF E_00000 =
• {
• PERIOD = Period_1,
• BCLK1t0_1_x1 = d_d 0/1 @,
• BCLK1t0_0_x1 = d_d 0/1 @,
• RESETnn_x1 = nop_nop 0/1 @,
• INITnn = d_d 0/1 @,
• AACLKPH_x1 = s_s 0/1 @,
• DCLKPH_x1 = s_s 0/1 @,
• ; pin names in pindef order seq sym
• ; seq = timing sequence name, must be predefined in the timing
• ; sym = vector data symbols for '0' and '1'
• }
• 6. Pattern Components
• Vector ā contains the tester data for each specific tester period.
• ; opcode (operand) Vec_Def pattern data csim_ts ; tstr_cyc ; tstr_rma ; info
• MAIN_F;
• ; B B
• ; C C
• ; L L R A
• ; K K E A D
• ; 1 1 S C C
• ; t t E L L
• ; 0 0 T I K K B L
• ; _ _ n N P P B B P B O
• ; 1 0 n I H H R R R N C
• ; _ _ _ T _ _ 0 1 I R K
• ; x x x n x x n n n n n
• ; 1 1 1 n 1 1 n n n n n
• INC E_00007 { 00 11 00 11 11 11 00 11 11 11 11 } ; 420243.1 ; 3 ; 2 ; FS_TARESUMECLK;IDLE
• INC E_00029 { 11 00 00 11 11 11 00 11 11 11 11 } ; 420257.1 ; 4 ; 3
• INC E_00007 { 00 11 00 11 11 11 00 11 11 11 11 } ; 420271.1 ; 5 ; 4 ; FS_TARESUMECLK;IDLE
• INC E_00029 { 11 00 00 11 11 11 00 11 11 11 11 } ; 420285.1 ; 6 ; 5 ;
• ; Where: Vec_Def = Vector Definition Label
• ; csim_ts = Csim Time Stamp - Time stamp from the logic simulation that corresponds to this vector.
• ; tstr_cyc = Tester Cycle - Number of tester cycles execute up to this point
• ; tstr_rma = Tester Relative Main Address - assuming the pattern was loaded at Address '0', what
• ; address would this be? Think of this as the number of vectors executed up to this point.
• ; info = Other interesting facts about this vector - usually the TAP State and TAP Instruction
• 7. Basic Structure/Interaction:
• KX Period 1 ā One (1) vector line per half bus cycle. Most pins only use F2 Data. Note : data pins are an exception to this (see below).
• Ex:
bclk 1 RMA 0 0 1 1 D63t48nn_63 1 1 0 0 VEC_DEF E_00136 E_00124 Timing &quot;s_s&quot;, 3, { PZ, TF @HDO_a, TF2 @HDO_b } &quot;d_d&quot;, 0, { PZ, DF2 @(bclk_drv_1) }
• 8. Basic Structure/Interaction: KX
• Main Memory
• Subroutine Memory
PreAmble (Long Reset) PLL Warmup Fuse LSD/LCP MidAmble (Short Reset) Init Routine Pattern (Individual Test) 64M Vectors Subroutines DO_NOTHING LONG_PLL_WarmUP REAL_LONG_PLL_WarmUp _______________________ GIFT Pad Area (Tools) 4K Vectors
• 9. Basic Structure: What else is in a pattern?
• Comments ā Inactive line begin w/ ā;ā
• Header contains pin names delimiting columns.
• Other comments give information to the user about what is happening or allow for post processing capabilities.
• ; VCF_INSERT_PREAMBLE_HERE
• ; JTAG STRAP register setting
• ; Power on configuration setting
• Labels ā Active lines ending w/ a ā;ā
• Linked directly to a specific RMA such that tester software can jump to specific labels (and therefore a specific vector in the pattern).
• Ex. CPUres; - placed on the vector containing the rising edge of pin RESET .
• 10. Basic Structure: Reset & Initialization
• Generated from the āinit_r1ā test
• Detailed information can be found at: http://mpgsites.intel.com/sites/MPGBD/PDE/TVPV/Yonah/Reset-Sequence/
• Noteworthy labels:
• pre_<b/e>_<PATNAME>
• UNLOCKinstr<Start/End>
• JTAGunlock_<Start/End>
• PLLTESTinstr<Start/End>
• JTAGpllTest_<Start/End>
• JTAGSTRAPinstr<Start/End>
• JTAGstraps_<Start/End>
• FUSEinstr<Start/End>
• JTAG_WRITE_FUSE_*
• mid_<b/e>_<PATNAME>
• SIGCTLinstr<Start/End>
• JTAGsigCtl_<Start/End>
• JTAGSTRAPinstr<Start/End>
• JTAGstraps_<Start/End>
• RESUMECLKinstr<Start/End>
• CPUres
• FSB2Vector_1_<X>