Ovonic Unified MemoryDEPT. OF E & C., GECH. 2013 Page 1VISVESVARAYA TECHNOLOGICAL UNIVERSITYBELGAUM-590014Technical Seminar Report onOVONIC UNIFIED MEMORYSubmitted in partial fulfillment of the requirements for the award of degreeBACHELOR OF ENGINEERINGINELECTRONICS AND COMMUNICATION ENGINEERINGBYSRINIVAS H.V(4GH09EC046)Under the guidance ofMrs. SHRUTHI K.N.B.E., M.TECH.Assistant ProfessorDEPT OF E & CGEC.HASSAN-573 201Department of Electronics and Communication EngineeringGOVERNMENT ENGINEERING COLLEGEDairy Circle, Hassan - 5732012012-2013
Ovonic Unified MemoryDEPT. OF E & C., GECH. 2013 Page 2GOVERNMENT ENGINEERING COLLEGEDAIRY CIRCLE, HASSAN-573201Department of Electronics and Communication EngineeringCERTIFICATEThis is to certify that the seminar work entitled “OVONIC UNIFIEDMEMORY” carried out by SRINIVAS H.V, with USN - 4GH09EC046is a bonafidestudent of Government Engineering College, Hassan in partial fulfillment ofrequirements as part of the VIII semester Technical Seminar prescribed by theVisvesvaraya Technological University, Belgaum during the academic year 2012-2013.It is certified that, all corrections/suggestions indicated for Internal Assessment have beenincorporated in the report deposited in the departmental library. The project report hasbeen approved as it satisfies the academic requirements with respect of seminarprescribed for the said Degree.Seminar Guide Seminar Coordinator--------------------------------------------- -----------------------------------------Mrs. SHRUTHI K.N. B.E., M.TECH. Mrs. PALLAVI H.V. B.E., M.TECH,.LMISTEAssistant Professor Associate ProfessorDEPT.OF E& C DEPT.OF E& CGECH-573 201 GECH-573 201Name and Signature of HOD--------------------------------------------Dr. PARAMESH B.E., M.TECH. , Ph.D.Professor and HeadDEPT. OF E & CGECH-573201
Ovonic Unified MemoryDEPT. OF E & C., GECH. 2013 Page 3ACKNOWLEDGEMENTI wish to express my thanks to beloved PRINCIPAL DR.KARISIDDAPPA, forencouragement throughout my studies.I express my gratitude to DR.PARAMESH, PROFESSOR AND HEAD, dept. ofElectronics and Communication Engineering, for his encouragement and supportthroughout my work.I also express my warm gratitude to MRS. PALLAVI H.V., ASSOCIATEPROFESSOR, dept. of Electronics and Communication Engineering, for her greatsupport during the preparation of seminar and also in helping in curricular activities.At the outset I express my most sincere grateful thanks to my seminar guide,MRS. SHRUTHI K.N., ASSISTANT PROFESSOR, dept. of Electronics andCommunication Engineering for continuous support and advice not only during thecourse of my seminar but also during the period of my stay in GECH.I also gratefully thank to the holy sanctum “GOVERNMENTENGINEERINGCOLLEGE, HASSAN” the temple of learning, for giving me anopportunity to pursue the degree course in Electronics and Communication Engineeringthus help in shaping my carrier.Finally I express my gratitude to all teaching staff of dept. of Electronics andCommunication Engineering, my classmates and my parents for their timely support andsuggestions.I am conscious of the fact that I have received co-operation in many ways fromthe teaching and non-teaching staff of the dept. of Electronics and CommunicationEngineering and I am grateful to all of their co-operation and their guidance incompleting the task well in time. I thank once again to one and all who have been helpedme in one or the other way in completing my seminar in time.SRINIVAS H.V(4GH09EC046)
Ovonic Unified MemoryDEPT. OF E & C., GECH. 2013 Page 4ABSTRACTNowadays, digital memories are used in each and every fields of day-to-day life.Semiconductors form the fundamental blocks of the modern electronic world providingthe brains and the memory of products all around us from washing machines to supercomputers. But now we are entering an era of material limited scaling. Continuousscaling has required the introduction of new materials.Current memory technologies have a lot of limitations. The new memorytechnologies have got all the good attributes for an ideal memory. Among them OvonicUnified Memory (OUM) is the most promising one. OUM is a type of nonvolatilememory, which uses chalcogenide materials for storage of binary data. The termchalcogen refers to the Group VI elements of the periodic table. Chalcogenide refers toalloys containing at least one of these elements such as the alloy of germanium, antimonyand tellurium, which is used as the storage element in OUM. Electrical energy (heat) isused to convert the material between crystalline (conductive) and amorphous (resistive)phases and the resistive property of these phases is used to represent 0s and 1s.To write data into the cell, the chalcogenide is heated past its melting point andthen rapidly cooled to make it amorphous. To make it crystalline, it is heated to justbelow its melting point and held there for approximately 50ns, giving the atoms time toposition themselves in their crystal locations. Once programmed, the memory state of thecell is determined by reading its resistance.
Ovonic Unified MemoryDEPT. OF E & C., GECH. 2013 Page 5LIST OF FIGURESFIGURE 5.1 Structural states of chalcogenide alloy 12FIGURE 5.2 Temperature profile 13FIGURE 5.3 OUM Architecture 14FIGURE 6.1 Temperature v/s time plot 16FIGURE 6.2 Resistance v/s pulse width plot 17FIGURE6.3 V-I Characteristics 17FIGURE 6.4 R-I Characteristics 18FIGURE 7.1 Integration with CMOS 19FIGURE 7.2 V-I Characteristics 20FIGURE 7.3 R-I Characteristics 21FIGURE 7.4 Drain current v/s gate voltage plot 22FIGURE 9.1 Ternary system 24
Ovonic Unified MemoryDEPT. OF E & C., GECH. 2013 Page 6CONTENTSCERTIFICATE iiACKNOWLEDGEMENT iiiABSTRACT ivLIST OF FIGURES vCHAPTER 1 INTRODUCTION 1-2CHAPTER 2 HISTORY OF OUM 3-4CHAPTER 3 PRESENT MEMORY TECHNOLOGY SCENARIO 53.1 Review of memory basics 5-63.2 Memory device characteristics 63.2.1 Cost 63.2.2 Access time and access rate 6-73.2.3 Access mode-random and serial 7-83.2.4 Alterability-ROMS 83.2.5 Permanence of storage 8-93.2.6 Cycle time and data transfer rate 9CHAPTER 4 EMERGING MEMORY TECHNOLOGIES 104.1 Fundamental ideas of emerging memories 10-11CHAPTER 5 OVONIC UNIFIED MEMORY TECHNOLOGY 12-145.1 OUM Attributes 145.2 OUM Architecture 14-15CHAPTER 6 BASIC DEVICE OPERATION 166.1 Technology and performance 16-176.2 V-I Characteristics 17-186.3 R-I Characteristics 18CHAPTER 7 INTEGRATION WITH CMOS 19-22
Ovonic Unified MemoryDEPT. OF E & C., GECH. 2013 Page 7CHAPTER 8 ADVANTAGES AND RISK FACTORS OF OUM 23CHAPTER 9 ABOUT CHALCOGENIDE ALLOY 249.1 Comparison of amorphous and crystalline state 249.2 Test results 24-25CONCLUSION 26REFERENCES 27
Ovonic Unified MemoryDEPT. OF E & C., GECH. 2013 Page 8CHAPTER 1INTRODUCTIONWe are now living in a world driven by various electronic equipments.Semiconductors form the fundamental building blocks of the modern electronic worldproviding the brains and the memory of products all around us from washing machines tosuper computers. Semiconductors consist of array of transistors with each transistor beinga simple switch between electrical 0 and 1. Now often bundled together in their 10‟s ofmillions they form highly complex, intelligent, reliable semiconductor chips, which aresmall and cheap enough for proliferation into products all around us.Identification of new materials has been, and still is, the primary means in thedevelopment of next generation semiconductors. For the past 30 years, relentless scalingof CMOS IC technology to smaller dimensions has enabled the continual introduction ofcomplex microelectronics system functions. However, this trend is not likely to continueindefinitely beyond the semiconductor technology roadmap. As silicon technologyapproaches its material limit, and as we reach the end of the roadmap, an understandingof emerging research devices will be of foremost importance in the identification of newmaterials to address the corresponding technological requirements.If scaling is to continue to and below the 65nm node, alternatives to CMOSdesigns will be needed to provide a path to device scaling beyond the end of the roadmap.However, these emerging research technologies will be faced with an uphill technologychallenge. For digital applications, these challenges include exponentially increasing theleakage current (gate, channel, and source/drain junctions), short channel effects, etc.while for analogue or RF applications, among the challenges are sustained linearity, lownoise figure, power added efficiency and transistor matching. One of the fundamentalapproaches to manage this challenge is using new materials to build the next generationtransistors.Almost 25% of the world wide chip markets are memory devices, each type usedfor their specific advantages: the high speed of an SRAM, the high integration density ofa DRAM, or the nonvolatile capability of a FLASH memory device.The industry is searching for a holy grail of future memory technologies to servicethe upcoming market of portable and wireless devices. These applications are already
Ovonic Unified MemoryDEPT. OF E & C., GECH. 2013 Page 9available based on existing memory technology, but for a successful market penetration.A higher performance at a lower price is required. The existing technologies arecharacterized by the following limitations. DRANs are difficult to integrate. SRAMs areexpensive. FLASH memory can have only a limited number of read and write cycles.EPROMs have high power requirement and poor flexibility.There is a growing need for nonvolatile memory technology for high densitystandalone embedded CMOS application with faster write speed and higher endurancethan existing nonvolatile memories. OUM is a promising technology to meet this need.R.G.Neale, D.L.Nelson and Gorden.E.Moore originally reported a phase-change memorybased on chalcogenide materials in 1970. Improvements in phase-change materialstechnology subsequently paved the way for development of commercially availablerewriteable CDs and DVD optical memory disks. These advances, coupled withsignificant technology scaling and better understanding of the fundamental electricaldevice operation, have motivated development of the OUM technology at the present daytechnology node.Ovonic Unified Memory (OUM) is the nonvolatile memory that utilizes areversible structural phase change between amorphous and polycrystalline states in aGeSbTe chalcogenide alloy material. This transition is accomplished by heating a smallvolume of the material with a write current pulse and results in a considerable change inalloy resistivity. The amorphous phase has high resistance and is defined as the RESETstate. The low resistance polycrystalline phase is defined as the SET state.
Ovonic Unified MemoryDEPT. OF E & C., GECH. 2013 Page 10CHAPTER 2HISTORY OF OVONIC UNIFIED MEMORY (OUM)In the 1960s, Stanford R. Ovshinsky of Energy Conversion Devices firstexplored the properties of chalcogenide glasses as a potential memory technology. In1969, Charles Sie published a dissertation, at Iowa State University that both describedand demonstrated the feasibility of a phase change memory device by integratingchalcogenide film with a diode array. A cinematographic study in 1970 established thatthe phase change memory mechanism in chalcogenide glass involves electric-field-induced crystalline filament growth. In the September 1970 issue of Electronics, GordonMoore co-founder of Intel published an article on the technology. However, materialquality and power consumption issues prevented commercialization of the technology.More recently, interest and research have resumed as flash and DRAM memorytechnologies are expected to encounter scaling difficulties as chip lithography shrinks.The crystalline and amorphous states of chalcogenide glass have dramaticallydifferent electrical resistivity. The amorphous, high resistance state represents a binary 1,while the crystalline, low resistance state represents a 0. Chalcogenide is the samematerial used in re-writable optical media (such as CD-RW and DVD-RW). In thoseinstances, the materials optical properties are manipulated, rather than its electricalresistivity, as chalcogenide refractive index also changes with the state of the material.Magnetic Random Access Memory (MRAM), a technology first developed inthe 1970s, but rarely commercialized, has attracted by the backing of I.B.M, Motorolaand others. MRAM stores information by flip flopping two layers of magnetic material inand out of alignment with an electric current. For reading and writing data, MRAM canbe as fast as a few nanoseconds, or billionths of a second, best among the next threegeneration memory candidates. And if promises to integrate easily with the industrysexisting chip manufacturing process. MRAM is built on top of silicon circuitry. Thebiggest problem with MRAM is a relatively small distance, difficult to detect, between itsON and OFF states.The second potential successor to flash, Ferro-electric Random Access Memory(FeRAM / FRAM), has actually been commercially available for nearly 15 years, hasattracted by the backing of Fujitsu, Matsushita, I.B.M. and Ramtron. FRAM relies on the
Ovonic Unified MemoryDEPT. OF E & C., GECH. 2013 Page 11polarization of what amount to tiny magnets inside certain materials like perouikite, frombasaltic rocks. FRAM memory cells do not wear out until they have been read or writtento billions of times, while MRAM and OUM would require the addition of six to eight"masking" layers in the chip manufacturing process, just like Flash, FRAM might requireas little as two extra layers.OVONIC UNIFIED MEMORY is based on the information storage technologydeveloped by Mr. Ovshinsky that allows rewriting of CDs and DVDs. While CD andDVD drives read and write ovonic material with lasers, OUM uses electric current tochange the phase of memory cells. These cells are either in crystalline state, whereelectrical resistance is low or in amorphous state, where resistance is high. OUM can beread and write to trillionths of times making its use essentially nondestructive, unlikeMRAM or FRAM. OUMs dynamic range, difference between the electrical resistance inthe crystalline state and in the amorphous state-is wide enough to allow more than one setof ON and OFF values in a cell, dividing it in to several bits and multiplying memorydensity by two, four potential even 16 times. OUM is not as fast as MRAM. The OUMsolid-state memory has cost advantages over conventional solid-state memories such asDRAM or Flash due to its thin-film nature, very small active storage media, and simpledevice structure. OUM requires fewer steps in an IC manufacturing process resulting inreduced cycle times, fewer defects, and greater manufacturing flexibility.
Ovonic Unified MemoryDEPT. OF E & C., GECH. 2013 Page 12CHAPTER 3PRESENT MEMORY TECHNOLOGY SCENARIOAs stated, revising the memory technology fields ruled by silicon technology is ofgreat importance. Digital Memory is and has been a close comrade of each and everytechnical advancement in Information Technology. The current memory technologieshave a lot of limitations. DRAM is volatile and difficult to integrate. RAM is high costand volatile. Flash has slower writes and lesser number of write / erase cycles comparedto others. These memory technologies when needed to expand will allow expansion onlytwo-dimensional space. Hence area required will be increased. They will not allowstacking of one memory chip over the other. Also the storage capacities are not enough tofulfill the exponentially increasing need. Hence industry is searching for “Holy Grail”future memory technologies that are efficient to provide a good solution. Next generationmemories are trying tradeoffs between size and cost. These make them good possibilitiesfor development.3.1 Review of memory basicsEvery computer system contains a variety of devices to store the instructions anddata required for its operation. These storage devices plus the algorithms needed tocontrol or manage the stored information constitute the memory system of the computer.In general, it is desirable that processors should have immediate and interrupted access tomemory, so the time required to transfer information between the processor and memoryshould be such that the processor can operate at, close to, its maximum speed.Unfortunately, memories that operate at speeds comparable to processors speed are verycostly. It is not feasible to employ a single memory using just one type of technology.Instead the stored information is distributed in complex fashion over a variety of differentmemory units with very different physical characteristics.The memory components of a computer can be subdivided into three main groups:1) Internal processor memory: This usually comprises of a small set of high speedregisters used as working registers for temporary storage of instructions and data.2) Main memory: This is a relatively large fast memory used for program and datastorage during computer operation. It is characterized by the fact that location in the main
Ovonic Unified MemoryDEPT. OF E & C., GECH. 2013 Page 13memory can be directly accessed by the CPU instruction set. The principal technologiesused for main memory are semiconductor integrated circuits and ferrite cores.3) Secondary memory: This is generally much larger in capacity but also much slowerthan main memory. It is used for storing system programs and large data files and thelikes which are not continually required by the CPU; it also serves as an overflowmemory when the capacity of the main memory is exceeded. Information in secondarystorage is usually accessed directly via special programs that first transfer the requiredinformation to main memory. Representative technologies used for secondary memoryare magnetic disks and tapes.3.2 Memory device characteristicsThe computer architect is faced with a bewildering variety of memory devices touse. However; all memories are based on a relatively small number of physicalphenomena and employ relatively few organizational principles. The characteristics andthe underlying physical principles of some specific representative technologies are alsodiscussed.3.2.1 CostThe cost of a memory unit is almost meaningfully measured by the purchase orlease price to the user of the complete unit. The price should include not only the cost ofthe information storage cells themselves but also the cost of the peripheral equipment oraccess circuitry essential to the operation of the memory.3.2.2 Access time and access rateThe performance of a memory device is primarily determined by the rate at whichinformation can be read from or written into memory. A convenient performance measureis the average time required to read a fixed amount of information from the memory. Thisis termed read access time. The write access time is defined similarly; it is typically butnot always equal to the read access time. Access time depends on the physicalcharacteristics of the storage medium, and also on the type of access mechanism used. Itis usually calculated from the time a read request is received by the memory and to thetime at which all the requested information has been made available at the memory outputterminals. The access rate of the memory is defined is the inverse of the access time.
Ovonic Unified MemoryDEPT. OF E & C., GECH. 2013 Page 14Clearly low cost and high access rate are desirable memory characteristics;unfortunately they appear to be largely compatible. Memory units with high access ratesare generally expensive, while low cost memory are relatively slow.3.2.3 Access mode-random and serialAn important property of a memory device is the order or sequence in whichinformation can be accessed. If locations may be accessed in any order and the accesstime is independent of the location being accessed, the memory is termed as a randomaccess memory.Ferrite core memory and semiconductor memory are usually of this type.Memories where storage locations can be accessed only in a certain predeterminedsequence are called serial access memories. Magnetic tape units and magnetic bubblememories employ serial access methods.In a random access memory each storage location can be accessed independentlyof the other locations. There is, in effect, a separate access mechanism, or read-write, forevery location. In serial memories, on the other hand, the access mechanism is sharedamong different locations. It must be assigned to different locations at different times.This is accomplished by moving the stored information, the read write head or both.Many serial access memories operate by continually moving the storage locations arounda closed path or track. A particular location can be accessed only when it passes the fixedread write head; thus the time required to access a particular location depends on therelative location of the read/write head when the access request is received.Since every location has its own addressing mechanism, random access memorytends to be more costly than the serial type. In serial type memory, however the timerequired bringing the desired location into correspondence with a read/write headincreases the effective access time, so access tends to be slower than the random access.Thus the access mode employed contributes significantly to the inverse relation betweencost and access time.Some memory devices such as magnetic disks and DRAMs contain large numberof independently rotating tracks. If each track has its own read-write head, the track maybe accessed randomly, although access within track in serial. In such cases the access
Ovonic Unified MemoryDEPT. OF E & C., GECH. 2013 Page 15mode is sometimes called semi random or direct access. It should be noted that the accessis a function of the memory technology used.3.2.4 Alterability-ROMSThe method used to write information into a memory may be irreversible, in thatonce the information has been written, it cannot be altered while the memory is in use,i.e., online. Punching holes in cards and printing on paper are examples of essentiallypermanent storage techniques. Memories whose contents cannot be altered online arecalled read only memories. A ROM is therefore a non-alterable storage device. ROMs arewidely used for storing control programs such as micro programs. ROMs whose contentscan be changed are called programmable read only memories (PROMs).Memories in which reading or writing can be done with impunity online aresometimes called read-write memories (RWMs) to contrast them with ROMs. Allmemories used for temporary storage are RWMs.3.2.5 Permanence of storageThe physical processes involved in storage are sometimes inherently unstable, sothat the stored information may be lost over a period of time unless appropriate action istaken. There are important memory characteristics that can destroy information:1. Destructive read out2. Dynamic volatility3. VolatilityFerrite core memories have the property that the method of reading the memoryalters, i.e., destroys, the stored information; this phenomenon is called destructive readout (DRO). Memories in which reading does not affect the stored data are said to havenondestructive readout (NRDO). In DRO memories, each read operation must befollowed by a write operation that restores the original state of the memory. Thisrestoration is usually carried out by automatically using a buffer register.Certain memory devices have the property that a stored 1 tends to become a 0, orvice versa, due to some physical decay processes. Over a period of time, a stored chargetends to leak away, causing a loss of information unless the stored charge is restored. This
Ovonic Unified MemoryDEPT. OF E & C., GECH. 2013 Page 16process of restoring is called refreshing. Memories which require periodic refreshing arecalled dynamic memories, as opposed to static memories, which require no refreshing.Most memories that using magnetic storage techniques are static. Refreshing in dynamicmemories can be carried out in the same way data is restored in a DRO memory. Thecontents of every location are transferred systematically to a buffer register and thenreturned, in suitably amplified form, to their original locations.Another physical process that can destroy the contents of a memory is the failureof power supply. A memory is said to be volatile if the stored information can bedestroyed by a power failure. Most semiconductor memories are volatile, while mostmagnetic memories are non-volatile.3.2.6 Cycle time and data transfer rateThe access time of a memory is defined as the time between the receipt of a readrequest and the delivery of the requested information to its external output terminals. InDRO and dynamic memories, it may not be possible to initiate another memory accessuntil a restore or refresh operation has been carried out. This means that the minimumtime that must elapse between the initiations of two different accesses by the memory canbe greater than the access time: this rather loosely defined time is called the cycle time ofthe memory.It is generally convenient to assume the cycle time as the time needed to completeany read or write operation in the memory. Hence the maximum amount of informationthat can be transferred to or from the memory every second is the reciprocal of cycletime. This quantity is called the data transfer rate or band width.
Ovonic Unified MemoryDEPT. OF E & C., GECH. 2013 Page 17CHAPTER 4EMERGING MEMORY TECHNOLOGIESMany new memory technologies were introduced when it is understood thatsemiconductor memory technology has to be replaced, or updated by its successor sincescaling with semiconductor memory reached its material limit. These memorytechnologies are referred as „Next Generation Memories”. Next Generation Memoriessatisfy all of the good attributes of memory. The most important one among them is theirability to support expansion in three-dimensional spaces. Intel, the biggest maker ofcomputer processors, is also the largest maker of flash-memory chips is trying to combinethe processing features and space requirements feature and several next generationmemories are being studied in this perspective. They include MRAM, FeRAM, PolymerMemory Ovonic Unified Memory, ETOX-4BPC, NRAM etc. One or two of them willbecome the mainstream.4.1 Fundamental ideas of emerging memoriesThe fundamental idea of all these technologies is the bistable nature possible forof the selected material. FeRAM works on the basis of the bistable nature of the centeratom of selected crystalline material. A voltage is applied upon the crystal, which in turnpolarizes the internal dipoles up or down. i.e. actually the difference between these statesis the difference in conductivity. Non –Linear FeRAM read capacitor, i.e., the crystal unitplaced in between two electrodes will remain in the direction polarized (state) by theapplied electric field until another field capable of polarizing the crystal‟s central atom toanother state is applied.In the case of Polymer memory data stored by changing the polarization of thepolymer between metal lines (electrodes). To activate this cell structure, a voltage isapplied between the top and bottom electrodes, modifying the organic material. Differentvoltage polarities are used to write and read the cells. Application of an electric field to acell lowers the polymer‟s resistance, thus increasing its ability to conduct current; thepolymer maintains its state until a field of opposite polarity is applied to raise itsresistance back to its original level. The different conductivity states represent bits ofinformation.
Ovonic Unified MemoryDEPT. OF E & C., GECH. 2013 Page 18In the case of NRAM ONO stacks are used to store charges at specific locations.This requires a charge pump for producing the charges required for writing into thememory cell. Here charge is stored at the ON junctions.Phase change memory also called Ovonic Unified Memory (OUM), is based onrapid reversible phase change effect in materials under the influence of electric currentpulses. The OUM uses the reversible structural phase-change in thin-film material (e.g.,chalcogenide) as the data storage mechanism. The small volume of active media acts as aprogrammable resistor between a high and low resistance with > 40X dynamic range.Ones and zeros are represented by crystalline versus amorphous phase states of activematerial. Phase states are programmed by the application of a current pulse through aMOSFET, which drives the memory cell into a high or low resistance state, depending oncurrent magnitude. Measuring resistance changes in the cell performs the function ofreading data. OUM cells can be programmed to intermediate resistance values; e.g., formultistate data storage.MRAMs are based on the magneto resistive effects in magnetic materials andstructures that exhibit a resistance change when an external magnetic field is applied. Inthe MRAM, data are stored by applying magnetic fields that cause magnetic materials tobe magnetized into one of two possible magnetic states. Measuring resistance changes inthe cell compared to a reference performs reading data. Passing currents nearby orthrough the magnetic structure creates the magnetic fields applied to each cell.
Ovonic Unified MemoryDEPT. OF E & C., GECH. 2013 Page 19CHAPTER 5OVONIC UNIFIED MEMORY (OUM)TECHNOLOGYAmong the above-mentioned non-volatile memories, Ovonic Unified Memory isthe most promising one. “Ovonic Unified Memory” is the registered name for the non-volatile memory based on the material called chalcogenide.The term “chalcogen” refers to the Group VI elements of the periodic table.“Chalcogenide” refers to alloys containing at least one of these elements such as the alloyof germanium, antimony, and tellurium discussed here. Energy Conversion Devices, Inc.has used this particular alloy to develop a phase-change memory technology used incommercially available rewriteable CD and DVD disks. This phase change technologyuses a thermally activated, rapid, reversible change in the structure of the alloy to storedata. Since the binary information is represented by two different phases of the material itis inherently non-volatile, requiring no energy to keep the material in either of its twostable structural states.The two structural states of the chalcogenide alloy, as shown in Figure 5.1, are anamorphous state and a polycrystalline state. Relative to the amorphous state, thepolycrystalline state shows a dramatic increase in free electron density, similar to a metal.This difference in free electron density gives rise to a difference in reflectivity andresistivity. In the case of the re-writeable CD and DVD disk technology, a laser is used toheat the material to change states. Directing a low-power laser at the material anddetecting the difference in reflectivity between the two phases read the state of thememory.FIGURE 5.1 Structural states of chalcogenide alloy
Ovonic Unified MemoryDEPT. OF E & C., GECH. 2013 Page 20Ovonyx, Inc., under license from Energy Conversion Devices, Inc., is workingwith several commercial partners to develop a solid-state non-volatile memorytechnology using the chalcogenide phase change material. To implement a memory thedevice is incorporated as a two terminal resistor element with standard CMOS processing.Resistive heating is used to change the phase of the chalcogenide material. Dependingupon the temperature profile applied, the material is either melted by taking it above themelting temperature (Tm) to form the amorphous state, or crystallized by holding it at alower temperature (Tx) for a slightly longer period of time, as shown in Figure 5.2. Thetime needed to program either state is = 400ns. Multiple resistance states between thesetwo extremes have been demonstrated, enabling multi-bit storage per memory cell.However, current development activities are focused on single-bit applications. Onceprogrammed, the memory state of the cell is determined by reading its resistance.FIGURE 5.2 Temperature profileA radiation hardened semiconductor technology incorporating chalcogenide basedmemory elements will address both critical and enabling space system needs, includingstandalone memory modules and embedded cores for microprocessors and ASICs.Previously, BAE SYSTEMS and Ovonyx have reported on the results of discrete memoryelements fabricated in BAE SYSTEMS‟ Manassas, Virginia facility. These devices weremanufactured using standard semiconductor process equipment to sputter and etch thechalcogenide material. While built in the same line used to fabricate radiation-hardened
Ovonic Unified MemoryDEPT. OF E & C., GECH. 2013 Page 21CMOS products, these memory elements were not yet integrated with transistors. Theywere discrete two-terminal programmable resistors, requiring approximately 0.6 mA toset the device into a low resistance state, and 1.3 mA to reset it to the high resistancestate. One billion (1E9) write cycles between these two states were demonstrated.Reading the state of the device is non-destructive and has no impact on device wear out(unlimited read cycles).5.1 OUM Attributes Non-volatile in nature. High density ensures large storage of data within a small area. Non-destructive read:-ensures that the data is not corrupted during a read cycle. Uses very low voltage and power from a single source. Write/erase cycles of 10e12 are demonstrated. Poly crystalline. This technology offers the potential of easy addition of non-volatile memory to astandard CMOS process. This is a highly scalable memory. Low cost implementation is expected.5.2 OUM ArchitectureFIGURE 5.3 OUM Architecture
Ovonic Unified MemoryDEPT. OF E & C., GECH. 2013 Page 22A memory cell consists of a top electrode, a layer of the chalcogenide, and aresistive heating element. The base of the heater is connected to a diode. As with MRAM,reading the micrometer-sized cell is done by measuring its resistance. But unlike MRAMthe resistance change is very large-more than a factor of 100. Thermal insulators are alsoattached to the memory structure in order to avoid data lose due to destruction of materialat high temperatures.To write data into the cell, the chalcogenide is heated past its melting point andthen rapidly cooled to make it amorphous. To make it crystalline, it is heated to justbelow its melting point and held there for approximately 50ns, giving the atoms time toposition themselves in their crystal locations.
Ovonic Unified MemoryDEPT. OF E & C., GECH. 2013 Page 23CHAPTER 6BASIC DEVICE OPERATIONThe basic device operation can be explained from the temperature versus timegraph shown in figure 6.1. During the amorphizing reset pulse, the temperature of theprogrammed volume of phase change material exceeds the melting point whicheliminates the poly crystalline order in the material. When the reset pulse is terminatedthe device quenches to freeze in the disordered structural state. The quench time isdetermined by the thermal environment of the device and the fall time of the pulse. Thecrystallizing set pulse is of lower amplitude and of sufficient duration to maintain thedevice temperature in the rapid crystallization range for a time sufficient for crystalgrowth.FIGURE 6.1 Temperature v/s time plot6.1 Technology and performanceThe figure 6.2 on next page shows device resistance versus write pulse width. Thereset resistance saturates when the pulse width is long enough to achieve melting of thephase change material. The set pulse adequately crystallizes the bit in 50 ns with aRESET/SET resistance ratio of greater than 100.
Ovonic Unified MemoryDEPT. OF E & C., GECH. 2013 Page 24FIGURE 6.2 Resistance v/s pulse width plot6.2 V-I CharacteristicsFIGURE 6.3 V-I CharacteristicsThe figure 6.3 shows V-I characteristics of the OUM device. At low voltages, thedevice exhibits either a low resistance (~1k) or high resistance (>100k), depending on itsprogrammed state. This is the read region of operation. To program the device, a pulse ofsufficient voltage is applied to drive the device into a high conduction “dynamic onstate”. For a reset device, this requires a voltage greater than Vth.Vth is the device design parameter and for current memory application is chosento be in the range of 0.5 to 0.9 V. to avoid read disturb, the device read region as shownin the figure, is well below Vth and also below the reset regime.
Ovonic Unified MemoryDEPT. OF E & C., GECH. 2013 Page 25The device is programmed while it is in the dynamic on state. The finalprogrammed state of the device is determined by the current amplitude and the pulseduration in the dynamic on state. The reciprocal slope of the V-I curve in the dynamic onstate is the series device resistance.6.3 R-I CharacteristicsFIGURE 6.4 R-I CharacteristicsThe figure 6.4 shows the device read resistance resulting from application of theprogramming current pulse amplitude. Starting in the set condition, moving from left toright, the device continues to remain in SET state as the amplitude is increased. Furtherincrease in the pulse amplitude begins to reset the device with still further increaseresetting the device to a standard amorphous resistance. Beginning again with a deviceinitially in the RESET state, low amplitude pulses at voltages less than Vth do not set thedevice. Once Vth is surpassed, the device switches to the dynamic on state andprogrammed resistance is dramatically reduced as crystallization of the material isachieved. Further increase in programming current further crystallizes the material, whichdrops the resistance to a minimum value. As the programming pulse amplitude isincreased further, resetting again is exhibited as in the case above. Devices can be safelyreset above the saturation point for margin. Importantly, the right side of the curveexhibits direct overwrite capability, where a particular resistance value can be obtainedfrom a programming pulse, irrespective of the prior state of the material. The slope of theright side of the curve is the device design parameter and can be adjusted to enable amulti- state memory cell.
Ovonic Unified MemoryDEPT. OF E & C., GECH. 2013 Page 26CHAPTER 7INTEGRATION WITH CMOSUnder contract to the Space Vehicles Directorate of the Air Force ResearchLaboratory (AFRL), BAE SYSTEMS and Ovonyx began the current program in Augustof 2001 to integrate the chalcogenide-based memory element into a radiation-hardenedCMOS process. The initial goal of this effort was to develop the processes necessary toconnect the memory element to CMOS transistors and metal wiring, without degradingthe operation of either the memory elements or the transistors. It also was desired tomaximize the potential memory density of the technology by placing the memory elementdirectly above the transistors and below the first level of metal as shown in a simplifieddiagram in Figure 7.1.FIGURE 7.1 Integration with CMOSTo accomplish this process integration task, it was necessary to design a test chipwith appropriate structures. This vehicle was called the Access Device Test Chip (ADTC)since each memory cell requires an access device (transistor) in addition to the
Ovonic Unified MemoryDEPT. OF E & C., GECH. 2013 Page 27chalcogenide memory element. Such a memory cell, comprised of one access transistorand one chalcogenide resistor, is herein referred to as a1T1R cell. The ADTC included272 macros, each with 2 columns of 10 probe pads. Of these, 163 macros were borrowedfrom existing BAE SYSTEMS‟ test structures and used to verify normal transistoroperation. There were 109 new macros designed to address the memory element features.These included sheet resistance and contact resistance measurement structures, discretememory elements of various sizes and configurations, and two 16-bit 1T1R memoryarrays.Short loop (partial flow) experiments were processed using subsets of the fullADTC mask set. These experiments were used to optimize the process steps used toconnect the bottom electrode of the memory element to underlying tungsten studs and toconnect an additional tungsten stud level between Metal 1 and the top electrode of thememory element. A full flow experiment was then processed to demonstrate integratedtransistors and memory elements.FIGURE 7.2 V-I CharacteristicsFigure 7.2 shows the V-I characteristic for a 1T1R memory cell successfullyfabricated using the ADTC vehicle. The voltage is applied to one of the two terminals ofthe chalcogenide resistor, and the access transistor (biased on) is between the otherresistor terminal and ground. The high resistance amorphous material shows very littlecurrent below a threshold voltage (VT) of 1.2V. In this same region the low resistancepolycrystalline material shows a significantly higher current. The state of the memory cell
Ovonic Unified MemoryDEPT. OF E & C., GECH. 2013 Page 28is read using the difference in V-I characteristics below VT. Above VT, both materialsdisplay identical V-I characteristics, with a dynamic resistance (RDYNAMIC) of ~1k. Initself, this transition to a low resistance electrical state does not change the structuralphase of the material. However, it does allow for heating of the material to program it tothe low resistance state (1) or the high resistance state (0). Extrapolation of the portion ofthe V-I curve that is above VT to the X-axis yields a point referred to as a holding voltage(VH). The applied voltage must be reduced below VH to exit the programming mode.FIGURE 7.3 R-I CharacteristicsFigure 7.3 shows the operation of a 1T1R memory, again with the accesstransistor biased on. The plotted resistance values were measured below VT, while thecurrent used to program these resistances was measured above VT. Similar to thepreviously demonstrated stand-alone memory elements, these devices requireapproximately 0.6 mA to set to the low resistance state (R SET) and 1.2 mA to reset tothe high resistance state (R RESET). The circuit was verified to be electrically open withthe access transistor biased off.
Ovonic Unified MemoryDEPT. OF E & C., GECH. 2013 Page 29FIGURE 7.4 Drain current v/s gate voltage plotFigure 7.4 shows the total dose (X-ray) response of N-channel transistorsprocessed through the chalcogenide memory flow. The small threshold voltage shift istypical of BAE SYSTEMS‟ standard radiation-hardened transistor processing. All othermeasured parameters (drive current, threshold voltage, electrical channel length, contactresistance, etc.) were also typical of product manufactured without the memory element.
Ovonic Unified MemoryDEPT. OF E & C., GECH. 2013 Page 30CHAPTER 8ADVANTAGES AND RISK FACTORS OF OUMAdvantages OUM uses a reversible structural phase change. Small active storage medium. Simple manufacturing process. Simple planar device structure. Low voltage single supply. Reduced assembly and test costs. Highly scalable- performance improves with scaling. Multistate are demonstrated. High temperature resistance. Easy integration with CMOS. It makes no effect on measured CMOS transistor parametric. Total dose response of the base technology is not affected.Risk factors Reset current < min W switch current. Standard CMOS process integration. Alloy optimization for robust high temp operation and speed. Cycle life endurance consistency. Endurance testing to 10 – DRAM. Defect density and failure mechanisms.
Ovonic Unified MemoryDEPT. OF E & C., GECH. 2013 Page 31CHAPTER 9ABOUT CHALCOGENIDE ALLOYChalcogenide or phase change alloys is a ternary system of Gallium, Antimonyand Tellurium. Chemically it is Ge2Sb2Te5.FIGURE 9.1 Ternary systemProduction Process: Powders for the phase change targets are produced by state-of –the art alloying through melting of the raw material and subsequent milling. Thisachieves the defined particle size distribution. Then powders are processed to discsthrough Hot Isotactic Pressing.9.1 Comparison of amorphous and crystalline stateAmorphous CrystallineShort range atomic order. Long range atomic order.Low free electron density. High free electron density.High activation energy. Low activation energy.High resistivity. Low resistivity.9.2 Test resultsTest results confirmed that the insertion of a chalcogenide manufacturing flow hadno effect on measured CMOS transistor parametric and did not change the total doseresponse of the base technology. Preliminary results on send-ahead package departsindicate full functionality of the 64 Kbit memory arrays. Further characterization of theADTC wafers and packaged devices from the CTCV wafers will include chalcogenide
Ovonic Unified MemoryDEPT. OF E & C., GECH. 2013 Page 32material-specific studies, such as write cycle endurance (a.k.a. “cycle life”), operating andstorage temperature effects and further radiation effects tests on packaged parts, toinclude total dose (60Co) and heavy ion exposure. Minimum write and read cycle timing,layout spacing evaluation, data pattern insensitivity and other design relatedcharacterization will be conducted to support product optimization.Companies working with Ovonic Unified Memory have their ultimate goal togather enough data to begin a product design targeting a 1–4 Mbit C-RAM device that islatch-up and SEU immune to greater than 120 LET and total dose hard to greater than 1Mrad (Si), operating across the full temperature range commonly specified for spaceapplications.
Ovonic Unified MemoryDEPT. OF E & C., GECH. 2013 Page 33CONCLUSIONUnlike conventional flash memory Ovonic unified memory can be randomlyaddressed. OUM cell can be written 10 trillion times when compared with conventionalflash memory. The computers using OUM would not be subjected to critical data losswhen the system hangs up or when power is abruptly lost as are present day computersusing DRAM a/o SRAM. OUM requires fewer steps in an IC manufacturing processresulting in reduced cycle times, fewer defects, and greater manufacturing flexibility.These properties essentially make OUM an ideal commercial memory. Currentcommercial technologies do not satisfy the density, radiation tolerance, or endurancerequirements for space applications. OUM technology offers great potential for lowpower operation and radiation tolerance, which assures its compatibility in spaceapplications. OUM has direct applications in all products presently using solid statememory, including computers, cell phones, graphics-3D rendering, GPS, videoconferencing, multi-media, Internet networking and interfacing, digital TV, telecom,PDA, digital voice recorders, modems, DVD, networking (ATM), Ethernet, and pagers.OUM offers a way to realize full system-on-a-chip capability through integrating unifiedmemory, linear, and logic on the same silicon chip.Non-volatile OUM with fast read and write speeds, high endurance, lowvoltage/low energy operation, ease of integration and competitive cost structure issuitable for ultra-high density, stand alone and embedded memory applications. Theseattributes make OUM an attractive alternative to flash memory technology and potentiallycompetitive with volatile memory technologies.
Ovonic Unified MemoryDEPT. OF E & C., GECH. 2013 Page 34REFERENCESText books1) OUM - a 180 nm nonvolatile memory cell element technology for standalone andembedded applications - Stefan Lai and Tyler Lowrey.2) Current status of the phase change memory and its future (2003) – Stefan Lai.3) Ovonic unified memory - a high-performance nonvolatile memory technology forstand-alone memory and embedded applications (0)by M Gill, T Lowrey, J Park.Website links1) http://en.wikipedia.org/wiki/Ovonic_Unified_Memory2) http://ovonicunifiedmemory.blogspot.in/3) http://www.studentsphere.co/index.php/technical-articles/computers-it/90-tet4) http://www.techopedia.com/definition/2797/phase-change-memory-pcm5) http://maltiel-consulting.com/Nonvolatile_Phase_Change_Memory.htm