A 500-MHz Low-Voltage Programmable Gain Ampliﬁer for HD Video in 65-nm CMOS Syed Ahmed Aamir and J Jacob Wikner Department of Electrical Engineering Link¨ ping University o SE-581 83 Link¨ ping, Sweden o E-mails: firstname.lastname@example.org, Jacob.Wikner@liu.se Abstract—This work describes the implementation of a 1.2- identical brightness levels across each horizontal line drawnV programmable gain ampliﬁer (PGA) for high-deﬁnition (HD) on the screen.video digitizers in a 65-nm digital CMOS process. The “pseudo” switched-capacitor (SC) PGA architecturebuffers the video signal, without switching, during the activevideo. The SC circuitry is used for setup of DC operating pointduring horizontal and vertical blanking periods. Additionally,it compensates for the ’sync-tip’ of analog video signals to anequal blanking level for increased dynamic range to the digitizerfollowing the PGA. The operational transconductance ampliﬁer (OTA) employedas main ampliﬁer in the PGA is a pseudo-differential, positive-feedback input stage architecture with a common-mode feedfor-ward (CMFF) technique. The common-mode feedback (CMFB)is provided once two OTAs are cascaded. Schematic-level simulation results show that the OTA main-tains a −3-dB bandwidth of 550 MHz, while keeping thedistortion HD3 at –60 dB for a 30-MHz, 850 mVpp high deﬁnitionvideo signal. The 88 dB DC gain is distributed among fourOTA stages and the overall, combined PGA achieves a signal-to-noise ratio of 63 dB. Due to only two stacked transistors, itachieves high output swing of ±0.85 V, 1240 V/µs slew rate whileconsuming 10.4 mW power. Fig. 1. A video analog front-end (AFE) showing the interfacing circuits. Index Terms—CMOS analog integrated circuits, switchedcapacitor circuits, programmable gain ampliﬁers, feedforwardampliﬁers, operational ampliﬁers In this work we propose a programmable gain ampliﬁer (PGA) for such high deﬁnition video analog front-ends. We I. I NTRODUCTION have aimed the integration of AFE in a system-on-chip (SOC) environment and have therefore explored a low-voltage imple- The rapidly growing trends of home entertainment video in- mentation in a 65-nm digital CMOS process.dustry has pushed the traditional video screens to deliver more Notice that the high-deﬁnition video and graphics stan-detailed, high resolution and sharper pictures. With the advent dards have a high signal bandwidth. Signal frequencies upof high deﬁnition progressive scanning (e.g. HDTV 1080p), to 30 MHz must be multiplexed, buffered and digitized withvideo technology is bounded by stringent speciﬁcations, and high linearity maintained throughout the AFE. To preventany design lapse is more ”visible” than ever. The video analog other types of artifacts from appearing on the high-resolutionfrontends have faced its direct impact, which coupled with picture screen, a bandwidth up to 20 times higher is required.lower supplies and scaled sub-micron digital processes, make For the high-resolution graphics formats the bandwidth needsthe design more challenging. to be beyond 500 MHz. This type of bandwidth puts high A typical modern video analog front-end (AFE) receiver requirements on the open-loop unity-gain bandwidth of thechain is outlined in Fig. 1 (digital parts omitted). An AC PGA. These speciﬁcations are considerably more challengingcoupled video signal which is multiplexed and selected from compared to previously reported video PGAs such as .a set of different input sources (there could be many video An example of an analog video signal waveform is shownsources connected to the same TV set) is buffered. Inside the in Fig. 2. The active video region contains the vital pictureAC capacitor there is no connection to ground, i.e., no leakage. information, whereas the blanking intervals synchronize dur-The signal is possibly ampliﬁed or attenuated by the PGA to ing the minimal black-time between successive frames andadjust the levels to ﬁt the digitizing ADC range. The signal horizontal lines. The blanking period typically contains aleakage is prevented or restored by a clamp circuit, ensuring −40 IRE sync-tip, followed by a color burst (dependent on978-1-4244-8971-8/10$26.00 c 2010 IEEE
video formats) which provide amplitude, phase reference foreach color. Traditionally, the clamping occurs during the back-porch duration. Fig. 2. A typical analog video waveform. Fig. 3. The proposed video PGA including DC conditioning SC input. In Section II we outline the PGA architecture and itsimplementation for a video digitizing AFE to be used in SOCs. B. Gain SettingsIn Section III the low-voltage OTA architecture is presented The gain settings are achieved by means of capacitorand discussed. Simulation results are given in Section IV and ratios, and for the input video signals we have provided twoﬁnally the paper is concluded in Section V. gain settings: 0.5 and 1. Capacitor Cin is then changed to accomplish this programmable gain. II. P ROPOSED V IDEO PGA C IRCUIT It should be mentioned that some lower voltage swing video The proposed video programmable gain ampliﬁer (PGA) formats may require higher gain settings (2 times) to enable ais realized as a fully-differential, ”pseudo” switched-capacitor more efﬁcient utilization of the ADC. However, this increases(SC) circuit that gets the multiplexed, clamped and band- the capacitive load on the PGA and the signal, thus decreasinglimited video signal from the ﬁrst parts of the AFE. the system bandwidth. Such video formats, however, have One has to consider a couple of points before outlining a bandwidth requirements much lower than 500 MHz too, andvideo PGA using an SC technique, mainly: would not really suffer from the impact of lower bandwidth. • The circuit must not switch during the active video The next section describes a four-stage, low-voltage pseudo- duration of the analog video signal, to preserve a higher differential OTA architecture that is used in the PGA circuit. signal linearity. • In order to increase the signal dynamic range, the PGA III. P SEUDO -D IFFERENTIAL OTA A RCHITECTURE compensates for the sync-tip of analog video waveform, Various designs of low-voltage OTAs have been proposed in presenting the ADC a sync-tip free signal. the literature, including for example –. We have explored a pseudo-differential design, which eliminates the tail currentA. ”Pseudo” SC Circuit with Sync-Tip Compensation source in the input differential pair and becomes particularly With the above considerations, we propose an SC architec- suited for low voltage design. One pseudo-differential OTAture where charge is transferred between the nodes during the with a CMFF strategy is presented in –. These designssync-tip duration only, which means the non-overlapping clock were originally implemented in a 0.5-μm CMOS process andgenerator does not function beyond the sync-tip duration. In for higher supply voltage. We wanted to explore the design inthe absence of a sync-tip, i.e., during active video, the PGA a more modern SOC environment such as a 65-nm process.acts like a capacitive buffer. However, porting of the originally proposed architecture to Additionally, we exploit the fact, that most often the real a (relatively) much smaller dimension does have problems.input video signal is single ended, and the second input of the These problems are foremost due to the low-gain devicesPGA is referenced from an on-chip, programmable digital-to- available among the core devices in an SOC process.analog converter (DAC). We utilize this reference DAC voltage Thus the PGA in our work is realized using a modiﬁed OTAto level-shift the sync-tip duration of video signal, effectively architecture, which has a positive feedback pseudo-differentialcanceling the sync-tip, and obtaining a clean output signal. input stage for higher gain, but additionally for achieving the The resulting SC architecture is shown in Fig. 3. Notice higher targeted video bandwidth, linearity, etc. The pseudo-that the ﬁrst two switches triggered by presence or absence differential OTA architecture with its inherent common-modeof sync-tip, provide separate reference DC levels Vsync and feedforward also provides efﬁcient common-mode feedbackVCM . Vsync is then the sync-tip voltage level (≈ −0.3 V (CMFB), when a similar OTA is cascaded! This saves usor −40 IRE) and VCM is the input common-mode level. an additional CMFB block as proposed in  and shown inThis level is maintained in accordance with the input signal Fig. 4. The second stage OTA provides the ﬁrst stage withbrightness. a common-mode feedback signal. Instead of using a separate
transconductance for common-mode detection as in , , The two most dominant poles found in the OTA stage arethe OTA utilizes the differential transconductance to detect the given byinput common-mode level too. gm5 − (gds1 + gds2 + gds5 + gm2 ) ωp1 = , Cz and gds3 + gds4 ωp2 = , CL where Cz is the parasitic capacitance at the output of the input differential pair (also illustrated in Fig. 5) and CL is the load capacitance at output node creating the most dominant pole. Fig. 4. The cascaded OTA blocks to provide CMFB. B. CMFB Detection As mentioned above, the common-mode component is ex- The positive-feedback OTA with its CMFF is shown tracted in the Vcm node of the OTA (see Fig. 5). In a multi-in Fig. 5. The individual input stage currents are further stage OTA conﬁguration, this Vcm voltage inside any OTA iscopied using a differential transconductance to detect the the sensed output common-mode level of the preceding OTA.common-mode component in the OTA node Vcm . The detected Exploiting this property, one can provide CMFB as long ascommon-mode current, (I1 + I2 )/2, is then subtracted at at least two OTAs are used in the chain (see Fig. 4). Thethe output performing the feedforward cancellation. Due to ﬁrst OTA adds an additional set of devices in parallel to thesimilar differential-mode and common-mode signal paths the biasing PMOS of the output stage, which are controlled by thebandwidths for both loops can be made fairly identical. fed back Vcm , and shown in Fig. 6 as VcmN ext . A common- mode reference current is further mirrored in the output stage, which then adjusts output DC point to its optimum level by comparing the currents.Fig. 5. The positive feedback pseudo-differential OTA with inherent Fig. 6. One half of the pseudo-differential architecture with CMFF andcommon-mode feedforward. CMFB.A. OTA Parameters C. Nonlinearity To further describe the OTA design, some of the important Since the pseudo-differential input pairs remove the taildesign parameters are presented in this section. The DC gain current source, the ampliﬁer will be more sensitive towardsADC of the positive feedback input stage OTA is: mismatch variations. This implies that the second-order har- gm1 gm4 monic distortion (HD2 ) will be larger than for a differential ADC = , input pair with tail current source. Cross coupling between (gm5 − (gm2 + gds1 + gds2 + gds5 ))(gds3 + gds4 ) gm1 gm4 differential signal and any common-mode interferer also con- ≈ , tributes to HD2 components. HD3 is contributed by short (gm5 − gm2 )(gds3 + gds4 ) channel effects, as well as due to non-linear interaction ofwhere gmi is the transconductance of transistor Mi and gdsi differential OTA outputs and CMFB. A more detailed analysisis the output conductance (or channel length modulation) of of sources of non-linearity in pseudo-differential designs istransistor Mi . presented in .
Parameter    This workD. Noise and SNR Process (nm) 90 350 90 65 Considering only transistor thermal noise, the input referred Supply (V) 1.2 1.8 2.5 1.2 2 DC gain (dB) 40 12 45 88*noise power density, Pn = Vn−rms , of the positive feedback f3dB (MHz) 240 400 500 550OTA architecture (omitting the common-mode noise contrib- Input Referred Noise 4.6 15 5.7 12.6 √utors M6 , M7 , see Fig. 5) becomes: (nV/ Hz) @40 dB @0 dB @88 dB THD −30 −40 - −6016kT · BW E 2gm3 E + 2gm4 E + gm5 E HD3 (dB) @80 MHz @0.8Vpp @30 MHz · 1+ + 2 , 3gm1 gm2 gm1 gm1 gm4 Power (mW) 3.48 2.1 32.5 10.4 TABLE IIwhere BW is the equivalent noise bandwidth. E is a factor C OMPARISON OF RECENT PGA S (* OPEN - LOOP GAIN ).given by E = (gm2 − gm5 )2 and once E ≈ 0, i.e., thetransconductance of the mirror transistors is approximatelyequal to that of positive feedback transistors, the signal-to-noise ratio (SNR) at the input becomes: V. C ONCLUSION 2 3gm1 HD3 Vef f (1 + θ Vef f ) (2 + θ Vef f ) We have described a programmable gain ampliﬁer archi-SNR ≈ 10 · log10 [ ] 2kT · BW tecture for high deﬁnition video standards that provides sync-It can be noted that the positive feedback architecture clearly tip compensation using SC techniques. We maintained a low-achieves a better SNR than the one derived originally in . voltage implementation in a modern short channel process to attain the challenging speciﬁcations of targeted video stan- IV. S IMULATION R ESULTS dards. The novel pseudo-differential multi-stage OTA archi- Table I compiles the simulation results for the PGA/OTA tecture with CMFB was enhanced to provide higher gain andand in Table II the results are compared to other reported bandwidth, wider output swing and low distortion, to processresults. the video signals for best visual performance. In Fig. 7 we show the simulated transient response for an R EFERENCESactive video line. The upper graph shows the input signal  G. Xu and H. Bilhan, “A programmable gain ampliﬁer buffer design forwith embedded sync-tip. The lower graph shows the PGA video applications,” in Proc. IEEE Symp. Circuits Syst., 2004, vol. I,output where the sync-tip can be removed by the SC circuitry pp. 557–560.during horizontal blanking. The oscillations we see during the  G. Ferri and W. Sansen, “A rail-to-rail constant-gm low-voltage CMOS operational transconductance ampliﬁer,” IEEE J. Solid-State Circuits,blanking interval are given by the SC clock phases. vol. 32, no. 10, 1997.  J.M. Carrillo, G. Torelli, R. P´ rez-Aloe, and J.F. Duque-Carrillo, “1-V e Parameter Value Parameter Value rail-to-rail CMOS opamp with improved bulk-driven input stage,” IEEE Supply voltage 1.2 V DC gain 88 dB J. Solid-State Circuits, vol. 42, no. 3, 2007. Process node 65 nm f3dB 550 MHz  S. Chatterjee, Y. Tsividis, and P. Kinget, “0.5-V analog circuit techniques Phase margin 45◦ HD2 –118 dB and their application in OTA and ﬁlter design,” IEEE J. Solid-State Slew rate 1240 V/µs HD3 –60 dB Circuits, vol. 40, no. 12, 2005. Output swing 850 mVpp SNR 63 dB  A.N. Mohieldin, E. S´ nchez-Sinencio, and J. Silva-Mart´nez, “A fully a ı Power 10.4 mW balanced pseudo-differential OTA with common-mode feedforward and inherent common-mode feedback detector,” IEEE J. Solid State Circuits, TABLE I vol. 38, pp. 663–668, April 2003. S IMULATION RESULTS OF MODIFIED OTA.  A.N. Mohieldin, E. S´ nchez-Sinencio, and J. Silva-Mart´nez, “A a ı low-voltage fully balanced OTA with common-mode feedforward and inherent common-mode feedback detector,” in Proc. IEEE European Solid-State Circuits Conf. (ESSCIRC)., 2002, vol. I, pp. 191–194. videoSignal  A.N. Mohieldin, E. S´ nchez-Sinencio, and J. Silva-Mart´nez, “Nonlinear a ı 750.0 effects in pseudo differential OTAs with CMFB,” IEEE Trans. Circuits 500.0 Syst. II, vol. 50, pp. 296–301, Oct. 2003.  F. Rezzi, A. Baschirotto, and R. Castello, “A 3-V 12-55-MHz BiCMOS V (mV) 250.0 pseudo-differential continous-time ﬁlter,” IEEE Trans. Circuits Syst. I, 0 vol. 42, pp. 896–903, Nov. 1995.  A. Shankar, J. Silva-Mart´nez, and E. S´ nchez-Sinencio, “A low voltage ı a −250.0 operational transconductance ampliﬁer using common mode feedforward Sync Tip Sync Tip Sync Tip Tip vOutDiff for high frequency switched capacitor circuits,” in Proc. IEEE Symp. 500 Circuits Syst., 2001, vol. I, pp. 643–646.  S. D’Amico, A. Baschirotto, K. Philips, O. Rousseaux, and B. Gy- 250 selinckx, “A 240MHz programmable gain ampliﬁer & ﬁlter for ultra V (mV) 0 low power low-rate UWB receivers,” in Proc. IEEE European Solid- State Circuits Conf. (ESSCIRC)., 2009, pp. 260–263. −250  B. Calvo, S. Celma, J.P. Alegre, and M.T. Sanz, “A 1.8-V 400 MHz −500 programmable gain ampliﬁer in 0.35µm CMOS,” in Proc. 50th Midwest Symp. Circuits Syst., 2007, vol. I, pp. 257–260. 0 10 20 30 40 50 60 70 80 time (us)  T.H. Teo, M.A. Arasu, W.G. Yeoh, M. Itoh, and B. Gyselinckx, “A 90nmFig. 7. An input video signal and its corresponding sync-tip compensated CMOS variable-gain ampliﬁer and RSSI design for wide-band wirelessoutput, for a unity gain PGA setting. network application,” in Proc. IEEE European Solid-State Circuits Conf. (ESSCIRC)., 2006, pp. 86–89.