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Calibration of ΣΔ Analog-to-Digital Converters Based on Histogram Test Methods A. Jalili and S.M. Sayedi J.J. Wikner, N.U. Andersson, and M. Vesterbacka ECE Department Department of Electrical Engineering, Isfahan University of Technology Link¨ ping University, o 84156-83111 Isfahan, Iran SE-581 83 Link¨ ping, Sweden o Abstract—In this paper we present a calibration technique for In this work, a calibration technique for subADCs insigma-delta analog-to-digital converters (ΣΔADC) in which high- ΣΔADCs is proposed, then this technique is extended to alsospeed, low-resolution ﬂash subADCs are used. The calibration cover the imperfections of other building blocks, includingtechnique as such is mainly targeting calibration of the ﬂashsubADC, but we also study how the correction depends on where DAC and accumulator. The technique employs so calledin the ΣΔ modulator the calibration signals are applied. histogram test methods [1]–[7] that are used to calibrate the It is shown that the calibration technique can cope with errors converter. In these histogram-based methods an analog signalthat occur in the feedback digital-to-analog converter (DAC) and with a known probability density function (PDF) is applied tothe input accumulator. the input of the converter and then the number occurrences Behavioral-level simulation results show an improvement of ineffective number of bits (ENOB) from 6.6 to 11.3. Fairly large of a certain digital output code is recorded. The result, i.e.,offset and gain errors have been introduced which illustrates a the code density, is used to compute all bit transition levelsrobust calibration technique. [2]. Linearity, gain and offset errors can be calculated and Index Terms—Calibration, Comparator, Flash ADC, His- corrected for through these estimated transition levels.togram based test methods, sigma-delta modulators. I. I NTRODUCTION Sigma-delta analog-to-digital converters, ΣΔADCs, are typ-ically used in situtations where the input signal bandwidthis small compared to the available sample frequency. Fig. 1shows a block diagram of a ﬁrst-order ΣΔADC including itsbuilding blocks such as the ﬂash analog-to-digital converter Fig. 1. A ﬁrst-order ΣΔADC with output decimator omitted.(subADC), feedback digital-to-analog converter (DAC) andaccumulator. The advantage with the ΣΔ approach is thatthe subADC inside the modulator can be implemented with II. S TATIC E RROR M ODELSa lower physical number of bits. For an (ideal) Lth-order ΣΔ A block diagram of a 4-bit ﬂash ADC is shown in Fig. 2 (a).modulator employing an M -bit subADC the achievable in- The structure contains 24 − 1 = 15 voltage reference levelsband signal-to-noise ratio (SNR) in dB is approximately generated by a resistor ladder. There is one comparator for π 2L+1 each reference level, and the array of comparators compares SNR ≈ 6.02 · M + 1.76 − 10 · log10 + the input signal with the reference voltages and generates a 2L + 1 fs thermometer code at its output. A decoder is used to generate a + (20L + 10) · log10 dB, more convenient representation, e.g., binary code, at the output 2fB of the converter. The static errors affect the accuracy in thewhere fs is the sample frequency and 2fB is the signal decision levels of the converter. Errors in the reference levelsbandwidth. By choosing the sample frequency and modulator are mainly caused by the resistor mismatch and offsets in theorder we can reach a high SNR, i.e., effective resolution. For comparators that can be model by a voltage source Vos of eachexample, with M = 4, L = 1, and an oversampling ratio of comparator as shown in Fig. 2 (b).fs /2fB = 64 we can achieve SNR ≈ 70 dB correspondingto 11 effective number of bits, ENOB = (SNR − 1.76)/6.02. III. P ROPOSED CALIBRATION METHODCrudely, we can state that an 11-bit converter can be imple- In order to deal with different error sources in the ΣΔADC,mented using a 4-bit converter running at higher speed. The we need to employ a calibration approach with minimumsubADC can then be, for example, implemented using a high- circuit topology dependence. Many of previously reportedspeed architecture like the ﬂash ADC, which normally would calibration techniques of ﬂash ADCs [8]–[12], need to imposenot be applicable for an 11-bit converter due to increase in some changes to the ADC structure and especially comparatorshardware cost as function of number of bits. to perform calibration. This means that the calibration path978-1-4244-8971-8/10$26.00 c 2010 IEEE
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Fig. 3. The employed histogram-based calibration method in a ﬁrst-order ΣΔADC. other offset values. If the PDF generator circuit generates a signal with a uni-Fig. 2. (a) Block diagram of a 4-bit ﬂash converter. (b) Modeling of the form distribution, e.g., a ramp signal, in the range [−VR , VR ],static errors as a voltage source Vos . we have for an ideal 4-bit converter and for every N input samples: Ni = N/16, for i = 1, 2, . . . , 16 (2)will be conﬁned to the ﬂash subADC only and it is therebydifﬁcult to extend the calibration method towards the entire and for a 4-bit non-ideal converter for interval Ii (Fig. 4(b)ΣΔADC. However, the histogram based technique is a proper for uniform PDF) we have:candidate. ˜ 2VR /16 − Vos,i + Vos,i−1 The employed method in a ﬁrst-order ΣΔADC is shown Ni = · N. (3) 2VRschematically in Fig. 3. fin (x) and fout (x) are the PDF’s of Rearranging (3) results inthe input and output signals of the subADC, respectively. Volt-age VR is the reference voltage such that −VR < Vin < VR . ˜ Vos,i = Vos,i−1 − 2VR · Ni − Ni /N. (4)During calibration mode, the output of the PDF generator is Equation (4) is a recursive relationship that can be used inconnected to the input of the ﬂash ADC. The PDF generator the estimation of the offset values. Vos,0 = Vos,16 = 0, so forproduces an analog signal with a known PDF, fin (x). In comparators number 1 and 15, eq. (4) results inpractice, due to the static errors, the input and output PDFs,fin (x) and fout (x), are not identical, and in the histogram- ˜ Vos,1 = −2VR · (N1 /N − 1/16) (5)based techniques, the differences are used to extract thesubADC errors. and ˜ Vos,15 = 2VR · (N16 /N − 1/16), (6) In an ideal converter, with zero error sources, interval i isdeﬁned as respectively. Equations (5) and (6) provide two initial condi- Ii : x ∈ [Vr,i−1 , Vr,i ], (1) tions for the recursive expression in (4). One of the conditions is sufﬁcient for the calculations; however, in order to avoidwhere Vr,0 = −VR , and Vr,16 = +VR . In practice, these large additive errors during error estimation, offset errorsintervals are changed due to the static error sources. related to comparators number 2 to 7 are estimated by using If, within a certain period of time, N input samples in initial condition (5) and offset errors related to comparatorsthe range [−VR , VR ] are applied to the ADC, the samples number 8 to 14 are estimated by using initial condition (6).would ideally be allocated to the intervals Ii identical to the In the case of large offset values, as shown in Fig. 4 (d), it isvalues of the input PDF. In a non-ideal case the numbers possible that the reference levels cross each other. In this case,differ from the ideal ones due to static error sources. The interval Ii disappears and a new interval is created. To extenddifference between the wanted number of samples, Ni and ˜the measured Ni can be used to estimate the error values.Fig. 4 clariﬁes what happens to the different intervals, Ii ,when we go from an ideal converter to a converter with staticerrors in the reference levels. In Fig. 4 (a) we ﬁnd the idealcase. Ni out of N recorded samples belong to interval Ii .Fig. 4 (b) then shows how the intervals will shift and alsocontain a different number of samples, for example interval ˜Ii will now contain Ni samples (with ∼ denoting the non-ideal case). The difference between the wanted Ni and the ˜measured Ni can be used to estimate the error values. Fig. 4(c)illustrates the boundary intervals of the PDF which are used Fig. 4. The number of samples in (a) interval Ii in an ideal converter, (b)to estimate the offset of ﬁrst and last comparators in the array. interval Ii in a non-ideal converter, (c) intervals I1 and I16 in a non-idealThese offsets are used as initial conditions to calculate the converter, (d) overlap of the reference levels due to large error values.
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the estimation process towards such a condition, (4) can bemodiﬁed as follows: ˜ Vos,i = Vos,i−1 + 2VR · Ni + Ni /N. (7)In case of an overlap, (7) must be used instead of (4). Thetrimming process, i.e., the compensation of the estimated errorvalues merged in the comparator offset, can be done in variousways [8], [9], [11]. In this work, an original trimming scheme,reported in [8], is used where the offset of comparators iscompensated for by adjusting the reference voltages switchedin from the resistor ladder. So, after calibration of the ﬂashsubADC, we have an accurate ADC, where the accuracy ofthe calibration will depend on the trimming procedure andcalibration time. Disregarding that for now, the subADC canbe used to calibrate other error sources in the structure of theΣΔADC. Fig. 5. Suggested calibration of the DAC using the already calibrated ﬂash subADC.A. Extending Towards DAC Errors The output of an ideal binary coded 4-bit DAC can statically remain in their positions. In this case, the estimated offset ofbe expressed as: comparator 2 is 4 Vos,2 = γDAC,2 · VLSB + δDAC , (11) VDAC = −VR + VLSB · Di · 2i−1 , (8) i=1 where γDAC,2 is the second LSB gain error of the DAC.where Di ∈ {0, 1} are the input digital bits, VR is the reference Continuing this approach, the offsets of comparators 4, 8, andvoltage considering the signal range equal to [−VR , VR ] and 3 result in:VLSB = 2VR /16 is the quantization step. In practice, the output Vos,4 = γDAC,3 · VLSB + δDAC , (12)of the DAC deviates from its ideal value given in (8) according Vos,8 = γDAC,4 · VLSB + δDAC , (13)to the offset and gain errors as: 4 and i−1 Vos,3 = (γDAC,1 + γDAC,2 ) · VLSB + δDAC , (14) VDAC = δDAC − VR + VLSB · Di · (2 + γDAC,i ), (9) i=1 where δDAC,3 and δDAC,4 are the second MSB and MSB gainwhere δDAC and γDAC,i for i = 1, 2, 3, 4 are the offset and gain errors of the DAC, respectively. Subtracting (14) from the sumerrors of the DAC, respectively. In order to estimate the error of (10) and (11) results invalues of the DAC, its output is directly fed to the input of δDAC = Vos,1 + Vos,2 − Vos,3 . (15)the subADC. In this case, the corresponding estimated offsetvalue is the error (gain and offset) of the DAC. The concept After estimation of the DAC offset according to (15), the DACis shown schematically in Fig. 5 for a binary weighted DAC. gain errors can be calculated using (10) to (13). The DAC canFive comparators numbered 1, 2, 3, 4, and 8 are chosen from be trimmed using for example a subDAC and/or some digitalthe bank of the comparators and their threshold voltages can be predistortion techniques.generated either from the reference ladder or the DAC. For a B. Extending Towards Accumulator Errorthermometer-coded DAC, we would require more comparatorsto be used. During calibraton of the DAC, each time one After calibration of the DAC, the only remaining uncali-of the threshold voltages of the mentioned comparators are brated block is the accumulator (including its summation ofgenerated by the DAC and through this the equivalent DAC DAC and input signals). In order to perform calibration forerrors can be estimated in terms of offset of these comparators. this block, the input test signal is applied at the input of theThe calibration phase of the DAC is as follows: First, the DAC ΣΔADC. Fig. 6 shows this concept. If the PDF generator,input word, {D4 , D3 , D2 , D1 } is set to 0001 and switch S1 generates a signal with uniform distribution in the voltageis put in position 2. The other switches (S2 to S5 ) remain in range [−VR , VR ], at the input of the ΣΔADC, a close-to-their default position 1. In this case, the estimated offset of uniform distribution is obtained except that the boundariescomparator 1 is: close to −VR and VR , as illustrated in Fig. 6, are attenuated. The same formulas given for a uniform distribution can be Vos,1 = γDAC,1 · VLSB + δDAC , (10) used but with minor modiﬁcations. The terms γacc and δacc are the accumulator gain and offset errors, respectively. In thiswhere γDAC,1 is the LSB gain error of the DAC. Now the case, the estimated offset values of the ﬂash subADC result ininput {D4 , D3 , D2 , D1 } is set to 0010, switch S1 is put backto position 1 and S2 is put in position 2. The other switches Vos,i = γacc · Vr,i + δacc , (16)
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After calibration 12 Before calibration 10 ENOB (bit) 8 6 4 0 10 20 30 40 50 60 70 80 90 100 Simulation indexFig. 6. Calibration of the accumulator gain error by applying the test signalat the input of the ΣΔADC. Fig. 8. ENOB of the ﬁrst-order ΣΔADC before ( ) and after ( ) applying the proposed calibration technique.where γacc is the accumulator gain error δacc is the accumulatoroffset error and Vr,i is the reference voltage of the ith com- V. C ONCLUSIONSparator. Equation (16) can be used to estimate the accumulator In this paper, we have extended an ADC calibration method-gain error as: ology, previously employed for Nyquist-rate ﬂash ADCs, to γacc = Vos,9 − Vos,7 / Vr,9 − Vr,7 . (17) also cover calibration of ΣΔADCs. The calibration method, using histogram-based methods, was extended to also caterAfter calibration of accumulator gain error, the offset error can and correct for errors in the feedback DAC and input accu-be calculated on average as: mulators of the ΣΔADC. The algorithms and test circuitry 15 were implemented on a behavioral-level in MATLAB and 1 δacc = Vos,i . (18) simulation results of a ﬁrst-order ΣΔADC showed that nearly 15 i=1 full performance could be obtained after calibration. IV. S IMULATION R ESULTS The ΣΔADC of Fig. 1 is modeled behaviorally with a4-bit ﬂash subADC and DAC converters. The test setup isshown in Fig. 7 where we have also included the decimation R EFERENCESﬁlter. As can be seen, the test signal, i.e., the output of the [1] F.H. Irons J. Larrabee and D.M. Hummels, “Using sine wave histogramsPDF generator is applied to the structure from two different to estimate analog-to-digital converter dynamic error functions,” IEEEpoints, A and B. At each point, an analog multiplexer (MUX) Trans. Instrumentation and Measurement, vol. 47, pp. 1448–1456, 1998. [2] H.-S. Lee J. Doernberg and D.A. Hodges, “Full-speed testing of A/Dis placed and they are controlled by two calibration signals, converters,” IEEE J. Solid-State Circuits, vol. 19, pp. 820–827, DecCal A and Cal B. When the test signal is injected from point 1984.A, the ﬂash subADC and the DAC are calibrated. When it [3] Y. Betrand F. Azais, S. Bernard and M. Renovell, “Towards an ADC BIST scheme using the histogram test technique,” in IEEE Proc.is applied from point B, the accumulator is also included in European Test Workshop, May 2000, pp. 53–58.calibration path and possible errors are calibrated for. [4] U. Eduri and F. Maloberti, “Online calibration of a Nyquist-rate analog- to-digital converter using output code-density histograms,” IEEE Trans. Circuits and Systems I, vol. 51, pp. 15–24, Jan 2004. [5] Degang Chen Xin Dai and R. Geiger, “A cost-effective histogram test-based algorithm for digital calibration of high-precision pipelined ADCs,” in IEEE Intern’l Symp. on Circuits and Systems, May 2005, pp. 4831–4834. [6] Degang Chen Le Jin and R. Geiger, “A digital self-calibration algorithm for ADCs based on histogram test using low-linearity input signals,” in IEEE Intern’l Symp. on Circuits and Systems, May 2005, pp. 1378–1381.Fig. 7. Test setup for veriﬁcation of the proposed calibration technique in a [7] J. Elbornsson and J.-E. Eklund, “Histogram based correction ofﬁrst-order ΣΔADC. matching errors in subranged ADC,” in Proc. of the 27th European Solid-State Circuits Conference 2001. ESSCIRC 2001, 2001, pp. 555– 558. In the tests, random errors with Gaussian distribution were [8] Chun-Ying Chen; M. Q. Le and Kwang Young Kim, “A low powerused. For the subADC comparators the standard deviation 6-bit ﬂash ADC with reference voltage and common-mode calibration,”was σos ≈ 80 mV. For the DAC, it was σγ,DAC = 5% and IEEE J. Solid-State Circuits, vol. 44, pp. 1041–1046, April 2009. [9] H. Yu and M.-C. F. Chang, “A 1-V 1.25-GS/s 8-bit self-calibrated ﬂashσδ,DAC = 60 mV for the gain and offset errors, respectively. ADC in 90-nm digital CMOS,” IEEE Trans. Circuits and Systems II,For the accumulator a gain error with σγ,acc = 3% and offset vol. 55, pp. 668–672, July 2008.error with σδ,acc = 10mV was used. Fairly large values were [10] A. Lachhwani V. Srinivas, S. Pavan and N. Sasidhar, “A distortion compensating ﬂash analog-to-digital conversion technique,” IEEE J.selected to prove the concept of the calibration routines. Fig. 8 Solid-State Circuits, vol. 41, pp. 1959–1969, Sept 2006.shows the simulation results before ( ) and after ( ) the [11] C.-W. Lin Y.-Z. Lin and S.-J. Chang, “A 5-bit 3.2-GS/s ﬂash ADCproposed calibration process was applied. The results show with a digital offset calibration scheme,” IEEE Trans. Very Large Scale Integration (VLSI) Systems, 2009.the reported ENOB for 100 Monte-Carlo runs. As can be seen, [12] Jin Liu Junjie Yao and Hoi Lee, “Bulk voltage trimming offsetfor about 94 % of the simulations nearly full performance is calibration for high-speed ﬂash ADCs,” IEEE Trans. Circuits andachieved after applying the proposed calibration technique. Systems II, vol. 57, pp. 110–114, Feb 2010.
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