LOW POWER AND OPTIMAL DELAY MULTI THRESHOLD VOLTAGE LEVEL CONVERTERS Abstract: directly driven by the low voltage level signal Minimizing power consumption without provided by the driver. The operation of the pull-up compromising speed in any integrated circuit (IC) transistors is controlled by an internal feedback is a challenge. Employing multiple supply mechanism isolated from the low voltage swing voltages (multi-Vdd) is an effective technique to input signal, thereby avoiding the formation of achieve this. In order to minimize the power static dc current paths within the circuit. dissipation in an integrated circuit, voltage level (a.i) Feedback Level converter: converter circuits are required. There are two novel multi-threshold voltage (multi-Vth) based level converters are proposed. When these novel level converters are applied in an integrated circuit and compared with the previous level converter which are of feed back based circuit. The power dissipation is decreased in this approach up to 47% and the Delay is optimized by 50% with multi threshold based level converter in a 0.18- µm technology. Index: multi-threshold, level converters, power dissipation I. Introduction Power dissipation reduction in an Figure 1: Feedback level converter integrated circuit (ICs) is the most demanding issue for present chip-design. When a low voltage level The feedback-based level converter is shown in signal directly drives a gate that is connected to a Figure 1: transistor M1 and M2 experience a low higher supply voltage, the pull-up network of the gate overdrive voltage (VDDL-VTH) during the receiver cannot be fully turned off. A receiver operation of the circuit. Transistor M1 and M2 need driven by a low voltage level signal therefore to be sized larger to produce more current as produces static dc current. In order to suppress this compared to the transistor M 3 and M4 , dc current, specialized voltage level converter respectively. When the input is at 0 V is turned off. circuits are employed between a low voltage driver Node1 is charged to VDDL.M1 is turned on. Node 3 is and a full voltage level receiver. The main cause discharged to 0 V turning M4 on. Node2 is charged for static power dissipation is due to low level to turning M3 off. The output is pulled down to 0 signal the voltage level converter circuits are V. When the input transitions to VDDL, M2 is turned inserted in critical region of integrated circuit to on. Node1 is discharged, turning M1 off. Node2 is converter the low level signal to high level signal discharged, turning M3on. Node3 is charged up to which is the main cause for power dissipation, VDDH turning M4 off. The output transitions to previously level converters are of feed back based VDDH. A feedback loop, isolated from the input, which rely on some feed back circuit for controls the operation of M3 and M4 during both controlling the operation of pull up network transitions of the output. transistor to avoid power dissipation within the Due to the transitory contention between the level converter but these feedback based level pull-up and the pull-down networks and the large converters have many disadvantages like circuit size of the NMOS transistors (M1 and M2), has slow response due to feed back circuit it also however, Feedback level converter dissipates suffers form short circuit current and trapper significant short-circuit and dynamic switching inverters are required to drive the circuit at very power. To maintain functionality with the lower low voltage this further increases the power values of VDDL, the sizes of M1 and M2 need to be consumptions, to over avoid these the novel multi- further increased in order compensate for the gate Vth based level converters are proposed. overdrive degradation. The load seen by the previous stage is therefore increased, thereby II. Implementation further degrading the speed and increasing the (a)Feedback-Based Level Converters: power consumption. Tapered buffers are required The feedback-based level converters rely to drive M1 and M2 at very low voltages. These on some form of feedback circuitry for controlling tapered buffers further increase the power the operation of the pull-up network transistors in consumption of feedback level converter. order to avoid static dc current within the level converter. In feedback-based voltage level (b) Multi-Vth level converters:The Multi-Vth converter circuits, the pull-up transistors are not level converters employ a multi-CMOS technology978-1-4244-8971-8/10$26.00 c 2010 IEEE
in order to eliminate the static dc current. The high the output node is initially charged to VDDH-Vthn-M1-threshold voltage pull-up transistors in this level Vthn-M3 and VDDL-Vthn-M1 through M1.converter are directly driven by the low levelsignals without producing a static dc current Multi-Vth level converter has fewerproblem. transistors as compared feedback level converters.(b.i) Multi-Vth Level converters (MLC1): Furthermore, the elimination of the slow feedback circuitry reduces the short-circuit power of Multi- Vth level converter as compared to feedback based level converter. No increase in the size of M1 is required for achieving functionality at lower input voltages with the proposed circuit. Therefore, particularly for the very low values of VDDL, Multi- Vth level converter consumes lower power, occupies significantly smaller area, and imposes a much smaller load capacitance. (c) Application of level converter in an integrated circuit: Figure 3: Multi-Vth Level converter (MLC1) The level converter is shown in Figure 3 MultiVth level converter is composed of two cascadedinverters with dual- transistors. The thresholdvoltage of M2(VTH-M2) is more negative (higher׀Vth )׀for avoiding static dc current in the firstinverter when the input is at VDDL.׀Vth-M2 ׀isrequired to be higher than VDDH-VDDL foreliminating the static dc current. The Multi Vthlevel converter operates as follow input is at 0 V,M2 is turned on.M1 is cutoff.Node1 is pulled up toVDDH. The output is discharged to 0 V. When the Figure 5.Circuit in which level converters areinput transitions to VDDL, M1 is turned on. M2 is inserted into needed portions.turned off since VGS, M2>VTH, M2. Node1 is Circuit with shaded portion activates in VDDLdischarged to 0 V. The output is charged to VDDH. In Figure 5 the integrated circuit has a(b.ii) Multi-Vth Level converters (MLC2): critical path from flip-flop A (FF A) to flip-flop B (FF B). Due to excessive slack in the gates or flip- flops off the critical path, the timing constraints could be met even if we partially use VDDL gates. However, the structure has a problem while implementing it in CMOS large scale integrated circuits. DC current flows at a VDDH gate due to the direct connection of a VDDL gate to a VDDH one. This becomes a problem in low-power CMOS circuits. A typical way to block the static current is to insert a level-converter circuit in between the circuit where there is direct connection for low voltage to higher voltage  . The level converter converts the voltage level from VDDL to VDDH. Figure 4: Multi-Vth Level converter (MLC2) The level converter is shown in Figure 3Multi-Vth level converter is composed of twocascaded inverters with dual- transistors. In thislevel converter when the input is at 0 V, Node 1 ispulled high to VDDL turning M2 off .The outputnode is discharged to 0 V through the passtransistor M1. When the input transitions to VDDL,
III. Results: Figure 6.Layout for the circuit of an IC in which Figure 8.Layout for the circuit of an IC in which feed back level converters are inserted into needed Multi Vth level converters are inserted into needed portions. portions.In Figure 6 Integrated circuits feed back level In Figure 8 Integrated circuits Multi Vthconverters is inserted where is a transfer of low level converters is inserted where is a transfer ofvoltage level to high voltage level to avoid the low voltage level to high voltage level to avoid thestatic current dissipation, the input is given across static current dissipation, the input is given acrossthe filp flop A and the output is take across filp the filp flop A and the output is take across filpflop B then power and delay is calculated for this flop B then power and delay is calculated for thisintegrated circuit. integrated circuit. Figure 9.Waveform for the circuit of an IC in which Multi Vth level converters are inserted into needed portions. Figure 7.Waveform for the circuit of an IC in Figure 9 shows the output waveforms of which feed back level converters are inserted into the above layout where the Multi Vth level needed portions. converters are inserted at critical region, the output is taken across filp flop B, power and delay is Figure 7 shows the output waveforms of the above calculated.layout where the feedback level converters areinserted at critical region, the output is taken acrossfilp flop B, power and delay is calculated.
power dissipation and the speed is increased. This proves the circuit that having multi threshold and multi voltage level converters will reduce the(a) Comparison of power and delay at power dissipation with out scarifying speed.different values References: Using different level converters in an  Sherif A. Tawfik and Volkan Kursun,”Lowintegrated circuit the delay and power is calculated Power and High Speed Multi Threshold Voltagefor different input voltage values. Interface Circuits,” IEEE Trans. Very Large Scale Integr. (VLSI) syst., vol 17, No.5.May2009 Optimized Optimized  Stephan Henzler, Power Management of Delay power Digital Circuits in Deep Sub-Micron CMOS VDDL Delay Power Technologies. (v) (ps) (µw)  V.Kursun and E. G. Friedman, Multi-Voltage Feedback 1.2 167 205.4 CMOS Circuit Design. New York: Wiley, 2006. level 1 234 426.4  K. Usami et al., “Automated low-power converter technique exploiting multiple supply voltages 0.8 454 620.68 applied to a media processor,” IEEE J. Solid-State Multi Vth 1.2 177 158.92 Circuits, vol. 33, no. 3, pp. 463–471, Mar. 1998. level 1 167 342.9  Y. Taur and T. H. Ning, Fundamentals of converter 0.8 234 546.2 Modern VLSI Devices. Cambridge, MA: Cambridge University Press, 1998.  S. H. Kulkarni and D. Sylvester, “High Table: 1 average propagation delay (D), and performance level conversion for dual VDD average power design,” IEEE Trans. Very Large Scale Integr. Consumption (P) of the level converters (VLSI) Syst., vol. 12, no. 9, pp. 926–936, Sep. 2004.  S. H. Kulkarni, A. N. Srivastava, and D. Sylvester, “A new algorithm for improved VDD assignment in low power dual VDD systems,” in Proc. IEEE Int. Symp. Low Power Electron. Des., Aug. 2004, pp. 200–205.  F. Ishihara, F. Sheikh, and B. Nikolic´, “Level conversion for dual supply systems,” IEEE Trans. Very Large Scale Integr. (VLSI) Syst., vol. 12, no. 2, pp. 185–195, Feb. 2004.  V. Kursun, R. M. Secareanu, and E. G. Friedman, “CMOS voltage interface circuit for low power systems,” in Proc. IEEE Int. Symp. Circuits Syst., May 2002, vol. 3, pp. 667–670.  M. Hamada et al., “A top-down low power design technique using clustered voltage scaling with variable supply-voltage scheme,” in Proc. IEEE Custom Integr. Circuits Conf., May 1998, pp. Figure 8. Plot for percentage of delay and power 495–498. with respective voltageIn the Figure 8 the power is optimized to 47% anddelay has reduced to 50% with the different inputvoltage levels.IV Conclusion: The aim of this paper is to demonstratethe successful implementation of the “Multi LevelConverter”. After a brief overview of thebackground information, design considerationswith particular interest on the selection of voltagelevel converter, the operation of the multi thresholdvoltage level converter were discussed. Thisparticularly made to decrease the power dissipationwithout affecting speed. It is found to be 47% andDelay is optimized by 50% Thus, the feedbackbased level converter is replacing with the multithreshold based level converter to decrease the